1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2021 Amlogic, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/interrupt-controller/irq.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/gpio/meson-s4-gpio.h> 10#include <dt-bindings/clock/amlogic,s4-pll-clkc.h> 11#include <dt-bindings/clock/amlogic,s4-peripherals-clkc.h> 12#include <dt-bindings/power/meson-s4-power.h> 13 14/ { 15 cpus { 16 #address-cells = <2>; 17 #size-cells = <0>; 18 19 cpu0: cpu@0 { 20 device_type = "cpu"; 21 compatible = "arm,cortex-a35"; 22 reg = <0x0 0x0>; 23 enable-method = "psci"; 24 }; 25 26 cpu1: cpu@1 { 27 device_type = "cpu"; 28 compatible = "arm,cortex-a35"; 29 reg = <0x0 0x1>; 30 enable-method = "psci"; 31 }; 32 33 cpu2: cpu@2 { 34 device_type = "cpu"; 35 compatible = "arm,cortex-a35"; 36 reg = <0x0 0x2>; 37 enable-method = "psci"; 38 }; 39 40 cpu3: cpu@3 { 41 device_type = "cpu"; 42 compatible = "arm,cortex-a35"; 43 reg = <0x0 0x3>; 44 enable-method = "psci"; 45 }; 46 }; 47 48 timer { 49 compatible = "arm,armv8-timer"; 50 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 51 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 52 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 53 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 54 }; 55 56 psci { 57 compatible = "arm,psci-1.0"; 58 method = "smc"; 59 }; 60 61 xtal: xtal-clk { 62 compatible = "fixed-clock"; 63 clock-frequency = <24000000>; 64 clock-output-names = "xtal"; 65 #clock-cells = <0>; 66 }; 67 68 pwrc: power-controller { 69 compatible = "amlogic,meson-s4-pwrc"; 70 #power-domain-cells = <1>; 71 status = "okay"; 72 }; 73 74 soc { 75 compatible = "simple-bus"; 76 #address-cells = <2>; 77 #size-cells = <2>; 78 ranges; 79 80 gic: interrupt-controller@fff01000 { 81 compatible = "arm,gic-400"; 82 #interrupt-cells = <3>; 83 #address-cells = <0>; 84 interrupt-controller; 85 reg = <0x0 0xfff01000 0 0x1000>, 86 <0x0 0xfff02000 0 0x2000>, 87 <0x0 0xfff04000 0 0x2000>, 88 <0x0 0xfff06000 0 0x2000>; 89 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 90 }; 91 92 apb4: bus@fe000000 { 93 compatible = "simple-bus"; 94 reg = <0x0 0xfe000000 0x0 0x480000>; 95 #address-cells = <2>; 96 #size-cells = <2>; 97 ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>; 98 99 clkc_periphs: clock-controller@0 { 100 compatible = "amlogic,s4-peripherals-clkc"; 101 reg = <0x0 0x0 0x0 0x49c>; 102 clocks = <&clkc_pll CLKID_FCLK_DIV2>, 103 <&clkc_pll CLKID_FCLK_DIV2P5>, 104 <&clkc_pll CLKID_FCLK_DIV3>, 105 <&clkc_pll CLKID_FCLK_DIV4>, 106 <&clkc_pll CLKID_FCLK_DIV5>, 107 <&clkc_pll CLKID_FCLK_DIV7>, 108 <&clkc_pll CLKID_HIFI_PLL>, 109 <&clkc_pll CLKID_GP0_PLL>, 110 <&clkc_pll CLKID_MPLL0>, 111 <&clkc_pll CLKID_MPLL1>, 112 <&clkc_pll CLKID_MPLL2>, 113 <&clkc_pll CLKID_MPLL3>, 114 <&clkc_pll CLKID_HDMI_PLL>, 115 <&xtal>; 116 clock-names = "fclk_div2", "fclk_div2p5", "fclk_div3", 117 "fclk_div4", "fclk_div5", "fclk_div7", 118 "hifi_pll", "gp0_pll", "mpll0", "mpll1", 119 "mpll2", "mpll3", "hdmi_pll", "xtal"; 120 #clock-cells = <1>; 121 }; 122 123 clkc_pll: clock-controller@8000 { 124 compatible = "amlogic,s4-pll-clkc"; 125 reg = <0x0 0x8000 0x0 0x1e8>; 126 clocks = <&xtal>; 127 clock-names = "xtal"; 128 #clock-cells = <1>; 129 }; 130 131 watchdog@2100 { 132 compatible = "amlogic,s4-wdt", "amlogic,t7-wdt"; 133 reg = <0x0 0x2100 0x0 0x10>; 134 clocks = <&xtal>; 135 }; 136 137 periphs_pinctrl: pinctrl@4000 { 138 compatible = "amlogic,meson-s4-periphs-pinctrl"; 139 #address-cells = <2>; 140 #size-cells = <2>; 141 ranges; 142 143 gpio: bank@4000 { 144 reg = <0x0 0x4000 0x0 0x004c>, 145 <0x0 0x40c0 0x0 0x0220>; 146 reg-names = "mux", "gpio"; 147 gpio-controller; 148 #gpio-cells = <2>; 149 gpio-ranges = <&periphs_pinctrl 0 0 82>; 150 }; 151 152 remote_pins: remote-pin { 153 mux { 154 groups = "remote_in"; 155 function = "remote_in"; 156 bias-disable; 157 }; 158 }; 159 160 i2c0_pins1: i2c0-pins1 { 161 mux { 162 groups = "i2c0_sda", 163 "i2c0_scl"; 164 function = "i2c0"; 165 drive-strength-microamp = <3000>; 166 bias-disable; 167 }; 168 }; 169 170 i2c1_pins1: i2c1-pins1 { 171 mux { 172 groups = "i2c1_sda_c", 173 "i2c1_scl_c"; 174 function = "i2c1"; 175 drive-strength-microamp = <3000>; 176 bias-disable; 177 }; 178 }; 179 180 i2c1_pins2: i2c1-pins2 { 181 mux { 182 groups = "i2c1_sda_d", 183 "i2c1_scl_d"; 184 function = "i2c1"; 185 drive-strength-microamp = <3000>; 186 bias-disable; 187 }; 188 }; 189 190 i2c1_pins3: i2c1-pins3 { 191 mux { 192 groups = "i2c1_sda_h", 193 "i2c1_scl_h"; 194 function = "i2c1"; 195 drive-strength-microamp = <3000>; 196 bias-disable; 197 }; 198 }; 199 200 i2c1_pins4: i2c1-pins4 { 201 mux { 202 groups = "i2c1_sda_x", 203 "i2c1_scl_x"; 204 function = "i2c1"; 205 drive-strength-microamp = <3000>; 206 bias-disable; 207 }; 208 }; 209 210 i2c2_pins1: i2c2-pins1 { 211 mux { 212 groups = "i2c2_sda_d", 213 "i2c2_scl_d"; 214 function = "i2c2"; 215 drive-strength-microamp = <3000>; 216 bias-disable; 217 }; 218 }; 219 220 i2c2_pins2: i2c2-pins2 { 221 mux { 222 groups = "i2c2_sda_h8", 223 "i2c2_scl_h9"; 224 function = "i2c2"; 225 drive-strength-microamp = <3000>; 226 bias-disable; 227 }; 228 }; 229 230 i2c2_pins3: i2c2-pins3 { 231 mux { 232 groups = "i2c2_sda_h0", 233 "i2c2_scl_h1"; 234 function = "i2c2"; 235 drive-strength-microamp = <3000>; 236 bias-disable; 237 }; 238 }; 239 240 i2c3_pins1: i2c3-pins1 { 241 mux { 242 groups = "i2c3_sda_x", 243 "i2c3_scl_x"; 244 function = "i2c3"; 245 drive-strength-microamp = <3000>; 246 bias-disable; 247 }; 248 }; 249 250 i2c3_pins2: i2c3-pins2 { 251 mux { 252 groups = "i2c3_sda_z", 253 "i2c3_scl_z"; 254 function = "i2c3"; 255 drive-strength-microamp = <3000>; 256 bias-disable; 257 }; 258 }; 259 260 i2c4_pins1: i2c4-pins1 { 261 mux { 262 groups = "i2c4_sda_c", 263 "i2c4_scl_c"; 264 function = "i2c4"; 265 drive-strength-microamp = <3000>; 266 bias-disable; 267 }; 268 }; 269 270 i2c4_pins2: i2c4-pins2 { 271 mux { 272 groups = "i2c4_sda_d", 273 "i2c4_scl_d"; 274 function = "i2c4"; 275 drive-strength-microamp = <3000>; 276 bias-disable; 277 }; 278 }; 279 280 i2c4_pins3: i2c4-pins3 { 281 mux { 282 groups = "i2c4_sda_z", 283 "i2c4_scl_z"; 284 function = "i2c4"; 285 drive-strength-microamp = <3000>; 286 bias-disable; 287 }; 288 }; 289 290 nand_pins: nand-pins { 291 mux { 292 groups = "emmc_nand_d0", 293 "emmc_nand_d1", 294 "emmc_nand_d2", 295 "emmc_nand_d3", 296 "emmc_nand_d4", 297 "emmc_nand_d5", 298 "emmc_nand_d6", 299 "emmc_nand_d7", 300 "nand_ce0", 301 "nand_ale", 302 "nand_cle", 303 "nand_wen_clk", 304 "nand_ren_wr"; 305 function = "nand"; 306 input-enable; 307 }; 308 }; 309 310 spicc0_pins_x: spicc0-pins_x { 311 mux { 312 groups = "spi_a_mosi_x", 313 "spi_a_miso_x", 314 "spi_a_clk_x"; 315 function = "spi_a"; 316 drive-strength-microamp = <3000>; 317 }; 318 }; 319 320 spicc0_pins_h: spicc0-pins-h { 321 mux { 322 groups = "spi_a_mosi_h", 323 "spi_a_miso_h", 324 "spi_a_clk_h"; 325 function = "spi_a"; 326 drive-strength-microamp = <3000>; 327 }; 328 }; 329 330 spicc0_pins_z: spicc0-pins-z { 331 mux { 332 groups = "spi_a_mosi_z", 333 "spi_a_miso_z", 334 "spi_a_clk_z"; 335 function = "spi_a"; 336 drive-strength-microamp = <3000>; 337 }; 338 }; 339 340 }; 341 342 gpio_intc: interrupt-controller@4080 { 343 compatible = "amlogic,meson-s4-gpio-intc", 344 "amlogic,meson-gpio-intc"; 345 reg = <0x0 0x4080 0x0 0x20>; 346 interrupt-controller; 347 #interrupt-cells = <2>; 348 amlogic,channel-interrupts = 349 <10 11 12 13 14 15 16 17 18 19 20 21>; 350 }; 351 352 eth_phy: mdio-multiplexer@28000 { 353 compatible = "amlogic,g12a-mdio-mux"; 354 reg = <0x0 0x28000 0x0 0xa4>; 355 356 #address-cells = <1>; 357 #size-cells = <0>; 358 clocks = <&clkc_periphs CLKID_ETHPHY>, 359 <&xtal>, 360 <&clkc_pll CLKID_MPLL_50M>; 361 clock-names = "pclk", "clkin0", "clkin1"; 362 mdio-parent-bus = <&mdio0>; 363 364 ext_mdio: mdio@0 { 365 reg = <0>; 366 #address-cells = <1>; 367 #size-cells = <0>; 368 }; 369 370 int_mdio: mdio@1 { 371 reg = <1>; 372 #address-cells = <1>; 373 #size-cells = <0>; 374 375 internal_ephy: ethernet-phy@8 { 376 compatible = "ethernet-phy-id0180.3301", 377 "ethernet-phy-ieee802.3-c22"; 378 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 379 reg = <8>; 380 max-speed = <100>; 381 }; 382 }; 383 }; 384 385 spicc0: spi@50000 { 386 compatible = "amlogic,meson-g12a-spicc"; 387 reg = <0x0 0x50000 0x0 0x44>; 388 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 389 clocks = <&clkc_periphs CLKID_SPICC0>, 390 <&clkc_periphs CLKID_SPICC0_EN>; 391 clock-names = "core", "pclk"; 392 #address-cells = <1>; 393 #size-cells = <0>; 394 status = "disabled"; 395 }; 396 397 i2c0: i2c@66000 { 398 compatible = "amlogic,meson-axg-i2c"; 399 reg = <0x0 0x66000 0x0 0x20>; 400 interrupts = <GIC_SPI 160 IRQ_TYPE_EDGE_RISING>; 401 clocks = <&clkc_periphs CLKID_I2C_M_A>; 402 #address-cells = <1>; 403 #size-cells = <0>; 404 status = "disabled"; 405 }; 406 407 i2c1: i2c@68000 { 408 compatible = "amlogic,meson-axg-i2c"; 409 reg = <0x0 0x68000 0x0 0x20>; 410 interrupts = <GIC_SPI 161 IRQ_TYPE_EDGE_RISING>; 411 clocks = <&clkc_periphs CLKID_I2C_M_B>; 412 #address-cells = <1>; 413 #size-cells = <0>; 414 status = "disabled"; 415 }; 416 417 i2c2: i2c@6a000 { 418 compatible = "amlogic,meson-axg-i2c"; 419 reg = <0x0 0x6a000 0x0 0x20>; 420 interrupts = <GIC_SPI 162 IRQ_TYPE_EDGE_RISING>; 421 clocks = <&clkc_periphs CLKID_I2C_M_C>; 422 #address-cells = <1>; 423 #size-cells = <0>; 424 status = "disabled"; 425 }; 426 427 i2c3: i2c@6c000 { 428 compatible = "amlogic,meson-axg-i2c"; 429 reg = <0x0 0x6c000 0x0 0x20>; 430 interrupts = <GIC_SPI 163 IRQ_TYPE_EDGE_RISING>; 431 clocks = <&clkc_periphs CLKID_I2C_M_D>; 432 #address-cells = <1>; 433 #size-cells = <0>; 434 status = "disabled"; 435 }; 436 437 i2c4: i2c@6e000 { 438 compatible = "amlogic,meson-axg-i2c"; 439 reg = <0x0 0x6e000 0x0 0x20>; 440 interrupts = <GIC_SPI 164 IRQ_TYPE_EDGE_RISING>; 441 clocks = <&clkc_periphs CLKID_I2C_M_E>; 442 #address-cells = <1>; 443 #size-cells = <0>; 444 status = "disabled"; 445 }; 446 447 nand: nand-controller@8c800 { 448 compatible = "amlogic,meson-axg-nfc"; 449 reg = <0x0 0x8c800 0x0 0x100>, <0x0 0x8c000 0x0 0x4>; 450 reg-names = "nfc", "emmc"; 451 interrupts = <GIC_SPI 175 IRQ_TYPE_EDGE_RISING>; 452 clocks = <&clkc_periphs CLKID_SD_EMMC_C>, 453 <&clkc_pll CLKID_FCLK_DIV2>; 454 clock-names = "core", "device"; 455 status = "disabled"; 456 }; 457 458 uart_b: serial@7a000 { 459 compatible = "amlogic,meson-s4-uart", 460 "amlogic,meson-ao-uart"; 461 reg = <0x0 0x7a000 0x0 0x18>; 462 interrupts = <GIC_SPI 169 IRQ_TYPE_EDGE_RISING>; 463 clocks = <&xtal>, <&clkc_periphs CLKID_UART_B>, <&xtal>; 464 clock-names = "xtal", "pclk", "baud"; 465 status = "disabled"; 466 }; 467 468 reset: reset-controller@2000 { 469 compatible = "amlogic,meson-s4-reset"; 470 reg = <0x0 0x2000 0x0 0x98>; 471 #reset-cells = <1>; 472 }; 473 474 ir: ir@84040 { 475 compatible = "amlogic,meson-s4-ir"; 476 reg = <0x0 0x84040 0x0 0x30>; 477 interrupts = <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; 478 status = "disabled"; 479 }; 480 481 hwrng: rng@440788 { 482 compatible = "amlogic,meson-s4-rng"; 483 reg = <0x0 0x440788 0x0 0x0c>; 484 }; 485 }; 486 487 ethmac: ethernet@fdc00000 { 488 compatible = "amlogic,meson-axg-dwmac", 489 "snps,dwmac-3.70a", 490 "snps,dwmac"; 491 reg = <0x0 0xfdc00000 0x0 0x10000>, 492 <0x0 0xfe024000 0x0 0x8>; 493 494 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 495 interrupt-names = "macirq"; 496 power-domains = <&pwrc PWRC_S4_ETH_ID>; 497 clocks = <&clkc_periphs CLKID_ETH>, 498 <&clkc_pll CLKID_FCLK_DIV2>, 499 <&clkc_pll CLKID_MPLL2>; 500 clock-names = "stmmaceth", "clkin0", "clkin1"; 501 rx-fifo-depth = <4096>; 502 tx-fifo-depth = <2048>; 503 status = "disabled"; 504 505 mdio0: mdio { 506 #address-cells = <1>; 507 #size-cells = <0>; 508 compatible = "snps,dwmac-mdio"; 509 }; 510 }; 511 }; 512}; 513