Lines Matching +full:0 +full:x4080
45 * SoC Integrated devices: 0xF1000000, 16 MB (VA == PA)
49 #define MV_PHYS_BASE 0xF1000000
53 #define MV_CESA_SRAM_BASE 0xF1100000
56 * External devices: 0x80000000, 1 GB (VA == PA)
62 #define MV_PCI_MEM_PHYS_BASE 0x80000000
67 #define MV_PCI_IO_PHYS_BASE 0xBF000000
71 #define MV_PCI_VA_MEM_BASE 0
72 #define MV_PCI_VA_IO_BASE 0
77 #define MV_DEV_BOOT_BASE 0xF9300000
80 #define MV_DEV_CS0_BASE 0xF9400000
83 #define MV_DEV_CS1_BASE 0xF9500000
86 #define MV_DEV_CS2_BASE 0xFB500000
93 #define MV_DDR_CADR_BASE_ARMV7 (MV_BASE + 0x20180)
94 #define MV_DDR_CADR_BASE (MV_BASE + 0x1500)
95 #define MV_MPP_BASE (MV_BASE + 0x10000)
97 #define MV_MISC_BASE (MV_BASE + 0x18200)
98 #define MV_MBUS_BRIDGE_BASE (MV_BASE + 0x20000)
99 #define MV_INTREGS_BASE (MV_MBUS_BRIDGE_BASE + 0x80)
100 #define MV_MP_CLOCKS_BASE (MV_MBUS_BRIDGE_BASE + 0x700)
102 #define MV_CPU_CONTROL_BASE_ARMV7 (MV_MBUS_BRIDGE_BASE + 0x1800)
103 #define MV_CPU_CONTROL_BASE (MV_MBUS_BRIDGE_BASE + 0x100)
105 #define MV_PCI_BASE (MV_BASE + 0x30000)
106 #define MV_PCI_SIZE 0x2000
108 #define MV_PCIE_BASE_ARMADA38X (MV_BASE + 0x80000)
109 #define MV_PCIE_BASE (MV_BASE + 0x40000)
110 #define MV_PCIE_SIZE 0x2000
111 #define MV_SDIO_BASE (MV_BASE + 0x90000)
112 #define MV_SDIO_SIZE 0x10000
117 #define MV_WIN_CPU_CTRL_ARMV7(n) (((n) < 8) ? 0x10 * (n) : 0x90 + (0x8 * ((n) - 8)))
118 #define MV_WIN_CPU_BASE_ARMV7(n) ((((n) < 8) ? 0x10 * (n) : 0x90 + (0x8 * ((n) - 8))) + 0x4)
119 #define MV_WIN_CPU_REMAP_LO_ARMV7(n) (0x10 * (n) + 0x008)
120 #define MV_WIN_CPU_REMAP_HI_ARMV7(n) (0x10 * (n) + 0x00C)
122 #define MV_WIN_CPU_CTRL_ARMV5(n) (0x10 * (n) + (((n) < 8) ? 0x000 : 0x880))
123 #define MV_WIN_CPU_BASE_ARMV5(n) (0x10 * (n) + (((n) < 8) ? 0x004 : 0x884))
124 #define MV_WIN_CPU_REMAP_LO_ARMV5(n) (0x10 * (n) + (((n) < 8) ? 0x008 : 0x888))
125 #define MV_WIN_CPU_REMAP_HI_ARMV5(n) (0x10 * (n) + (((n) < 8) ? 0x00C : 0x88C))
134 #define MV_WIN_DDR_BASE(n) (0x8 * (n) + 0x0)
135 #define MV_WIN_DDR_SIZE(n) (0x8 * (n) + 0x4)
142 #define MV_WIN_DDR_ATTR(cs) (0x0F & ~(0x01 << (cs)))
143 #define MV_WIN_DDR_TARGET 0x0
146 #define MV_WIN_CESA_ATTR(eng_sel) 0
158 * Bits [1:0] = Data swapping
159 * 0x0 = Byte swap
160 * 0x1 = No swap
161 * 0x2 = Byte and word swap
162 * 0x3 = Word swap
164 * 0x6 = CESA0
165 * 0x5 = CESA1
167 #define MV_WIN_CESA_ATTR_ARMADA38X(eng_sel) (0x11 | (1 << (3 - (eng_sel))))
169 #define MV_WIN_CESA_CTRL(n) (0x8 * (n) + 0xA04)
170 #define MV_WIN_CESA_BASE(n) (0x8 * (n) + 0xA00)
173 #define MV_WIN_USB_CTRL(n) (0x10 * (n) + 0x320)
174 #define MV_WIN_USB_BASE(n) (0x10 * (n) + 0x324)
177 #define MV_WIN_USB3_CTRL(n) (0x8 * (n) + 0x4000)
178 #define MV_WIN_USB3_BASE(n) (0x8 * (n) + 0x4004)
181 #define MV_WIN_NETA_OFFSET 0x2000
184 #define MV_WIN_CESA_OFFSET 0x2000
186 #define MV_WIN_ETH_BASE(n) (0x8 * (n) + 0x200)
187 #define MV_WIN_ETH_SIZE(n) (0x8 * (n) + 0x204)
188 #define MV_WIN_ETH_REMAP(n) (0x4 * (n) + 0x280)
191 #define MV_WIN_IDMA_BASE(n) (0x8 * (n) + 0xa00)
192 #define MV_WIN_IDMA_SIZE(n) (0x8 * (n) + 0xa04)
193 #define MV_WIN_IDMA_REMAP(n) (0x4 * (n) + 0xa60)
194 #define MV_WIN_IDMA_CAP(n) (0x4 * (n) + 0xa70)
198 #define MV_WIN_XOR_BASE(n, m) (0x4 * (n) + 0xa50 + (m) * 0x100)
199 #define MV_WIN_XOR_SIZE(n, m) (0x4 * (n) + 0xa70 + (m) * 0x100)
200 #define MV_WIN_XOR_REMAP(n, m) (0x4 * (n) + 0xa90 + (m) * 0x100)
201 #define MV_WIN_XOR_CTRL(n, m) (0x4 * (n) + 0xa40 + (m) * 0x100)
202 #define MV_WIN_XOR_OVERR(n, m) (0x4 * (n) + 0xaa0 + (m) * 0x100)
208 #define MV_WIN_PCIE_MEM_ATTR_ARMADAXP(n) (0xE8 + (0x10 * ((n) / 2)))
209 #define MV_WIN_PCIE_IO_ATTR_ARMADAXP(n) (0xE0 + (0x10 * ((n) / 2)))
210 #define MV_WIN_PCIE_TARGET_ARMADA38X(n) ((n) == 0 ? 8 : 4)
211 #define MV_WIN_PCIE_MEM_ATTR_ARMADA38X(n) ((n) < 2 ? 0xE8 : (0xD8 - (((n) % 2) * 0x20)))
212 #define MV_WIN_PCIE_IO_ATTR_ARMADA38X(n) ((n) < 2 ? 0xE0 : (0xD0 - (((n) % 2) * 0x20)))
214 #define MV_WIN_PCIE_MEM_ATTR(n) (0xE8 + (0x10 * ((n) / 2)))
215 #define MV_WIN_PCIE_IO_ATTR(n) (0xE0 + (0x10 * ((n) / 2)))
218 #define MV_WIN_PCI_MEM_ATTR 0x59
219 #define MV_WIN_PCI_IO_ATTR 0x51
221 #define MV_WIN_PCIE_CTRL(n) (0x10 * (((n) < 5) ? (n) : \
222 (n) + 1) + 0x1820)
223 #define MV_WIN_PCIE_BASE(n) (0x10 * (((n) < 5) ? (n) : \
224 (n) + 1) + 0x1824)
225 #define MV_WIN_PCIE_REMAP(n) (0x10 * (((n) < 5) ? (n) : \
226 (n) + 1) + 0x182C)
229 #define MV_PCIE_BAR_CTRL(n) (0x04 * (n) + 0x1800)
230 #define MV_PCIE_BAR_BASE(n) (0x08 * ((n) < 3 ? (n) : 4) + 0x0010)
231 #define MV_PCIE_BAR_BASE_H(n) (0x08 * (n) + 0x0014)
233 #define MV_PCIE_BAR_64BIT (0x4)
234 #define MV_PCIE_BAR_PREFETCH_EN (0x8)
236 #define MV_PCIE_CONTROL (0x1a00)
239 #define MV_WIN_SATA_CTRL_ARMADA38X(n) (0x10 * (n) + 0x60)
240 #define MV_WIN_SATA_BASE_ARMADA38X(n) (0x10 * (n) + 0x64)
241 #define MV_WIN_SATA_SIZE_ARMADA38X(n) (0x10 * (n) + 0x68)
243 #define MV_WIN_SATA_CTRL(n) (0x10 * (n) + 0x30)
244 #define MV_WIN_SATA_BASE(n) (0x10 * (n) + 0x34)
247 #define MV_WIN_SDHCI_CTRL(n) (0x8 * (n) + 0x4080)
248 #define MV_WIN_SDHCI_BASE(n) (0x8 * (n) + 0x4084)
251 #define MV_BOOTROM_MEM_ADDR 0xFFF00000
252 #define MV_BOOTROM_WIN_SIZE 0xF
253 #define MV_CPU_SUBSYS_REGS_LEN 0x100
255 #define IO_WIN_9_CTRL_OFFSET 0x98
256 #define IO_WIN_9_BASE_OFFSET 0x9C
259 #define MBUS_BOOTROM_TGT_ID 0x1
260 #define MBUS_BOOTROM_ATTR 0x1D
263 #define MV_SYNC_BARRIER_CTRL 0x84
264 #define MV_SYNC_BARRIER_CTRL_ALL 0xFFFF
268 #define IO_WIN_SIZE_MASK 0xFFFF
269 #define IO_WIN_COH_ATTR_MASK (0xF << 12)
271 #define IO_WIN_ATTR_MASK 0xFF
273 #define IO_WIN_TGT_MASK 0xF
275 #define IO_WIN_SYNC_MASK 0x1
276 #define IO_WIN_ENA_SHIFT 0
277 #define IO_WIN_ENA_MASK 0x1