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/linux/drivers/media/rc/keymaps/
H A Drc-ct-90405.c5 * Copyright (C) 2021 Alexander Voronov <avv.0@ya.ru>
12 { 0x4014, KEY_SWITCHVIDEOMODE },
13 { 0x4012, KEY_POWER },
14 { 0x4044, KEY_TV },
15 { 0x40be43, KEY_3D_MODE },
16 { 0x400c, KEY_SUBTITLE },
17 { 0x4001, KEY_NUMERIC_1 },
18 { 0x4002, KEY_NUMERIC_2 },
19 { 0x4003, KEY_NUMERIC_3 },
20 { 0x4004, KEY_NUMERIC_4 },
[all …]
/linux/drivers/input/touchscreen/
H A Dgoodix.h13 #define GOODIX_REG_MISCTL_DSP_CTL 0x4010
14 #define GOODIX_REG_MISCTL_SRAM_BANK 0x4048
15 #define GOODIX_REG_MISCTL_MEM_CD_EN 0x4049
16 #define GOODIX_REG_MISCTL_CACHE_EN 0x404B
17 #define GOODIX_REG_MISCTL_TMR0_EN 0x40B0
18 #define GOODIX_REG_MISCTL_SWRST 0x4180
19 #define GOODIX_REG_MISCTL_CPU_SWRST_PULSE 0x4184
20 #define GOODIX_REG_MISCTL_BOOTCTL 0x4190
21 #define GOODIX_REG_MISCTL_BOOT_OPT 0x4218
22 #define GOODIX_REG_MISCTL_BOOT_CTL 0x5094
[all …]
/linux/sound/soc/codecs/
H A Dadau17x1.h72 #define ADAU17X1_CLOCK_CONTROL 0x4000
73 #define ADAU17X1_PLL_CONTROL 0x4002
74 #define ADAU17X1_REC_POWER_MGMT 0x4009
75 #define ADAU17X1_MICBIAS 0x4010
76 #define ADAU17X1_SERIAL_PORT0 0x4015
77 #define ADAU17X1_SERIAL_PORT1 0x4016
78 #define ADAU17X1_CONVERTER0 0x4017
79 #define ADAU17X1_CONVERTER1 0x4018
80 #define ADAU17X1_LEFT_INPUT_DIGITAL_VOL 0x401a
81 #define ADAU17X1_RIGHT_INPUT_DIGITAL_VOL 0x401b
[all …]
/linux/arch/parisc/include/uapi/asm/
H A Dsocket.h9 #define SOL_SOCKET 0xffff
11 #define SO_DEBUG 0x0001
12 #define SO_REUSEADDR 0x0004
13 #define SO_KEEPALIVE 0x0008
14 #define SO_DONTROUTE 0x0010
15 #define SO_BROADCAST 0x0020
16 #define SO_LINGER 0x0080
17 #define SO_OOBINLINE 0x0100
18 #define SO_REUSEPORT 0x0200
19 #define SO_SNDBUF 0x1001
[all …]
/linux/drivers/ntb/hw/intel/
H A Dntb_hw_gen3.h50 #define GEN3_IMBAR1SZ_OFFSET 0x00d0
51 #define GEN3_IMBAR2SZ_OFFSET 0x00d1
52 #define GEN3_EMBAR1SZ_OFFSET 0x00d2
53 #define GEN3_EMBAR2SZ_OFFSET 0x00d3
54 #define GEN3_DEVCTRL_OFFSET 0x0098
55 #define GEN3_DEVSTS_OFFSET 0x009a
56 #define GEN3_UNCERRSTS_OFFSET 0x014c
57 #define GEN3_CORERRSTS_OFFSET 0x0158
58 #define GEN3_LINK_STATUS_OFFSET 0x01a2
60 #define GEN3_NTBCNTL_OFFSET 0x0000
[all …]
/linux/Documentation/devicetree/bindings/arm/apple/
H A Dapple,pmgr.yaml20 pattern: "^power-management@[0-9a-f]+$"
42 "power-controller@[0-9a-f]+$":
64 reg = <0x2 0x3b700000 0x0 0x14000>;
68 reg = <0x1c0 8>;
69 #power-domain-cells = <0>;
70 #reset-cells = <0>;
77 reg = <0x220 8>;
78 #power-domain-cells = <0>;
79 #reset-cells = <0>;
86 reg = <0x270 8>;
[all …]
/linux/drivers/net/ethernet/tehuti/
H A Dtn40_regs.h8 #define TN40_REGS_SIZE 0x10000
10 /* Registers from 0x0000-0x00fc were remapped to 0x4000-0x40fc */
11 #define TN40_REG_TXD_CFG1_0 0x4000
12 #define TN40_REG_TXD_CFG1_1 0x4004
13 #define TN40_REG_TXD_CFG1_2 0x4008
14 #define TN40_REG_TXD_CFG1_3 0x400C
16 #define TN40_REG_RXF_CFG1_0 0x4010
17 #define TN40_REG_RXF_CFG1_1 0x4014
18 #define TN40_REG_RXF_CFG1_2 0x4018
19 #define TN40_REG_RXF_CFG1_3 0x401C
[all …]
/linux/drivers/gpu/drm/radeon/reg_srcs/
H A Drv5151 rv515 0x6d40
2 0x1434 SRC_Y_X
3 0x1438 DST_Y_X
4 0x143C DST_HEIGHT_WIDTH
5 0x146C DP_GUI_MASTER_CNTL
6 0x1474 BRUSH_Y_X
7 0x1478 DP_BRUSH_BKGD_CLR
8 0x147C DP_BRUSH_FRGD_CLR
9 0x1480 BRUSH_DATA0
10 0x1484 BRUSH_DATA1
[all …]
H A Dr3001 r300 0x4f60
2 0x1434 SRC_Y_X
3 0x1438 DST_Y_X
4 0x143C DST_HEIGHT_WIDTH
5 0x146C DP_GUI_MASTER_CNTL
6 0x1474 BRUSH_Y_X
7 0x1478 DP_BRUSH_BKGD_CLR
8 0x147C DP_BRUSH_FRGD_CLR
9 0x1480 BRUSH_DATA0
10 0x1484 BRUSH_DATA1
[all …]
H A Drs6001 rs600 0x6d40
2 0x1434 SRC_Y_X
3 0x1438 DST_Y_X
4 0x143C DST_HEIGHT_WIDTH
5 0x146C DP_GUI_MASTER_CNTL
6 0x1474 BRUSH_Y_X
7 0x1478 DP_BRUSH_BKGD_CLR
8 0x147C DP_BRUSH_FRGD_CLR
9 0x1480 BRUSH_DATA0
10 0x1484 BRUSH_DATA1
[all …]
H A Dr4201 r420 0x4f60
2 0x1434 SRC_Y_X
3 0x1438 DST_Y_X
4 0x143C DST_HEIGHT_WIDTH
5 0x146C DP_GUI_MASTER_CNTL
6 0x1474 BRUSH_Y_X
7 0x1478 DP_BRUSH_BKGD_CLR
8 0x147C DP_BRUSH_FRGD_CLR
9 0x1480 BRUSH_DATA0
10 0x1484 BRUSH_DATA1
[all …]
/linux/drivers/net/fddi/skfp/h/
H A Dsmt_p.h19 #define SMT_P0012 0x0012
21 #define SMT_P0015 0x0015
22 #define SMT_P0016 0x0016
23 #define SMT_P0017 0x0017
24 #define SMT_P0018 0x0018
25 #define SMT_P0019 0x0019
27 #define SMT_P001A 0x001a
28 #define SMT_P001B 0x001b
29 #define SMT_P001C 0x001c
30 #define SMT_P001D 0x001d
[all …]
/linux/include/video/
H A Dpermedia2.h17 #define PM2_REGS_SIZE 0x10000
19 #define PM2TAG(r) (u32 )(((r)-0x8000)>>3)
25 #define PM2R_RESET_STATUS 0x0000
26 #define PM2R_IN_FIFO_SPACE 0x0018
27 #define PM2R_OUT_FIFO_WORDS 0x0020
28 #define PM2R_APERTURE_ONE 0x0050
29 #define PM2R_APERTURE_TWO 0x0058
30 #define PM2R_FIFO_DISCON 0x0068
31 #define PM2R_CHIP_CONFIG 0x0070
33 #define PM2R_REBOOT 0x1000
[all …]
/linux/tools/include/perf/
H A Darm_pmuv3.h18 #define ARMV8_PMUV3_PERFCTR_SW_INCR 0x0000
19 #define ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL 0x0001
20 #define ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL 0x0002
21 #define ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL 0x0003
22 #define ARMV8_PMUV3_PERFCTR_L1D_CACHE 0x0004
23 #define ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL 0x0005
24 #define ARMV8_PMUV3_PERFCTR_LD_RETIRED 0x0006
25 #define ARMV8_PMUV3_PERFCTR_ST_RETIRED 0x0007
26 #define ARMV8_PMUV3_PERFCTR_INST_RETIRED 0x0008
27 #define ARMV8_PMUV3_PERFCTR_EXC_TAKEN 0x0009
[all …]
/linux/include/linux/perf/
H A Darm_pmuv3.h16 #define ARMV8_PMUV3_PERFCTR_SW_INCR 0x0000
17 #define ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL 0x0001
18 #define ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL 0x0002
19 #define ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL 0x0003
20 #define ARMV8_PMUV3_PERFCTR_L1D_CACHE 0x0004
21 #define ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL 0x0005
22 #define ARMV8_PMUV3_PERFCTR_LD_RETIRED 0x0006
23 #define ARMV8_PMUV3_PERFCTR_ST_RETIRED 0x0007
24 #define ARMV8_PMUV3_PERFCTR_INST_RETIRED 0x0008
25 #define ARMV8_PMUV3_PERFCTR_EXC_TAKEN 0x0009
[all …]
/linux/drivers/net/usb/
H A Dpegasus.h9 #define PEGASUS_II 0x80000000
10 #define HAS_HOME_PNA 0x40000000
14 #define EPROM_WRITE 0x01
15 #define EPROM_READ 0x02
16 #define EPROM_DONE 0x04
17 #define EPROM_WR_ENABLE 0x10
18 #define EPROM_LOAD 0x20
20 #define PHY_DONE 0x80
21 #define PHY_READ 0x40
22 #define PHY_WRITE 0x20
[all …]
/linux/arch/arm/boot/dts/nxp/mxs/
H A Dimx28-pinfunc.h13 #define MX28_PAD_GPMI_D00__GPMI_D0 0x0000
14 #define MX28_PAD_GPMI_D01__GPMI_D1 0x0010
15 #define MX28_PAD_GPMI_D02__GPMI_D2 0x0020
16 #define MX28_PAD_GPMI_D03__GPMI_D3 0x0030
17 #define MX28_PAD_GPMI_D04__GPMI_D4 0x0040
18 #define MX28_PAD_GPMI_D05__GPMI_D5 0x0050
19 #define MX28_PAD_GPMI_D06__GPMI_D6 0x0060
20 #define MX28_PAD_GPMI_D07__GPMI_D7 0x0070
21 #define MX28_PAD_GPMI_CE0N__GPMI_CE0N 0x0100
22 #define MX28_PAD_GPMI_CE1N__GPMI_CE1N 0x0110
[all …]
/linux/arch/sh/include/asm/
H A Dhd64461.h10 * (please note manual reference 0x10000000 = 0xb0000000)
14 #define HD64461_PCC_WINDOW 0x01000000
16 /* Area 6 - Slot 0 - memory and/or IO card */
17 #define HD64461_IOBASE 0xb0000000
19 #define HD64461_PCC0_BASE HD64461_IO_OFFSET(0x8000000)
20 #define HD64461_PCC0_ATTR (HD64461_PCC0_BASE) /* 0xb80000000 */
21 #define HD64461_PCC0_COMM (HD64461_PCC0_BASE+HD64461_PCC_WINDOW) /* 0xb90000000 */
22 #define HD64461_PCC0_IO (HD64461_PCC0_BASE+2*HD64461_PCC_WINDOW) /* 0xba0000000 */
25 #define HD64461_PCC1_BASE HD64461_IO_OFFSET(0x4000000)
26 #define HD64461_PCC1_ATTR (HD64461_PCC1_BASE) /* 0xb4000000 */
[all …]
/linux/drivers/net/can/sja1000/
H A Dems_pci.c50 #define PITA2_ICR 0x00 /* Interrupt Control Register */
51 #define PITA2_ICR_INT0 0x00000002 /* [RC] INT0 Active/Clear */
52 #define PITA2_ICR_INT0_EN 0x00020000 /* [RW] Enable INT0 */
54 #define PITA2_MISC 0x1c /* Miscellaneous Register */
55 #define PITA2_MISC_CONFIG 0x04000000 /* Multiplexed parallel interface */
59 #define PLX_ICSR 0x4c /* Interrupt Control/Status register */
60 #define PLX_ICSR_LINTI1_ENA 0x0001 /* LINTi1 Enable */
61 #define PLX_ICSR_PCIINT_ENA 0x0040 /* PCI Interrupt Enable */
62 #define PLX_ICSR_LINTI1_CLR 0x0400 /* Local Edge Triggerable Interrupt Clear */
68 #define ASIX_LINTSR 0x28 /* Interrupt Control/Status register */
[all …]
/linux/drivers/media/i2c/
H A Dog01a1b.c27 #define OG01A1B_REG_CHIP_ID 0x300a
28 #define OG01A1B_CHIP_ID 0x470141
30 #define OG01A1B_REG_MODE_SELECT 0x0100
31 #define OG01A1B_MODE_STANDBY 0x00
32 #define OG01A1B_MODE_STREAMING 0x01
35 #define OG01A1B_REG_VTS 0x380e
36 #define OG01A1B_VTS_120FPS 0x0498
37 #define OG01A1B_VTS_120FPS_MIN 0x0498
38 #define OG01A1B_VTS_MAX 0x7fff
41 #define OG01A1B_REG_HTS 0x380c
[all …]
/linux/include/linux/mfd/wm831x/
H A Dcore.h25 #define WM831X_RESET_ID 0x00
26 #define WM831X_REVISION 0x01
27 #define WM831X_PARENT_ID 0x4000
28 #define WM831X_SYSVDD_CONTROL 0x4001
29 #define WM831X_THERMAL_MONITORING 0x4002
30 #define WM831X_POWER_STATE 0x4003
31 #define WM831X_WATCHDOG 0x4004
32 #define WM831X_ON_PIN_CONTROL 0x4005
33 #define WM831X_RESET_CONTROL 0x4006
34 #define WM831X_CONTROL_INTERFACE 0x4007
[all …]
/linux/include/linux/
H A DmISDNif.h43 * <16 bit 0 >
58 #define MISDN_CMDMASK 0xff00
59 #define MISDN_LAYERMASK 0x00ff
62 #define OPEN_CHANNEL 0x0100
63 #define CLOSE_CHANNEL 0x0200
64 #define CONTROL_CHANNEL 0x0300
65 #define CHECK_DATA 0x0400
68 #define PH_ACTIVATE_REQ 0x0101
69 #define PH_DEACTIVATE_REQ 0x0201
70 #define PH_DATA_REQ 0x2001
[all …]
/linux/tools/perf/pmu-events/arch/x86/westmereex/
H A Dmemory.json4 "Counter": "0,1,2,3",
5 "EventCode": "0x5",
8 "UMask": "0x2"
13 "EventCode": "0xB7",
15 "MSRIndex": "0x1A6",
16 "MSRValue": "0x6011",
18 "UMask": "0x1"
23 "EventCode": "0xB7",
25 "MSRIndex": "0x1A6",
26 "MSRValue": "0xF811",
[all …]
/linux/tools/perf/pmu-events/arch/x86/nehalemex/
H A Dmemory.json5 "EventCode": "0xB7",
7 "MSRIndex": "0x1A6",
8 "MSRValue": "0x6011",
10 "UMask": "0x1"
15 "EventCode": "0xB7",
17 "MSRIndex": "0x1A6",
18 "MSRValue": "0xF811",
20 "UMask": "0x1"
25 "EventCode": "0xB7",
27 "MSRIndex": "0x1A6",
[all …]
/linux/tools/perf/pmu-events/arch/x86/nehalemep/
H A Dmemory.json5 "EventCode": "0xB7",
7 "MSRIndex": "0x1A6",
8 "MSRValue": "0x6011",
10 "UMask": "0x1"
15 "EventCode": "0xB7",
17 "MSRIndex": "0x1A6",
18 "MSRValue": "0xF811",
20 "UMask": "0x1"
25 "EventCode": "0xB7",
27 "MSRIndex": "0x1A6",
[all …]

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