xref: /linux/sound/soc/codecs/adau17x1.h (revision 4f2c0a4acffbec01079c28f839422e64ddeff004)
1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */
24101866cSLars-Peter Clausen #ifndef __ADAU17X1_H__
34101866cSLars-Peter Clausen #define __ADAU17X1_H__
44101866cSLars-Peter Clausen 
54101866cSLars-Peter Clausen #include <linux/regmap.h>
64101866cSLars-Peter Clausen #include <linux/platform_data/adau17x1.h>
74101866cSLars-Peter Clausen 
8d48b088eSLars-Peter Clausen #include "sigmadsp.h"
9d48b088eSLars-Peter Clausen 
104101866cSLars-Peter Clausen enum adau17x1_type {
114101866cSLars-Peter Clausen 	ADAU1361,
124101866cSLars-Peter Clausen 	ADAU1761,
13*c7b92395SRicard Wanderlof 	ADAU1761_AS_1361,
144101866cSLars-Peter Clausen 	ADAU1381,
154101866cSLars-Peter Clausen 	ADAU1781,
164101866cSLars-Peter Clausen };
174101866cSLars-Peter Clausen 
184101866cSLars-Peter Clausen enum adau17x1_pll {
194101866cSLars-Peter Clausen 	ADAU17X1_PLL,
204101866cSLars-Peter Clausen };
214101866cSLars-Peter Clausen 
224101866cSLars-Peter Clausen enum adau17x1_pll_src {
234101866cSLars-Peter Clausen 	ADAU17X1_PLL_SRC_MCLK,
244101866cSLars-Peter Clausen };
254101866cSLars-Peter Clausen 
264101866cSLars-Peter Clausen enum adau17x1_clk_src {
275d76de61SLars-Peter Clausen 	/* Automatically configure PLL based on the sample rate */
285d76de61SLars-Peter Clausen 	ADAU17X1_CLK_SRC_PLL_AUTO,
294101866cSLars-Peter Clausen 	ADAU17X1_CLK_SRC_MCLK,
304101866cSLars-Peter Clausen 	ADAU17X1_CLK_SRC_PLL,
314101866cSLars-Peter Clausen };
324101866cSLars-Peter Clausen 
335d76de61SLars-Peter Clausen struct clk;
345d76de61SLars-Peter Clausen 
354101866cSLars-Peter Clausen struct adau {
364101866cSLars-Peter Clausen 	unsigned int sysclk;
374101866cSLars-Peter Clausen 	unsigned int pll_freq;
385d76de61SLars-Peter Clausen 	struct clk *mclk;
394101866cSLars-Peter Clausen 
404101866cSLars-Peter Clausen 	enum adau17x1_clk_src clk_src;
414101866cSLars-Peter Clausen 	enum adau17x1_type type;
424101866cSLars-Peter Clausen 	void (*switch_mode)(struct device *dev);
434101866cSLars-Peter Clausen 
444101866cSLars-Peter Clausen 	unsigned int dai_fmt;
454101866cSLars-Peter Clausen 
464101866cSLars-Peter Clausen 	uint8_t pll_regs[6];
474101866cSLars-Peter Clausen 
484101866cSLars-Peter Clausen 	bool master;
494101866cSLars-Peter Clausen 
504101866cSLars-Peter Clausen 	unsigned int tdm_slot[2];
514101866cSLars-Peter Clausen 	bool dsp_bypass[2];
524101866cSLars-Peter Clausen 
534101866cSLars-Peter Clausen 	struct regmap *regmap;
54d48b088eSLars-Peter Clausen 	struct sigmadsp *sigmadsp;
554101866cSLars-Peter Clausen };
564101866cSLars-Peter Clausen 
57dd08102aSKuninori Morimoto int adau17x1_add_widgets(struct snd_soc_component *component);
58dd08102aSKuninori Morimoto int adau17x1_add_routes(struct snd_soc_component *component);
594101866cSLars-Peter Clausen int adau17x1_probe(struct device *dev, struct regmap *regmap,
60d48b088eSLars-Peter Clausen 	enum adau17x1_type type, void (*switch_mode)(struct device *dev),
61d48b088eSLars-Peter Clausen 	const char *firmware_name);
625d76de61SLars-Peter Clausen void adau17x1_remove(struct device *dev);
63dd08102aSKuninori Morimoto int adau17x1_set_micbias_voltage(struct snd_soc_component *component,
644101866cSLars-Peter Clausen 	enum adau17x1_micbias_voltage micbias);
654101866cSLars-Peter Clausen bool adau17x1_readable_register(struct device *dev, unsigned int reg);
664101866cSLars-Peter Clausen bool adau17x1_volatile_register(struct device *dev, unsigned int reg);
67dee9cec4SLars-Peter Clausen bool adau17x1_precious_register(struct device *dev, unsigned int reg);
68dd08102aSKuninori Morimoto int adau17x1_resume(struct snd_soc_component *component);
694101866cSLars-Peter Clausen 
704101866cSLars-Peter Clausen extern const struct snd_soc_dai_ops adau17x1_dai_ops;
714101866cSLars-Peter Clausen 
724101866cSLars-Peter Clausen #define ADAU17X1_CLOCK_CONTROL			0x4000
734101866cSLars-Peter Clausen #define ADAU17X1_PLL_CONTROL			0x4002
744101866cSLars-Peter Clausen #define ADAU17X1_REC_POWER_MGMT			0x4009
754101866cSLars-Peter Clausen #define ADAU17X1_MICBIAS			0x4010
764101866cSLars-Peter Clausen #define ADAU17X1_SERIAL_PORT0			0x4015
774101866cSLars-Peter Clausen #define ADAU17X1_SERIAL_PORT1			0x4016
784101866cSLars-Peter Clausen #define ADAU17X1_CONVERTER0			0x4017
794101866cSLars-Peter Clausen #define ADAU17X1_CONVERTER1			0x4018
804101866cSLars-Peter Clausen #define ADAU17X1_LEFT_INPUT_DIGITAL_VOL		0x401a
814101866cSLars-Peter Clausen #define ADAU17X1_RIGHT_INPUT_DIGITAL_VOL	0x401b
824101866cSLars-Peter Clausen #define ADAU17X1_ADC_CONTROL			0x4019
834101866cSLars-Peter Clausen #define ADAU17X1_PLAY_POWER_MGMT		0x4029
844101866cSLars-Peter Clausen #define ADAU17X1_DAC_CONTROL0			0x402a
854101866cSLars-Peter Clausen #define ADAU17X1_DAC_CONTROL1			0x402b
864101866cSLars-Peter Clausen #define ADAU17X1_DAC_CONTROL2			0x402c
874101866cSLars-Peter Clausen #define ADAU17X1_SERIAL_PORT_PAD		0x402d
884101866cSLars-Peter Clausen #define ADAU17X1_CONTROL_PORT_PAD0		0x402f
894101866cSLars-Peter Clausen #define ADAU17X1_CONTROL_PORT_PAD1		0x4030
904101866cSLars-Peter Clausen #define ADAU17X1_DSP_SAMPLING_RATE		0x40eb
914101866cSLars-Peter Clausen #define ADAU17X1_SERIAL_INPUT_ROUTE		0x40f2
924101866cSLars-Peter Clausen #define ADAU17X1_SERIAL_OUTPUT_ROUTE		0x40f3
934101866cSLars-Peter Clausen #define ADAU17X1_DSP_ENABLE			0x40f5
944101866cSLars-Peter Clausen #define ADAU17X1_DSP_RUN			0x40f6
954101866cSLars-Peter Clausen #define ADAU17X1_SERIAL_SAMPLING_RATE		0x40f8
964101866cSLars-Peter Clausen 
974101866cSLars-Peter Clausen #define ADAU17X1_SERIAL_PORT0_BCLK_POL		BIT(4)
984101866cSLars-Peter Clausen #define ADAU17X1_SERIAL_PORT0_LRCLK_POL		BIT(3)
994101866cSLars-Peter Clausen #define ADAU17X1_SERIAL_PORT0_MASTER		BIT(0)
1004101866cSLars-Peter Clausen 
1014101866cSLars-Peter Clausen #define ADAU17X1_SERIAL_PORT1_DELAY1		0x00
1024101866cSLars-Peter Clausen #define ADAU17X1_SERIAL_PORT1_DELAY0		0x01
1034101866cSLars-Peter Clausen #define ADAU17X1_SERIAL_PORT1_DELAY8		0x02
1044101866cSLars-Peter Clausen #define ADAU17X1_SERIAL_PORT1_DELAY16		0x03
1054101866cSLars-Peter Clausen #define ADAU17X1_SERIAL_PORT1_DELAY_MASK	0x03
1064101866cSLars-Peter Clausen 
1074101866cSLars-Peter Clausen #define ADAU17X1_CLOCK_CONTROL_INFREQ_MASK	0x6
1084101866cSLars-Peter Clausen #define ADAU17X1_CLOCK_CONTROL_CORECLK_SRC_PLL	BIT(3)
1094101866cSLars-Peter Clausen #define ADAU17X1_CLOCK_CONTROL_SYSCLK_EN	BIT(0)
1104101866cSLars-Peter Clausen 
1117c139db2SAndreas Irestål #define ADAU17X1_SERIAL_PORT1_BCLK64		(0x0 << 5)
1127c139db2SAndreas Irestål #define ADAU17X1_SERIAL_PORT1_BCLK32		(0x1 << 5)
1137c139db2SAndreas Irestål #define ADAU17X1_SERIAL_PORT1_BCLK48		(0x2 << 5)
1144101866cSLars-Peter Clausen #define ADAU17X1_SERIAL_PORT1_BCLK128		(0x3 << 5)
1154101866cSLars-Peter Clausen #define ADAU17X1_SERIAL_PORT1_BCLK256		(0x4 << 5)
1164101866cSLars-Peter Clausen #define ADAU17X1_SERIAL_PORT1_BCLK_MASK		(0x7 << 5)
1174101866cSLars-Peter Clausen 
1184101866cSLars-Peter Clausen #define ADAU17X1_SERIAL_PORT0_STEREO		(0x0 << 1)
1194101866cSLars-Peter Clausen #define ADAU17X1_SERIAL_PORT0_TDM4		(0x1 << 1)
1204101866cSLars-Peter Clausen #define ADAU17X1_SERIAL_PORT0_TDM8		(0x2 << 1)
1214101866cSLars-Peter Clausen #define ADAU17X1_SERIAL_PORT0_TDM_MASK		(0x3 << 1)
1224101866cSLars-Peter Clausen #define ADAU17X1_SERIAL_PORT0_PULSE_MODE	BIT(5)
1234101866cSLars-Peter Clausen 
1244101866cSLars-Peter Clausen #define ADAU17X1_CONVERTER0_DAC_PAIR(x)		(((x) - 1) << 5)
1254101866cSLars-Peter Clausen #define ADAU17X1_CONVERTER0_DAC_PAIR_MASK	(0x3 << 5)
1264101866cSLars-Peter Clausen #define ADAU17X1_CONVERTER1_ADC_PAIR(x)		((x) - 1)
1274101866cSLars-Peter Clausen #define ADAU17X1_CONVERTER1_ADC_PAIR_MASK	0x3
1284101866cSLars-Peter Clausen 
1294101866cSLars-Peter Clausen #define ADAU17X1_CONVERTER0_CONVSR_MASK		0x7
1304101866cSLars-Peter Clausen 
1311e6f4fc0SRicard Wanderlof #define ADAU17X1_CONVERTER0_ADOSR		BIT(3)
1321e6f4fc0SRicard Wanderlof 
1334101866cSLars-Peter Clausen 
1344101866cSLars-Peter Clausen #endif
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