Lines Matching +full:0 +full:x4010

50 #define PITA2_ICR           0x00	/* Interrupt Control Register */
51 #define PITA2_ICR_INT0      0x00000002	/* [RC] INT0 Active/Clear */
52 #define PITA2_ICR_INT0_EN   0x00020000	/* [RW] Enable INT0 */
54 #define PITA2_MISC          0x1c	/* Miscellaneous Register */
55 #define PITA2_MISC_CONFIG   0x04000000	/* Multiplexed parallel interface */
59 #define PLX_ICSR            0x4c   /* Interrupt Control/Status register */
60 #define PLX_ICSR_LINTI1_ENA 0x0001 /* LINTi1 Enable */
61 #define PLX_ICSR_PCIINT_ENA 0x0040 /* PCI Interrupt Enable */
62 #define PLX_ICSR_LINTI1_CLR 0x0400 /* Local Edge Triggerable Interrupt Clear */
68 #define ASIX_LINTSR 0x28 /* Interrupt Control/Status register */
69 #define ASIX_LINTSR_INT0AC BIT(0) /* Writing 1 enables or clears interrupt */
71 #define ASIX_LIEMR 0x24 /* Local Interrupt Enable / Miscellaneous Register */
79  * Setting the OCR register to 0xDA is a good idea.
92 #define EMS_PCI_V1_CONF_BAR 0
94 #define EMS_PCI_V1_CAN_BASE_OFFSET 0x400 /* offset where the controllers start */
95 #define EMS_PCI_V1_CAN_CTRL_SIZE 0x200 /* memory size for each controller */
98 #define EMS_PCI_V2_CONF_BAR 0
100 #define EMS_PCI_V2_CAN_BASE_OFFSET 0x400 /* offset where the controllers start */
101 #define EMS_PCI_V2_CAN_CTRL_SIZE 0x200 /* memory size for each controller */
103 #define EMS_PCI_V3_BASE_BAR 0
106 #define EMS_PCI_V3_CAN_BASE_OFFSET 0x00 /* offset where the controllers starts */
107 #define EMS_PCI_V3_CAN_CTRL_SIZE 0x100 /* memory size for each controller */
111 #define PCI_SUBDEVICE_ID_EMS 0x4010
115 	{PCI_VENDOR_ID_SIEMENS, 0x2104, PCI_ANY_ID, PCI_ANY_ID,},
117 	{PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_PLX, 0x4000},
119 	{PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_PLX, 0x4002},
121 	{PCI_VENDOR_ID_ASIX, PCI_DEVICE_ID_ASIX_AX99100_LB, 0xa000, PCI_SUBDEVICE_ID_EMS},
122 	{0,}
207 	return 0;  in ems_pci_check_chan()
214 	int i = 0;  in ems_pci_del_card()
216 	for (i = 0; i < card->channels; i++) {  in ems_pci_del_card()
241 	writeb(0, card->base_addr);  in ems_pci_card_reset()
257 	if (pci_enable_device(pdev) < 0) {  in ems_pci_add_card()
273 	card->channels = 0;  in ems_pci_add_card()
313 		if (ems_pci_v1_readb(card, 0) != 0x55 ||  in ems_pci_add_card()
314 		    ems_pci_v1_readb(card, 1) != 0xAA ||  in ems_pci_add_card()
315 		    ems_pci_v1_readb(card, 2) != 0x01 ||  in ems_pci_add_card()
316 		    ems_pci_v1_readb(card, 3) != 0xCB ||  in ems_pci_add_card()
317 		    ems_pci_v1_readb(card, 4) != 0x11) {  in ems_pci_add_card()
336 	for (i = 0; i < max_chan; i++) {  in ems_pci_add_card()
337 		dev = alloc_sja1000dev(0);  in ems_pci_add_card()
407 			dev_info(&pdev->dev, "Channel #%d at 0x%p, irq %d\n",  in ems_pci_add_card()
414 	return 0;  in ems_pci_add_card()