Home
last modified time | relevance | path

Searched +full:0 +full:x400 (Results 1 – 25 of 1038) sorted by relevance

12345678910>>...42

/linux/arch/arm/boot/dts/st/
H A Dstm32mp131.dtsi16 #size-cells = <0>;
18 cpu0: cpu@0 {
21 reg = <0>;
34 arm,smc-id = <0xbc000000>;
49 #size-cells = <0>;
50 linaro,optee-channel-id = <0>;
53 reg = <0x14>;
58 reg = <0x16>;
63 reg = <0x17>;
67 #size-cells = <0>;
[all …]
H A Dstm32f429.dtsi58 #clock-cells = <0>;
60 clock-frequency = <0>;
64 #clock-cells = <0>;
70 #clock-cells = <0>;
76 #clock-cells = <0>;
78 clock-frequency = <0>;
85 reg = <0x1fff7800 0x400>;
89 reg = <0x22c 0x2>;
92 reg = <0x22e 0x2>;
98 #size-cells = <0>;
[all …]
H A Dstm32f746.dtsi54 #clock-cells = <0>;
56 clock-frequency = <0>;
60 #clock-cells = <0>;
66 #clock-cells = <0>;
72 #clock-cells = <0>;
81 #size-cells = <0>;
83 reg = <0x40000000 0x400>;
84 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
103 #size-cells = <0>;
105 reg = <0x40000400 0x400>;
[all …]
H A Dstm32h743.dtsi54 #clock-cells = <0>;
56 clock-frequency = <0>;
60 #clock-cells = <0>;
66 #clock-cells = <0>;
68 clock-frequency = <0>;
75 reg = <0x40000c00 0x400>;
82 #size-cells = <0>;
84 reg = <0x40002400 0x400>;
95 trigger@0 {
97 reg = <0>;
[all …]
/linux/arch/arm/boot/dts/ti/keystone/
H A Dkeystone-k2hk-clocks.dtsi10 #clock-cells = <0>;
14 reg = <0x02620370 4>;
19 #clock-cells = <0>;
22 reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;
27 #clock-cells = <0>;
31 reg = <0x02620358 4>;
36 #clock-cells = <0>;
40 reg = <0x02620360 4>;
45 #clock-cells = <0>;
49 reg = <0x02620368 4>;
[all …]
H A Dkeystone-k2l-clocks.dtsi10 #clock-cells = <0>;
14 reg = <0x02620370 4>;
19 #clock-cells = <0>;
22 reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;
27 #clock-cells = <0>;
31 reg = <0x02620358 4>;
36 #clock-cells = <0>;
40 reg = <0x02620360 4>;
45 #clock-cells = <0>;
50 reg = <0x02350004 0xb00>, <0x02350000 0x400>;
[all …]
H A Dkeystone-clocks.dtsi14 #clock-cells = <0>;
17 reg = <0x02310108 4>;
24 #clock-cells = <0>;
33 #clock-cells = <0>;
42 #clock-cells = <0>;
45 reg = <0x02310120 4>;
46 bit-shift = <0>;
52 #clock-cells = <0>;
55 reg = <0x02310164 4>;
56 bit-shift = <0>;
[all …]
/linux/drivers/pmdomain/renesas/
H A Dr8a77980-sysc.c17 { "always-on", 0, 0, R8A77980_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
18 { "ca53-scu", 0x140, 0, R8A77980_PD_CA53_SCU, R8A77980_PD_ALWAYS_ON,
20 { "ca53-cpu0", 0x200, 0, R8A77980_PD_CA53_CPU0, R8A77980_PD_CA53_SCU,
22 { "ca53-cpu1", 0x200, 1, R8A77980_PD_CA53_CPU1, R8A77980_PD_CA53_SCU,
24 { "ca53-cpu2", 0x200, 2, R8A77980_PD_CA53_CPU2, R8A77980_PD_CA53_SCU,
26 { "ca53-cpu3", 0x200, 3, R8A77980_PD_CA53_CPU3, R8A77980_PD_CA53_SCU,
28 { "cr7", 0x240, 0, R8A77980_PD_CR7, R8A77980_PD_ALWAYS_ON,
30 { "a3ir", 0x180, 0, R8A77980_PD_A3IR, R8A77980_PD_ALWAYS_ON },
31 { "a2ir0", 0x400, 0, R8A77980_PD_A2IR0, R8A77980_PD_A3IR },
32 { "a2ir1", 0x400, 1, R8A77980_PD_A2IR1, R8A77980_PD_A3IR },
[all …]
H A Dr8a77970-sysc.c16 { "always-on", 0, 0, R8A77970_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
17 { "ca53-scu", 0x140, 0, R8A77970_PD_CA53_SCU, R8A77970_PD_ALWAYS_ON,
19 { "ca53-cpu0", 0x200, 0, R8A77970_PD_CA53_CPU0, R8A77970_PD_CA53_SCU,
21 { "ca53-cpu1", 0x200, 1, R8A77970_PD_CA53_CPU1, R8A77970_PD_CA53_SCU,
23 { "a3ir", 0x180, 0, R8A77970_PD_A3IR, R8A77970_PD_ALWAYS_ON },
24 { "a2ir0", 0x400, 0, R8A77970_PD_A2IR0, R8A77970_PD_A3IR },
25 { "a2ir1", 0x400, 1, R8A77970_PD_A2IR1, R8A77970_PD_A3IR },
26 { "a2dp", 0x400, 2, R8A77970_PD_A2DP, R8A77970_PD_A3IR },
27 { "a2cn", 0x400, 3, R8A77970_PD_A2CN, R8A77970_PD_A3IR },
28 { "a2sc0", 0x400, 4, R8A77970_PD_A2SC0, R8A77970_PD_A3IR },
[all …]
/linux/arch/arm/boot/dts/aspeed/
H A Dibm-power11-dual.dtsi71 #size-cells = <0>;
72 cfam-reset-gpios = <&gpio0 ASPEED_GPIO(Q, 0) GPIO_ACTIVE_HIGH>;
75 cfam@0,0 {
76 reg = <0 0>;
79 chip-id = <0>;
83 reg = <0x1000 0x400>;
88 reg = <0x1800 0x400>;
90 #size-cells = <0>;
92 cfam0_i2c0: i2c-bus@0 {
93 reg = <0>; /* OMI01 */
[all …]
H A Dibm-power11-quad.dtsi71 cfam@2,0 {
72 reg = <2 0>;
79 reg = <0x1000 0x400>;
84 reg = <0x1800 0x400>;
86 #size-cells = <0>;
88 cfam2_i2c0: i2c-bus@0 {
89 reg = <0>; /* OM01 */
91 #size-cells = <0>;
95 reg = <0x20>;
97 #size-cells = <0>;
[all …]
H A Daspeed-bmc-ibm-everest.dts175 reg = <0x80000000 0x40000000>;
185 reg = <0xb3d00000 0x100000>;
190 reg = <0xb3e00000 0x200000>; /* 16 * (4 * 0x8000) */
191 record-size = <0x8000>;
192 console-size = <0x8000>;
193 ftrace-size = <0x8000>;
194 pmsg-size = <0x8000>;
201 reg = <0xb4000000 0x04000000>; /* 64M */
208 reg = <0xbf000000 0x01000000>; /* 16M */
246 gpios = <&gpio0 ASPEED_GPIO(H, 0) GPIO_ACTIVE_LOW>;
[all …]
H A Dibm-power9-dual.dtsi5 cfam@0,0 {
6 reg = <0 0>;
9 chip-id = <0>;
13 reg = <0x1000 0x400>;
18 reg = <0x1800 0x400>;
20 #size-cells = <0>;
22 cfam0_i2c0: i2c-bus@0 {
23 reg = <0>;
85 reg = <0x2400 0x400>;
87 #size-cells = <0>;
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Domap2.dtsi29 #address-cells = <0>;
30 #size-cells = <0>;
61 reg = <0x480a6000 0x50>;
69 reg = <0x480b2000 0x1000>;
77 reg = <0x480FE000 0x1000>;
82 reg = <0x48056000 0x4>,
83 <0x4805602c 0x4>,
84 <0x48056028 0x4>;
98 ranges = <0 0x48056000 0x1000>;
100 sdma: dma-controller@0 {
[all …]
/linux/sound/soc/uniphier/
H A Daio-reg.h14 #define SG_AOUTEN 0x1c04
17 #define A2CHNMAPCTR0(n) (0x00000 + 0x40 * (n))
18 #define A2RBNMAPCTR0(n) (0x01000 + 0x40 * (n))
19 #define A2IPORTNMAPCTR0(n) (0x02000 + 0x40 * (n))
20 #define A2IPORTNMAPCTR1(n) (0x02004 + 0x40 * (n))
21 #define A2IIFNMAPCTR0(n) (0x03000 + 0x40 * (n))
22 #define A2OPORTNMAPCTR0(n) (0x04000 + 0x40 * (n))
23 #define A2OPORTNMAPCTR1(n) (0x04004 + 0x40 * (n))
24 #define A2OPORTNMAPCTR2(n) (0x04008 + 0x40 * (n))
25 #define A2OIFNMAPCTR0(n) (0x05000 + 0x40 * (n))
[all …]
/linux/arch/arm64/boot/dts/axiado/
H A Dax3000.dtsi11 /memreserve/ 0x3c0013a0 0x00000008; /* cpu-release-addr */
20 #size-cells = <0>;
22 cpu0: cpu@0 {
25 reg = <0x0 0x0>;
27 cpu-release-addr = <0x0 0x3c0013a0>;
28 d-cache-size = <0x8000>;
31 i-cache-size = <0x8000>;
40 reg = <0x0 0x1>;
42 cpu-release-addr = <0x0 0x3c0013a0>;
43 d-cache-size = <0x8000>;
[all …]
/linux/drivers/gpu/drm/kmb/
H A Dkmb_regs.h12 #define LCD_CONTROL (0x4 * 0x000)
13 #define LCD_CTRL_PROGRESSIVE (0 << 0)
14 #define LCD_CTRL_INTERLACED BIT(0)
20 #define LCD_CTRL_ALPHA_BLEND_VL1 (0 << 6)
24 #define LCD_CTRL_ALPHA_TOP_VL1 (0 << 8)
28 #define LCD_CTRL_ALPHA_MIDDLE_VL1 (0 << 10)
32 #define LCD_CTRL_ALPHA_BOTTOM_VL1 (0 << 12)
37 #define LCD_CTRL_CONTINUOUS (0 << 15)
42 #define LCD_CTRL_OUTPUT_DISABLED (0 << 19)
49 #define LCD_CTRL_ALPHA_ALL (0xff << 6)
[all …]
/linux/drivers/misc/mchp_pci1xxxx/
H A Dmchp_pci1xxxx_gpio.c17 #define PCI_DEV_REV_OFFSET 0x08
18 #define PERI_GEN_RESET 0
19 #define OUT_EN_OFFSET(x) ((((x) / 32) * 4) + 0x400)
20 #define INP_EN_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x10)
21 #define OUT_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x20)
22 #define INP_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x30)
23 #define PULLUP_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x40)
24 #define PULLDOWN_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x50)
25 #define OPENDRAIN_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x60)
26 #define WAKEMASK_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x70)
[all …]
/linux/drivers/accel/habanalabs/include/gaudi/asic_reg/
H A Dmme0_qm_masks.h23 #define MME0_QM_GLBL_CFG0_PQF_EN_SHIFT 0
24 #define MME0_QM_GLBL_CFG0_PQF_EN_MASK 0xF
26 #define MME0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F0
28 #define MME0_QM_GLBL_CFG0_CP_EN_MASK 0x3E00
31 #define MME0_QM_GLBL_CFG1_PQF_STOP_SHIFT 0
32 #define MME0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF
34 #define MME0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F0
36 #define MME0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E00
38 #define MME0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000
40 #define MME0_QM_GLBL_CFG1_CQF_FLUSH_MASK 0x1F00000
[all …]
H A Ddma0_qm_masks.h23 #define DMA0_QM_GLBL_CFG0_PQF_EN_SHIFT 0
24 #define DMA0_QM_GLBL_CFG0_PQF_EN_MASK 0xF
26 #define DMA0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F0
28 #define DMA0_QM_GLBL_CFG0_CP_EN_MASK 0x3E00
31 #define DMA0_QM_GLBL_CFG1_PQF_STOP_SHIFT 0
32 #define DMA0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF
34 #define DMA0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F0
36 #define DMA0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E00
38 #define DMA0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000
40 #define DMA0_QM_GLBL_CFG1_CQF_FLUSH_MASK 0x1F00000
[all …]
H A Dtpc0_qm_masks.h23 #define TPC0_QM_GLBL_CFG0_PQF_EN_SHIFT 0
24 #define TPC0_QM_GLBL_CFG0_PQF_EN_MASK 0xF
26 #define TPC0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F0
28 #define TPC0_QM_GLBL_CFG0_CP_EN_MASK 0x3E00
31 #define TPC0_QM_GLBL_CFG1_PQF_STOP_SHIFT 0
32 #define TPC0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF
34 #define TPC0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F0
36 #define TPC0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E00
38 #define TPC0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000
40 #define TPC0_QM_GLBL_CFG1_CQF_FLUSH_MASK 0x1F00000
[all …]
H A Dnic0_qm0_masks.h23 #define NIC0_QM0_GLBL_CFG0_PQF_EN_SHIFT 0
24 #define NIC0_QM0_GLBL_CFG0_PQF_EN_MASK 0xF
26 #define NIC0_QM0_GLBL_CFG0_CQF_EN_MASK 0x1F0
28 #define NIC0_QM0_GLBL_CFG0_CP_EN_MASK 0x3E00
31 #define NIC0_QM0_GLBL_CFG1_PQF_STOP_SHIFT 0
32 #define NIC0_QM0_GLBL_CFG1_PQF_STOP_MASK 0xF
34 #define NIC0_QM0_GLBL_CFG1_CQF_STOP_MASK 0x1F0
36 #define NIC0_QM0_GLBL_CFG1_CP_STOP_MASK 0x3E00
38 #define NIC0_QM0_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000
40 #define NIC0_QM0_GLBL_CFG1_CQF_FLUSH_MASK 0x1F00000
[all …]
/linux/drivers/gpu/drm/msm/disp/dpu1/catalog/
H A Ddpu_12_2_glymur.h11 .max_mixer_blendstages = 0xb,
22 .base = 0, .len = 0x494,
24 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
31 .base = 0x15000, .len = 0x1000,
35 .base = 0x16000, .len = 0x1000,
39 .base = 0x17000, .len = 0x1000,
43 .base = 0x18000, .len = 0x1000,
47 .base = 0x19000, .len = 0x1000,
51 .base = 0x1a000, .len = 0x1000,
55 .base = 0x1b000, .len = 0x1000,
[all …]
/linux/arch/arm64/boot/dts/renesas/
H A Dr9a07g043.dtsi17 #clock-cells = <0>;
19 clock-frequency = <0>;
24 #clock-cells = <0>;
26 clock-frequency = <0>;
32 #clock-cells = <0>;
33 clock-frequency = <0>;
39 #clock-cells = <0>;
41 clock-frequency = <0>;
44 cluster0_opp: opp-table-0 {
80 reg = <0 0x10001200 0 0xb00>;
[all …]
/linux/arch/powerpc/boot/dts/fsl/
H A Dqoriq-raid1.0-0.dtsi2 * QorIQ RAID 1.0 device tree stub [ controller @ offset 0x320000 ]
36 compatible = "fsl,raideng-v1.0";
39 reg = <0x320000 0x10000>;
40 ranges = <0 0x320000 0x10000>;
43 compatible = "fsl,raideng-v1.0-job-queue";
46 reg = <0x1000 0x1000>;
47 ranges = <0x0 0x1000 0x1000>;
49 raideng_jr0: jr@0 {
50 compatible = "fsl,raideng-v1.0-job-ring", "fsl,raideng-v1.0-hp-ring";
51 reg = <0x0 0x400>;
[all …]

12345678910>>...42