Lines Matching +full:0 +full:x400
12 #define LCD_CONTROL (0x4 * 0x000)
13 #define LCD_CTRL_PROGRESSIVE (0 << 0)
14 #define LCD_CTRL_INTERLACED BIT(0)
20 #define LCD_CTRL_ALPHA_BLEND_VL1 (0 << 6)
24 #define LCD_CTRL_ALPHA_TOP_VL1 (0 << 8)
28 #define LCD_CTRL_ALPHA_MIDDLE_VL1 (0 << 10)
32 #define LCD_CTRL_ALPHA_BOTTOM_VL1 (0 << 12)
37 #define LCD_CTRL_CONTINUOUS (0 << 15)
42 #define LCD_CTRL_OUTPUT_DISABLED (0 << 19)
49 #define LCD_CTRL_ALPHA_ALL (0xff << 6)
52 #define LCD_INT_STATUS (0x4 * 0x001)
53 #define LCD_INT_EOF BIT(0)
80 #define LCD_INT_LAYER (0x07fffff8)
81 #define LCD_INT_ENABLE (0x4 * 0x002)
82 #define LCD_INT_CLEAR (0x4 * 0x003)
83 #define LCD_LINE_COUNT (0x4 * 0x004)
84 #define LCD_LINE_COMPARE (0x4 * 0x005)
85 #define LCD_VSTATUS (0x4 * 0x006)
91 #define LCD_VSTATUS_COMPARE (0x4 * 0x007)
93 #define LCD_VSTATUS_COMPARE_VSYNC (0 << 13)
98 #define LCD_SCREEN_WIDTH (0x4 * 0x008)
99 #define LCD_SCREEN_HEIGHT (0x4 * 0x009)
100 #define LCD_FIELD_INT_CFG (0x4 * 0x00a)
101 #define LCD_FIFO_FLUSH (0x4 * 0x00b)
102 #define LCD_BG_COLOUR_LS (0x4 * 0x00c)
103 #define LCD_BG_COLOUR_MS (0x4 * 0x00d)
104 #define LCD_RAM_CFG (0x4 * 0x00e)
109 #define LCD_LAYER0_CFG (0x4 * 0x100)
110 #define LCD_LAYERn_CFG(N) (LCD_LAYER0_CFG + (0x400 * (N)))
125 #define LCD_LAYER_FORMAT_YCBCR444PLAN (0 << 9)
135 #define LCD_LAYER_FORMAT_RGBA1555 (0xa << 9)
136 #define LCD_LAYER_FORMAT_XRGB1555 (0xb << 9)
137 #define LCD_LAYER_FORMAT_RGB444 (0xc << 9)
138 #define LCD_LAYER_FORMAT_RGBA4444 (0xd << 9)
139 #define LCD_LAYER_FORMAT_RGBX4444 (0xe << 9)
140 #define LCD_LAYER_FORMAT_RGB332 (0xf << 9)
141 #define LCD_LAYER_FORMAT_RGBA3328 (0x10 << 9)
142 #define LCD_LAYER_FORMAT_RGBX3328 (0x11 << 9)
143 #define LCD_LAYER_FORMAT_CLUT (0x12 << 9)
144 #define LCD_LAYER_FORMAT_NV12 (0x1c << 9)
146 #define LCD_LAYER_8BPP (0 << 15)
153 #define LCD_LAYER_LUT_2ENT (0 << 20)
156 #define LCD_LAYER_NO_FLIP (0 << 22)
162 #define LCD_LAYER_FIFO_00 (0 << 25)
166 #define LCD_LAYER_INTERLEAVE_DIS (0 << 27)
173 #define LCD_LAYER_INTER_POS_EVEN (0 << 30)
176 #define LCD_LAYER0_COL_START (0x4 * 0x101)
177 #define LCD_LAYERn_COL_START(N) (LCD_LAYER0_COL_START + (0x400 * (N)))
178 #define LCD_LAYER0_ROW_START (0x4 * 0x102)
179 #define LCD_LAYERn_ROW_START(N) (LCD_LAYER0_ROW_START + (0x400 * (N)))
180 #define LCD_LAYER0_WIDTH (0x4 * 0x103)
181 #define LCD_LAYERn_WIDTH(N) (LCD_LAYER0_WIDTH + (0x400 * (N)))
182 #define LCD_LAYER0_HEIGHT (0x4 * 0x104)
183 #define LCD_LAYERn_HEIGHT(N) (LCD_LAYER0_HEIGHT + (0x400 * (N)))
184 #define LCD_LAYER0_SCALE_CFG (0x4 * 0x105)
185 #define LCD_LAYERn_SCALE_CFG(N) (LCD_LAYER0_SCALE_CFG + (0x400 * (N)))
186 #define LCD_LAYER0_ALPHA (0x4 * 0x106)
187 #define LCD_LAYERn_ALPHA(N) (LCD_LAYER0_ALPHA + (0x400 * (N)))
188 #define LCD_LAYER0_INV_COLOUR_LS (0x4 * 0x107)
190 (0x400 * (N)))
191 #define LCD_LAYER0_INV_COLOUR_MS (0x4 * 0x108)
193 (0x400 * (N)))
194 #define LCD_LAYER0_TRANS_COLOUR_LS (0x4 * 0x109)
196 (0x400 * (N)))
197 #define LCD_LAYER0_TRANS_COLOUR_MS (0x4 * 0x10a)
199 (0x400 * (N)))
200 #define LCD_LAYER0_CSC_COEFF11 (0x4 * 0x10b)
201 #define LCD_LAYERn_CSC_COEFF11(N) (LCD_LAYER0_CSC_COEFF11 + (0x400 * (N)))
202 #define LCD_LAYER0_CSC_COEFF12 (0x4 * 0x10c)
203 #define LCD_LAYERn_CSC_COEFF12(N) (LCD_LAYER0_CSC_COEFF12 + (0x400 * (N)))
204 #define LCD_LAYER0_CSC_COEFF13 (0x4 * 0x10d)
205 #define LCD_LAYERn_CSC_COEFF13(N) (LCD_LAYER0_CSC_COEFF13 + (0x400 * (N)))
206 #define LCD_LAYER0_CSC_COEFF21 (0x4 * 0x10e)
207 #define LCD_LAYERn_CSC_COEFF21(N) (LCD_LAYER0_CSC_COEFF21 + (0x400 * (N)))
208 #define LCD_LAYER0_CSC_COEFF22 (0x4 * 0x10f)
209 #define LCD_LAYERn_CSC_COEFF22(N) (LCD_LAYER0_CSC_COEFF22 + (0x400 * (N)))
210 #define LCD_LAYER0_CSC_COEFF23 (0x4 * 0x110)
211 #define LCD_LAYERn_CSC_COEFF23(N) (LCD_LAYER0_CSC_COEFF23 + (0x400 * (N)))
212 #define LCD_LAYER0_CSC_COEFF31 (0x4 * 0x111)
213 #define LCD_LAYERn_CSC_COEFF31(N) (LCD_LAYER0_CSC_COEFF31 + (0x400 * (N)))
214 #define LCD_LAYER0_CSC_COEFF32 (0x4 * 0x112)
215 #define LCD_LAYERn_CSC_COEFF32(N) (LCD_LAYER0_CSC_COEFF32 + (0x400 * (N)))
216 #define LCD_LAYER0_CSC_COEFF33 (0x4 * 0x113)
217 #define LCD_LAYERn_CSC_COEFF33(N) (LCD_LAYER0_CSC_COEFF33 + (0x400 * (N)))
218 #define LCD_LAYER0_CSC_OFF1 (0x4 * 0x114)
219 #define LCD_LAYERn_CSC_OFF1(N) (LCD_LAYER0_CSC_OFF1 + (0x400 * (N)))
220 #define LCD_LAYER0_CSC_OFF2 (0x4 * 0x115)
221 #define LCD_LAYERn_CSC_OFF2(N) (LCD_LAYER0_CSC_OFF2 + (0x400 * (N)))
222 #define LCD_LAYER0_CSC_OFF3 (0x4 * 0x116)
223 #define LCD_LAYERn_CSC_OFF3(N) (LCD_LAYER0_CSC_OFF3 + (0x400 * (N)))
226 #define LCD_LAYER0_DMA_CFG (0x4 * 0x117)
228 (0x400 * (N)))
229 #define LCD_DMA_LAYER_ENABLE BIT(0)
245 #define LCD_DMA_LAYER_AXI_BURST_10 (0xa << 5)
246 #define LCD_DMA_LAYER_AXI_BURST_11 (0xb << 5)
247 #define LCD_DMA_LAYER_AXI_BURST_12 (0xc << 5)
248 #define LCD_DMA_LAYER_AXI_BURST_13 (0xd << 5)
249 #define LCD_DMA_LAYER_AXI_BURST_14 (0xe << 5)
250 #define LCD_DMA_LAYER_AXI_BURST_15 (0xf << 5)
251 #define LCD_DMA_LAYER_AXI_BURST_16 (0x10 << 5)
254 #define LCD_LAYER0_DMA_START_ADR (0x4 * 0x118)
256 + (0x400 * (N)))
257 #define LCD_LAYER0_DMA_START_SHADOW (0x4 * 0x119)
259 + (0x400 * (N)))
260 #define LCD_LAYER0_DMA_LEN (0x4 * 0x11a)
262 (0x400 * (N)))
263 #define LCD_LAYER0_DMA_LEN_SHADOW (0x4 * 0x11b)
265 (0x400 * (N)))
266 #define LCD_LAYER0_DMA_STATUS (0x4 * 0x11c)
268 (0x400 * (N)))
269 #define LCD_LAYER0_DMA_LINE_WIDTH (0x4 * 0x11d)
271 (0x400 * (N)))
272 #define LCD_LAYER0_DMA_LINE_VSTRIDE (0x4 * 0x11e)
274 (0x400 * (N)))
275 #define LCD_LAYER0_DMA_FIFO_STATUS (0x4 * 0x11f)
277 (0x400 * (N)))
278 #define LCD_LAYER0_CFG2 (0x4 * 0x120)
279 #define LCD_LAYERn_CFG2(N) (LCD_LAYER0_CFG2 + (0x400 * (N)))
280 #define LCD_LAYER0_DMA_START_CB_ADR (0x4 * 0x700)
282 (0x20 * (N)))
283 #define LCD_LAYER0_DMA_START_CB_SHADOW (0x4 * 0x701)
285 + (0x20 * (N)))
286 #define LCD_LAYER0_DMA_CB_LINE_WIDTH (0x4 * 0x702)
288 (0x20 * (N)))
289 #define LCD_LAYER0_DMA_CB_LINE_VSTRIDE (0x4 * 0x703)
291 + (0x20 * (N)))
292 #define LCD_LAYER0_DMA_START_CR_ADR (0x4 * 0x704)
294 (0x20 * (N)))
295 #define LCD_LAYER0_DMA_START_CR_SHADOW (0x4 * 0x705)
298 + (0x20 * (N)))
299 #define LCD_LAYER0_DMA_CR_LINE_WIDTH (0x4 * 0x706)
301 (0x20 * (N)))
302 #define LCD_LAYER0_DMA_CR_LINE_VSTRIDE (0x4 * 0x707)
304 + (0x20 * (N)))
305 #define LCD_LAYER1_DMA_START_CB_ADR (0x4 * 0x708)
306 #define LCD_LAYER1_DMA_START_CB_SHADOW (0x4 * 0x709)
307 #define LCD_LAYER1_DMA_CB_LINE_WIDTH (0x4 * 0x70a)
308 #define LCD_LAYER1_DMA_CB_LINE_VSTRIDE (0x4 * 0x70b)
309 #define LCD_LAYER1_DMA_START_CR_ADR (0x4 * 0x70c)
310 #define LCD_LAYER1_DMA_START_CR_SHADOW (0x4 * 0x70d)
311 #define LCD_LAYER1_DMA_CR_LINE_WIDTH (0x4 * 0x70e)
312 #define LCD_LAYER1_DMA_CR_LINE_VSTRIDE (0x4 * 0x70f)
317 #define LCD_OUT_FORMAT_CFG (0x4 * 0x800)
318 #define LCD_OUTF_FORMAT_RGB121212 (0x00)
319 #define LCD_OUTF_FORMAT_RGB101010 (0x01)
320 #define LCD_OUTF_FORMAT_RGB888 (0x02)
321 #define LCD_OUTF_FORMAT_RGB666 (0x03)
322 #define LCD_OUTF_FORMAT_RGB565 (0x04)
323 #define LCD_OUTF_FORMAT_RGB444 (0x05)
324 #define LCD_OUTF_FORMAT_MRGB121212 (0x10)
325 #define LCD_OUTF_FORMAT_MRGB101010 (0x11)
326 #define LCD_OUTF_FORMAT_MRGB888 (0x12)
327 #define LCD_OUTF_FORMAT_MRGB666 (0x13)
328 #define LCD_OUTF_FORMAT_MRGB565 (0x14)
329 #define LCD_OUTF_FORMAT_YCBCR420_8B_LEGACY (0x08)
330 #define LCD_OUTF_FORMAT_YCBCR420_8B_DCI (0x09)
331 #define LCD_OUTF_FORMAT_YCBCR420_8B (0x0A)
332 #define LCD_OUTF_FORMAT_YCBCR420_10B (0x0B)
333 #define LCD_OUTF_FORMAT_YCBCR420_12B (0x0C)
334 #define LCD_OUTF_FORMAT_YCBCR422_8B (0x0D)
335 #define LCD_OUTF_FORMAT_YCBCR422_10B (0x0E)
336 #define LCD_OUTF_FORMAT_YCBCR444 (0x0F)
337 #define LCD_OUTF_FORMAT_MYCBCR420_8B_LEGACY (0x18)
338 #define LCD_OUTF_FORMAT_MYCBCR420_8B_DCI (0x19)
339 #define LCD_OUTF_FORMAT_MYCBCR420_8B (0x1A)
340 #define LCD_OUTF_FORMAT_MYCBCR420_10B (0x1B)
341 #define LCD_OUTF_FORMAT_MYCBCR420_12B (0x1C)
342 #define LCD_OUTF_FORMAT_MYCBCR422_8B (0x1D)
343 #define LCD_OUTF_FORMAT_MYCBCR422_10B (0x1E)
344 #define LCD_OUTF_FORMAT_MYCBCR444 (0x1F)
352 #define LCD_HSYNC_WIDTH (0x4 * 0x801)
353 #define LCD_H_BACKPORCH (0x4 * 0x802)
354 #define LCD_H_ACTIVEWIDTH (0x4 * 0x803)
355 #define LCD_H_FRONTPORCH (0x4 * 0x804)
356 #define LCD_VSYNC_WIDTH (0x4 * 0x805)
357 #define LCD_V_BACKPORCH (0x4 * 0x806)
358 #define LCD_V_ACTIVEHEIGHT (0x4 * 0x807)
359 #define LCD_V_FRONTPORCH (0x4 * 0x808)
360 #define LCD_VSYNC_START (0x4 * 0x809)
361 #define LCD_VSYNC_END (0x4 * 0x80a)
362 #define LCD_V_BACKPORCH_EVEN (0x4 * 0x80b)
363 #define LCD_VSYNC_WIDTH_EVEN (0x4 * 0x80c)
364 #define LCD_V_ACTIVEHEIGHT_EVEN (0x4 * 0x80d)
365 #define LCD_V_FRONTPORCH_EVEN (0x4 * 0x80e)
366 #define LCD_VSYNC_START_EVEN (0x4 * 0x80f)
367 #define LCD_VSYNC_END_EVEN (0x4 * 0x810)
368 #define LCD_TIMING_GEN_TRIG (0x4 * 0x811)
369 #define LCD_PWM0_CTRL (0x4 * 0x812)
370 #define LCD_PWM0_RPT_LEADIN (0x4 * 0x813)
371 #define LCD_PWM0_HIGH_LOW (0x4 * 0x814)
372 #define LCD_PWM1_CTRL (0x4 * 0x815)
373 #define LCD_PWM1_RPT_LEADIN (0x4 * 0x816)
374 #define LCD_PWM1_HIGH_LOW (0x4 * 0x817)
375 #define LCD_PWM2_CTRL (0x4 * 0x818)
376 #define LCD_PWM2_RPT_LEADIN (0x4 * 0x819)
377 #define LCD_PWM2_HIGH_LOW (0x4 * 0x81a)
378 #define LCD_VIDEO0_DMA0_BYTES (0x4 * 0xb00)
379 #define LCD_VIDEO0_DMA0_STATE (0x4 * 0xb01)
381 #define LCD_VIDEO0_DMA1_BYTES (0x4 * 0xb02)
382 #define LCD_VIDEO0_DMA1_STATE (0x4 * 0xb03)
383 #define LCD_VIDEO0_DMA2_BYTES (0x4 * 0xb04)
384 #define LCD_VIDEO0_DMA2_STATE (0x4 * 0xb05)
385 #define LCD_VIDEO1_DMA0_BYTES (0x4 * 0xb06)
386 #define LCD_VIDEO1_DMA0_STATE (0x4 * 0xb07)
387 #define LCD_VIDEO1_DMA1_BYTES (0x4 * 0xb08)
388 #define LCD_VIDEO1_DMA1_STATE (0x4 * 0xb09)
389 #define LCD_VIDEO1_DMA2_BYTES (0x4 * 0xb0a)
390 #define LCD_VIDEO1_DMA2_STATE (0x4 * 0xb0b)
391 #define LCD_GRAPHIC0_DMA_BYTES (0x4 * 0xb0c)
392 #define LCD_GRAPHIC0_DMA_STATE (0x4 * 0xb0d)
393 #define LCD_GRAPHIC1_DMA_BYTES (0x4 * 0xb0e)
394 #define LCD_GRAPHIC1_DMA_STATE (0x4 * 0xb0f)
399 #define MIPI0_HS_BASE_ADDR (MIPI_BASE_ADDR + 0x400)
400 #define HS_OFFSET(M) (((M) + 1) * 0x400)
402 #define MIPI_TX_HS_CTRL (0x0)
404 #define HS_CTRL_EN BIT(0)
405 /* 1:CSI 0:DSI */
407 /* 1:LCD, 0:DMA */
416 #define MIPI_TX_HS_SYNC_CFG (0x8)
419 #define LINE_SYNC_PKT_ENABLE BIT(0)
434 #define MIPI_TX0_HS_FG0_SECT0_PH (0x40)
436 HS_OFFSET(M) + (0x2C * (N)) \
438 #define MIPI_TX_SECT_WC_MASK (0xffff)
441 #define MIPI_TX_SECT_DT_MASK (0x3f)
446 #define MIPI_TX_HS_FG0_SECT_UNPACKED_BYTES0 (0x60)
447 #define MIPI_TX_HS_FG0_SECT_UNPACKED_BYTES1 (0x64)
450 + HS_OFFSET(M) + (0x2C * (N)))
451 #define MIPI_TX_HS_FG0_SECT0_LINE_CFG (0x44)
454 + (0x2C * (N)) + (8 * (O)))
456 #define MIPI_TX_HS_FG0_NUM_LINES (0x68)
459 + (0x2C * (N)))
460 #define MIPI_TX_HS_VSYNC_WIDTHS0 (0x104)
463 + (0x4 * (N)))
464 #define MIPI_TX_HS_V_BACKPORCHES0 (0x16c)
467 + (0x4 * (N)))
468 #define MIPI_TX_HS_V_FRONTPORCHES0 (0x174)
471 + (0x4 * (N)))
472 #define MIPI_TX_HS_V_ACTIVE0 (0x17c)
475 + (0x4 * (N)))
476 #define MIPI_TX_HS_HSYNC_WIDTH0 (0x10c)
479 + (0x4 * (N)))
480 #define MIPI_TX_HS_H_BACKPORCH0 (0x11c)
483 + (0x4 * (N)))
484 #define MIPI_TX_HS_H_FRONTPORCH0 (0x12c)
487 + (0x4 * (N)))
488 #define MIPI_TX_HS_H_ACTIVE0 (0x184)
491 + (0x4 * (N)))
492 #define MIPI_TX_HS_LLP_HSYNC_WIDTH0 (0x13c)
495 + (0x4 * (N)))
496 #define MIPI_TX_HS_LLP_H_BACKPORCH0 (0x14c)
499 + (0x4 * (N)))
500 #define MIPI_TX_HS_LLP_H_FRONTPORCH0 (0x15c)
503 + (0x4 * (N)))
505 #define MIPI_TX_HS_MC_FIFO_CTRL_EN (0x194)
509 #define MIPI_TX_HS_MC_FIFO_CHAN_ALLOC0 (0x198)
510 #define MIPI_TX_HS_MC_FIFO_CHAN_ALLOC1 (0x19c)
513 + (0x4 * (N)))
518 #define MIPI_TX_HS_MC_FIFO_RTHRESHOLD0 (0x1a0)
519 #define MIPI_TX_HS_MC_FIFO_RTHRESHOLD1 (0x1a4)
522 + (0x4 * (N)))
526 #define MIPI_TX_HS_DMA_CFG (0x1a8)
527 #define MIPI_TX_HS_DMA_START_ADR_CHAN0 (0x1ac)
528 #define MIPI_TX_HS_DMA_LEN_CHAN0 (0x1b4)
531 #define MIPI_CTRL_IRQ_STATUS0 (0x00)
533 #define MIPI_DPHY_ERR_MASK 0x7FE /*bits 1-10 */
536 #define MIPI_HS_IRQ_MASK 0x7FE000
540 #define MIPI_CTRL_IRQ_STATUS1 (0x04)
541 #define MIPI_HS_RX_EVENT_IRQ 0
544 #define MIPI_CTRL_IRQ_ENABLE0 (0x08)
550 #define MIPI_CTRL_IRQ_ENABLE1 (0x0c)
553 #define MIPI_CTRL_IRQ_CLEAR0 (0x010)
556 #define MIPI_CTRL_IRQ_CLEAR1 (0x014)
559 #define MIPI_CTRL_DIG_LOOPBACK (0x018)
560 #define MIPI_TX_HS_IRQ_STATUS (0x01c)
617 #define MIPI_TX_HS_IRQ_ENABLE (0x020)
621 #define MIPI_TX_HS_IRQ_CLEAR (0x024)
624 #define MIPI_TX_HS_TEST_PAT_CTRL (0x230)
627 #define TP_EN_VCm(M) (1 << ((M) * 0x04))
629 ((N) << (((M) * 0x04) + 1))
631 #define MIPI_TX_HS_TEST_PAT_COLOR0 (0x234)
634 #define MIPI_TX_HS_TEST_PAT_COLOR1 (0x238)
639 #define DPHY_ENABLE (0x100)
640 #define DPHY_INIT_CTRL0 (0x104)
641 #define SHUTDOWNZ 0
643 #define DPHY_INIT_CTRL1 (0x108)
646 #define DPHY_INIT_CTRL2 (0x10c)
653 #define DPHY_INIT_CTRL2 (0x10c)
654 #define DPHY_PLL_OBS0 (0x110)
655 #define DPHY_PLL_OBS1 (0x114)
656 #define DPHY_PLL_OBS2 (0x118)
657 #define DPHY_FREQ_CTRL0_3 (0x11c)
658 #define DPHY_FREQ_CTRL4_7 (0x120)
663 #define DPHY_FORCE_CTRL0 (0x128)
664 #define DPHY_FORCE_CTRL1 (0x12C)
665 #define MIPI_DPHY_STAT0_3 (0x134)
666 #define MIPI_DPHY_STAT4_7 (0x138)
670 (((dphy % 4) * 8) + 4)) & 0x03)
672 #define MIPI_DPHY_ERR_STAT6_7 (0x14C)
674 #define DPHY_TEST_CTRL0 (0x154)
680 #define DPHY_TEST_CTRL1 (0x158)
689 #define DPHY_TEST_DIN0_3 (0x15c)
693 #define DPHY_TEST_DOUT0_3 (0x168)
696 >> (((dphy) % 4) * 8) & 0xff)
697 #define DPHY_TEST_DOUT4_7 (0x16C)
700 >> (((dphy) % 4) * 8) & 0xff)
701 #define DPHY_TEST_DOUT8_9 (0x170)
702 #define DPHY_TEST_DIN4_7 (0x160)
703 #define DPHY_TEST_DIN8_9 (0x164)
704 #define DPHY_PLL_LOCK (0x188)
708 #define DPHY_CFG_CLK_EN (0x18c)
710 #define MSS_MIPI_CIF_CFG (0x00)
711 #define MSS_LCD_MIPI_CFG (0x04)
712 #define MSS_CAM_CLK_CTRL (0x10)
713 #define MSS_LOOPBACK_CFG (0x0C)
717 #define MSS_CAM_RSTN_CTRL (0x14)
718 #define MSS_CAM_RSTN_SET (0x20)
719 #define MSS_CAM_RSTN_CLR (0x24)
721 #define MSSCPU_CPR_CLK_EN (0x0)
722 #define MSSCPU_CPR_RST_EN (0x10)
723 #define BIT_MASK_16 (0xffff)
725 #define LCD_QOS_PRIORITY (0x8)
726 #define LCD_QOS_MODE (0xC)
727 #define LCD_QOS_BW (0x10)