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/freebsd/sys/contrib/device-tree/src/arm/st/
H A Dstm32mp131.dtsi16 #size-cells = <0>;
18 cpu0: cpu@0 {
21 reg = <0>;
43 #size-cells = <0>;
44 linaro,optee-channel-id = <0>;
47 reg = <0x14>;
52 reg = <0x16>;
57 reg = <0x17>;
61 #size-cells = <0>;
63 scmi_reg11: regulator@0 {
[all …]
H A Dstm32mp151.dtsi16 #size-cells = <0>;
18 cpu0: cpu@0 {
22 reg = <0>;
42 reg = <0xa0021000 0x1000>,
43 <0xa0022000 0x2000>;
58 #clock-cells = <0>;
64 #clock-cells = <0>;
70 #clock-cells = <0>;
76 #clock-cells = <0>;
82 #clock-cells = <0>;
[all …]
H A Dstm32f429.dtsi58 #clock-cells = <0>;
60 clock-frequency = <0>;
64 #clock-cells = <0>;
70 #clock-cells = <0>;
76 #clock-cells = <0>;
78 clock-frequency = <0>;
85 reg = <0x1fff7800 0x400>;
89 reg = <0x22c 0x2>;
92 reg = <0x22e 0x2>;
98 #size-cells = <0>;
[all …]
H A Dstm32f746.dtsi53 #clock-cells = <0>;
55 clock-frequency = <0>;
59 #clock-cells = <0>;
65 #clock-cells = <0>;
71 #clock-cells = <0>;
80 #size-cells = <0>;
82 reg = <0x40000000 0x400>;
83 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
102 #size-cells = <0>;
104 reg = <0x40000400 0x400>;
[all …]
H A Dstm32h743.dtsi54 #clock-cells = <0>;
56 clock-frequency = <0>;
60 #clock-cells = <0>;
66 #clock-cells = <0>;
68 clock-frequency = <0>;
75 reg = <0x40000c00 0x400>;
82 #size-cells = <0>;
84 reg = <0x40002400 0x400>;
95 trigger@0 {
97 reg = <0>;
[all …]
H A Dstm32f7-pinctrl.dtsi15 ranges = <0 0x40020000 0x3000>;
17 st,syscfg = <&syscfg 0x8>;
24 reg = <0x0 0x400>;
25 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>;
34 reg = <0x400
[all...]
/freebsd/sys/contrib/device-tree/Bindings/crypto/
H A Dhisilicon,hip07-sec.txt9 Region 0 has registers to control the backend processing engines.
16 Interrupt 0 is for the SEC unit error queue.
29 reg = <0x400 0xd0000000 0x0 0x10000
30 0x400 0xd2000000 0x0 0x10000
31 0x400 0xd2010000 0x0 0x10000
32 0x400 0xd2020000 0x0 0x10000
33 0x400 0xd2030000 0x0 0x10000
34 0x400 0xd2040000 0x0 0x10000
35 0x400 0xd2050000 0x0 0x10000
36 0x400 0xd2060000 0x0 0x10000
[all …]
/freebsd/sys/contrib/device-tree/src/arm/aspeed/
H A Dibm-power11-quad.dtsi126 #size-cells = <0>;
129 cfam-reset-gpios = <&gpio0 ASPEED_GPIO(Q, 0) GPIO_ACTIVE_HIGH>;
131 cfam@0,0 {
132 reg = <0 0>;
135 chip-id = <0>;
139 reg = <0x1000 0x400>;
144 reg = <0x1800 0x400>;
146 #size-cells = <0>;
148 cfam0_i2c0: i2c-bus@0 {
149 reg = <0>; /* OMI01 */
[all …]
H A Daspeed-bmc-ibm-fuji.dts175 reg = <0x80000000 0x40000000>;
184 reg = <0xb3d00000 0x100000>;
190 reg = <0xb3e00000 0x200000>; /* 16 * (4 * 0x8000) */
191 record-size = <0x8000>;
192 console-size = <0x8000>;
193 ftrace-size = <0x8000>;
194 pmsg-size = <0x8000>;
200 reg = <0xb4000000 0x04000000>; /* 64M */
207 reg = <0xbf000000 0x01000000>; /* 16M */
246 gpios = <&gpio0 ASPEED_GPIO(H, 0) GPIO_ACTIVE_LOW>;
[all …]
H A Daspeed-bmc-ibm-everest.dts175 reg = <0x80000000 0x40000000>;
185 reg = <0xb3d00000 0x100000>;
190 reg = <0xb3e00000 0x200000>; /* 16 * (4 * 0x8000) */
191 record-size = <0x8000>;
192 console-size = <0x8000>;
193 ftrace-size = <0x8000>;
194 pmsg-size = <0x8000>;
201 reg = <0xb4000000 0x04000000>; /* 64M */
208 reg = <0xbf000000 0x01000000>; /* 16M */
246 gpios = <&gpio0 ASPEED_GPIO(H, 0) GPIO_ACTIVE_LOW>;
[all …]
H A Dibm-power9-dual.dtsi5 cfam@0,0 {
6 reg = <0 0>;
9 chip-id = <0>;
13 reg = <0x1000 0x400>;
18 reg = <0x1800 0x400>;
20 #size-cells = <0>;
22 cfam0_i2c0: i2c-bus@0 {
23 reg = <0>;
85 reg = <0x2400 0x400>;
87 #size-cells = <0>;
[all …]
H A Dibm-power10-dual.dtsi8 #size-cells = <0>;
10 cfam-reset-gpios = <&gpio0 ASPEED_GPIO(Q, 0) GPIO_ACTIVE_HIGH>;
12 cfam@0,0 {
13 reg = <0 0>;
16 chip-id = <0>;
20 reg = <0x1000 0x400>;
25 reg = <0x1800 0x400>;
27 #size-cells = <0>;
29 cfam0_i2c0: i2c-bus@0 {
31 #size-cells = <0>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/ti/keystone/
H A Dkeystone-k2hk-clocks.dtsi10 #clock-cells = <0>;
14 reg = <0x02620370 4>;
19 #clock-cells = <0>;
22 reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;
27 #clock-cells = <0>;
31 reg = <0x02620358 4>;
36 #clock-cells = <0>;
40 reg = <0x02620360 4>;
45 #clock-cells = <0>;
49 reg = <0x02620368 4>;
[all …]
H A Dkeystone-k2l-clocks.dtsi10 #clock-cells = <0>;
14 reg = <0x02620370 4>;
19 #clock-cells = <0>;
22 reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;
27 #clock-cells = <0>;
31 reg = <0x02620358 4>;
36 #clock-cells = <0>;
40 reg = <0x02620360 4>;
45 #clock-cells = <0>;
50 reg = <0x02350004 0xb00>, <0x02350000 0x400>;
[all …]
H A Dkeystone-clocks.dtsi14 #clock-cells = <0>;
17 reg = <0x02310108 4>;
24 #clock-cells = <0>;
33 #clock-cells = <0>;
42 #clock-cells = <0>;
45 reg = <0x02310120 4>;
46 bit-shift = <0>;
52 #clock-cells = <0>;
55 reg = <0x02310164 4>;
56 bit-shift = <0>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/st/
H A Dstm32mp251.dtsi17 #size-cells = <0>;
19 cpu0: cpu@0 {
22 reg = <0>;
38 arm,smc-id = <0xb200005a>;
44 #clock-cells = <0>;
46 clock-frequency = <0>;
50 #clock-cells = <0>;
67 #size-cells = <0>;
68 linaro,optee-channel-id = <0>;
71 reg = <0x14>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Domap2.dtsi29 #address-cells = <0>;
30 #size-cells = <0>;
61 reg = <0x480a6000 0x50>;
69 reg = <0x480b2000 0x1000>;
77 reg = <0x480FE000 0x1000>;
82 reg = <0x48056000 0x4>,
83 <0x4805602c 0x4>,
84 <0x48056028 0x4>;
98 ranges = <0 0x48056000 0x1000>;
100 sdma: dma-controller@0 {
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/allwinner/
H A Dsun50i-a100.dtsi19 #size-cells = <0>;
21 cpu0: cpu@0 {
24 reg = <0x0>;
31 reg = <0x1>;
38 reg = <0x2>;
45 reg = <0x3>;
59 #clock-cells = <0>;
67 #clock-cells = <0>;
74 #clock-cells = <0>;
93 ranges = <0
[all...]
/freebsd/sys/contrib/device-tree/src/arm/allwinner/
H A Dsuniv-f1c100s.dtsi17 #clock-cells = <0>;
24 #clock-cells = <0>;
33 #size-cells = <0>;
35 cpu@0 {
38 reg = <0x0>;
51 reg = <0x01c00000 0x30>;
58 reg = <0x00010000 0x1000>;
61 ranges = <0 0x00010000 0x1000>;
63 otg_sram: sram-section@0 {
66 reg = <0x0000 0x1000>;
[all …]
H A Dsunxi-h3-h5.dtsi87 #clock-cells = <0>;
95 #clock-cells = <0>;
118 reg = <0x01000000 0x10000>;
129 compatible = "allwinner,sun8i-h3-de2-mixer-0";
130 reg = <0x01100000 0x100000>;
139 #size-cells = <0>;
153 reg = <0x01c02000 0x1000>;
163 reg = <0x01c0c000 0x1000>;
172 #size-cells = <0>;
174 tcon0_in: port@0 {
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/renesas/
H A Dr9a07g043.dtsi17 #clock-cells = <0>;
19 clock-frequency = <0>;
24 #clock-cells = <0>;
26 clock-frequency = <0>;
32 #clock-cells = <0>;
33 clock-frequency = <0>;
39 #clock-cells = <0>;
41 clock-frequency = <0>;
44 cluster0_opp: opp-table-0 {
80 reg = <0 0x10001200 0 0xb00>;
[all …]
H A Dr9a09g057.dtsi18 #clock-cells = <0>;
20 clock-frequency = <0>;
25 #size-cells = <0>;
27 cpu0: cpu@0 {
29 reg = <0>;
37 reg = <0x100>;
45 reg = <0x200>;
53 reg = <0x300>;
59 L3_CA55: cache-controller-0 {
62 cache-size = <0x100000>;
[all …]
/freebsd/sys/contrib/device-tree/src/powerpc/fsl/
H A Dqoriq-raid1.0-0.dtsi2 * QorIQ RAID 1.0 device tree stub [ controller @ offset 0x320000 ]
36 compatible = "fsl,raideng-v1.0";
39 reg = <0x320000 0x10000>;
40 ranges = <0 0x320000 0x10000>;
43 compatible = "fsl,raideng-v1.0-job-queue";
46 reg = <0x1000 0x1000>;
47 ranges = <0x0 0x1000 0x1000>;
49 raideng_jr0: jr@0 {
50 compatible = "fsl,raideng-v1.0-job-ring", "fsl,raideng-v1.0-hp-ring";
51 reg = <0x0 0x400>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/mfd/
H A Dst,stm32-timers.yaml68 const: 0
93 "index" indicates on which break input (0 or 1) the
95 enum: [0, 1]
97 "level" gives the active level (0=low or 1=high) of the
99 enum: [0, 1]
122 "^timer@[0-9]+$":
135 minimum: 0
155 #size-cells = <0>;
157 reg = <0x40000000 0x400>;
160 dmas = <&dmamux1 18 0x400 0x1>,
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx53-ppd.dts63 reg = <0x70000000 0x20000000>,
64 <0xb0000000 0x20000000>;
69 #clock-cells = <0>;
75 #clock-cells = <0>;
106 pinctrl-0 = <&pinctrl_usb_otg_vbus>;
125 pinctrl-0 = <&pinctrl_usbh2_vbus>;
136 pinctrl-0 = <&pinctrl_usbh3_vbus>;
170 pwms = <&pwm2 0 50000 0>;
171 brightness-levels = <0 2 5 7 10 12 15 17 20 22 25 28 30 33 35
180 default-brightness-level = <0>;
[all …]

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