1*c66ec88fSEmmanuel Vadot* Hisilicon hip07 Security Accelerator (SEC) 2*c66ec88fSEmmanuel Vadot 3*c66ec88fSEmmanuel VadotRequired properties: 4*c66ec88fSEmmanuel Vadot- compatible: Must contain one of 5*c66ec88fSEmmanuel Vadot - "hisilicon,hip06-sec" 6*c66ec88fSEmmanuel Vadot - "hisilicon,hip07-sec" 7*c66ec88fSEmmanuel Vadot- reg: Memory addresses and lengths of the memory regions through which 8*c66ec88fSEmmanuel Vadot this device is controlled. 9*c66ec88fSEmmanuel Vadot Region 0 has registers to control the backend processing engines. 10*c66ec88fSEmmanuel Vadot Region 1 has registers for functionality common to all queues. 11*c66ec88fSEmmanuel Vadot Regions 2-18 have registers for the 16 individual queues which are isolated 12*c66ec88fSEmmanuel Vadot both in hardware and within the driver. 13*c66ec88fSEmmanuel Vadot- interrupts: Interrupt specifiers. 14*c66ec88fSEmmanuel Vadot Refer to interrupt-controller/interrupts.txt for generic interrupt client node 15*c66ec88fSEmmanuel Vadot bindings. 16*c66ec88fSEmmanuel Vadot Interrupt 0 is for the SEC unit error queue. 17*c66ec88fSEmmanuel Vadot Interrupt 2N + 1 is the completion interrupt for queue N. 18*c66ec88fSEmmanuel Vadot Interrupt 2N + 2 is the error interrupt for queue N. 19*c66ec88fSEmmanuel Vadot- dma-coherent: The driver assumes coherent dma is possible. 20*c66ec88fSEmmanuel Vadot 21*c66ec88fSEmmanuel VadotOptional properties: 22*c66ec88fSEmmanuel Vadot- iommus: The SEC units are behind smmu-v3 iommus. 23*c66ec88fSEmmanuel Vadot Refer to iommu/arm,smmu-v3.txt for more information. 24*c66ec88fSEmmanuel Vadot 25*c66ec88fSEmmanuel VadotExample: 26*c66ec88fSEmmanuel Vadot 27*c66ec88fSEmmanuel Vadotp1_sec_a: crypto@400d2000000 { 28*c66ec88fSEmmanuel Vadot compatible = "hisilicon,hip07-sec"; 29*c66ec88fSEmmanuel Vadot reg = <0x400 0xd0000000 0x0 0x10000 30*c66ec88fSEmmanuel Vadot 0x400 0xd2000000 0x0 0x10000 31*c66ec88fSEmmanuel Vadot 0x400 0xd2010000 0x0 0x10000 32*c66ec88fSEmmanuel Vadot 0x400 0xd2020000 0x0 0x10000 33*c66ec88fSEmmanuel Vadot 0x400 0xd2030000 0x0 0x10000 34*c66ec88fSEmmanuel Vadot 0x400 0xd2040000 0x0 0x10000 35*c66ec88fSEmmanuel Vadot 0x400 0xd2050000 0x0 0x10000 36*c66ec88fSEmmanuel Vadot 0x400 0xd2060000 0x0 0x10000 37*c66ec88fSEmmanuel Vadot 0x400 0xd2070000 0x0 0x10000 38*c66ec88fSEmmanuel Vadot 0x400 0xd2080000 0x0 0x10000 39*c66ec88fSEmmanuel Vadot 0x400 0xd2090000 0x0 0x10000 40*c66ec88fSEmmanuel Vadot 0x400 0xd20a0000 0x0 0x10000 41*c66ec88fSEmmanuel Vadot 0x400 0xd20b0000 0x0 0x10000 42*c66ec88fSEmmanuel Vadot 0x400 0xd20c0000 0x0 0x10000 43*c66ec88fSEmmanuel Vadot 0x400 0xd20d0000 0x0 0x10000 44*c66ec88fSEmmanuel Vadot 0x400 0xd20e0000 0x0 0x10000 45*c66ec88fSEmmanuel Vadot 0x400 0xd20f0000 0x0 0x10000 46*c66ec88fSEmmanuel Vadot 0x400 0xd2100000 0x0 0x10000>; 47*c66ec88fSEmmanuel Vadot interrupt-parent = <&p1_mbigen_sec_a>; 48*c66ec88fSEmmanuel Vadot iommus = <&p1_smmu_alg_a 0x600>; 49*c66ec88fSEmmanuel Vadot dma-coherent; 50*c66ec88fSEmmanuel Vadot interrupts = <576 4>, 51*c66ec88fSEmmanuel Vadot <577 1>, <578 4>, 52*c66ec88fSEmmanuel Vadot <579 1>, <580 4>, 53*c66ec88fSEmmanuel Vadot <581 1>, <582 4>, 54*c66ec88fSEmmanuel Vadot <583 1>, <584 4>, 55*c66ec88fSEmmanuel Vadot <585 1>, <586 4>, 56*c66ec88fSEmmanuel Vadot <587 1>, <588 4>, 57*c66ec88fSEmmanuel Vadot <589 1>, <590 4>, 58*c66ec88fSEmmanuel Vadot <591 1>, <592 4>, 59*c66ec88fSEmmanuel Vadot <593 1>, <594 4>, 60*c66ec88fSEmmanuel Vadot <595 1>, <596 4>, 61*c66ec88fSEmmanuel Vadot <597 1>, <598 4>, 62*c66ec88fSEmmanuel Vadot <599 1>, <600 4>, 63*c66ec88fSEmmanuel Vadot <601 1>, <602 4>, 64*c66ec88fSEmmanuel Vadot <603 1>, <604 4>, 65*c66ec88fSEmmanuel Vadot <605 1>, <606 4>, 66*c66ec88fSEmmanuel Vadot <607 1>, <608 4>; 67*c66ec88fSEmmanuel Vadot}; 68