Lines Matching +full:0 +full:x400
29 #address-cells = <0>;
30 #size-cells = <0>;
61 reg = <0x480a6000 0x50>;
69 reg = <0x480b2000 0x1000>;
77 reg = <0x480FE000 0x1000>;
82 reg = <0x48056000 0x4>,
83 <0x4805602c 0x4>,
84 <0x48056028 0x4>;
98 ranges = <0 0x48056000 0x1000>;
100 sdma: dma-controller@0 {
102 reg = <0 0x1000>;
116 reg = <0x48070000 0x80>;
118 #size-cells = <0>;
125 reg = <0x48072000 0x80>;
127 #size-cells = <0>;
134 reg = <0x48098000 0x100>;
145 reg = <0x4809a000 0x100>;
154 reg = <0x480a0000 0x50>;
161 reg = <0x480a4000 0x64>;
170 reg = <0x4806a000 0x2000>;
180 reg = <0x4806c000 0x400>;
190 reg = <0x4806e000 0x400>;
199 reg = <0x4802a000 0x4>,
200 <0x4802a010 0x4>,
201 <0x4802a014 0x4>;
216 ranges = <0x0 0x4802a000 0x1000>;
218 timer2: timer@0 {
220 reg = <0 0x400>;
227 reg = <0x48078000 0x400>;
234 reg = <0x4807a000 0x400>;
241 reg = <0x4807c000 0x400>;
249 reg = <0x4807e000 0x400>;
257 reg = <0x48080000 0x400>;
265 reg = <0x48082000 0x400>;
273 reg = <0x48084000 0x400>;
281 reg = <0x48086000 0x400>;
289 reg = <0x48088000 0x400>;
297 reg = <0x4808a000 0x400>;
305 reg = <0x48050000 0x400>;
314 reg = <0x48050400 0x400>;
321 reg = <0x48050800 0x400>;
328 reg = <0x48050c00 0x400>;