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/linux/sound/soc/fsl/
H A Dfsl_audmix.h15 #define FSL_AUDMIX_CTR 0x200 /* Control */
16 #define FSL_AUDMIX_STR 0x204 /* Status */
18 #define FSL_AUDMIX_ATCR0 0x208 /* Attenuation Control */
19 #define FSL_AUDMIX_ATIVAL0 0x20c /* Attenuation Initial Value */
20 #define FSL_AUDMIX_ATSTPUP0 0x210 /* Attenuation step up factor */
21 #define FSL_AUDMIX_ATSTPDN0 0x214 /* Attenuation step down factor */
22 #define FSL_AUDMIX_ATSTPTGT0 0x218 /* Attenuation step target */
23 #define FSL_AUDMIX_ATTNVAL0 0x21c /* Attenuation Value */
24 #define FSL_AUDMIX_ATSTP0 0x220 /* Attenuation step number */
26 #define FSL_AUDMIX_ATCR1 0x228 /* Attenuation Control */
[all …]
H A Dfsl_audmix.c38 SOC_ENUM_SINGLE_S(FSL_AUDMIX_ATCR0, 0, endis_sel),
41 SOC_ENUM_SINGLE_S(FSL_AUDMIX_ATCR1, 0, endis_sel),
53 { .tdms = 0, .clk = 0, .msg = "" },
59 { .tdms = 3, .clk = 0, .msg = "DIS->MIX: Please start both TDMs!\n" }
61 { .tdms = 1, .clk = 0, .msg = "TDM1->DIS: TDM1 not started!\n" },
63 { .tdms = 0, .clk = 0, .msg = "" },
67 { .tdms = 3, .clk = 0, .msg = "TDM1->MIX: Please start both TDMs!\n" }
69 { .tdms = 2, .clk = 0, .msg = "TDM2->DIS: TDM2 not started!\n" },
73 { .tdms = 0, .clk = 0, .msg = "" },
75 { .tdms = 3, .clk = 0, .msg = "TDM2->MIX: Please start both TDMs!\n" }
[all …]
/linux/drivers/gpu/drm/mxsfb/
H A Dmxsfb_regs.h15 #define LCDC_CTRL 0x00
16 #define LCDC_CTRL1 0x10
17 #define LCDC_V3_TRANSFER_COUNT 0x20
18 #define LCDC_V4_CTRL2 0x20
19 #define LCDC_V4_TRANSFER_COUNT 0x30
20 #define LCDC_V4_CUR_BUF 0x40
21 #define LCDC_V4_NEXT_BUF 0x50
22 #define LCDC_V3_CUR_BUF 0x30
23 #define LCDC_V3_NEXT_BUF 0x40
24 #define LCDC_VDCTRL0 0x70
[all …]
H A Dlcdif_regs.h15 #define LCDC_V8_CTRL 0x00
16 #define LCDC_V8_DISP_PARA 0x10
17 #define LCDC_V8_DISP_SIZE 0x14
18 #define LCDC_V8_HSYN_PARA 0x18
19 #define LCDC_V8_VSYN_PARA 0x1c
20 #define LCDC_V8_VSYN_HSYN_WIDTH 0x20
21 #define LCDC_V8_INT_STATUS_D0 0x24
22 #define LCDC_V8_INT_ENABLE_D0 0x28
23 #define LCDC_V8_INT_STATUS_D1 0x30
24 #define LCDC_V8_INT_ENABLE_D1 0x34
[all …]
/linux/sound/soc/mediatek/mt6797/
H A Dmt6797-reg.h12 #define AUDIO_TOP_CON0 0x0000
13 #define AUDIO_TOP_CON1 0x0004
14 #define AUDIO_TOP_CON3 0x000c
15 #define AFE_DAC_CON0 0x0010
16 #define AFE_DAC_CON1 0x0014
17 #define AFE_I2S_CON 0x0018
18 #define AFE_DAIBT_CON0 0x001c
19 #define AFE_CONN0 0x0020
20 #define AFE_CONN1 0x0024
21 #define AFE_CONN2 0x0028
[all …]
/linux/drivers/accel/habanalabs/include/goya/asic_reg/
H A Dmmu_masks.h23 #define MMU_INPUT_FIFO_THRESHOLD_PCI_SHIFT 0
24 #define MMU_INPUT_FIFO_THRESHOLD_PCI_MASK 0x7
26 #define MMU_INPUT_FIFO_THRESHOLD_PSOC_MASK 0x70
28 #define MMU_INPUT_FIFO_THRESHOLD_DMA_MASK 0x700
30 #define MMU_INPUT_FIFO_THRESHOLD_CPU_MASK 0x7000
32 #define MMU_INPUT_FIFO_THRESHOLD_MME_MASK 0x70000
34 #define MMU_INPUT_FIFO_THRESHOLD_TPC_MASK 0x700000
36 #define MMU_INPUT_FIFO_THRESHOLD_OTHER_MASK 0x7000000
39 #define MMU_MMU_ENABLE_R_SHIFT 0
40 #define MMU_MMU_ENABLE_R_MASK 0x1
[all …]
H A Ddma_macro_masks.h23 #define DMA_MACRO_LBW_RANGE_HIT_BLOCK_R_SHIFT 0
24 #define DMA_MACRO_LBW_RANGE_HIT_BLOCK_R_MASK 0xFFFF
27 #define DMA_MACRO_LBW_RANGE_MASK_R_SHIFT 0
28 #define DMA_MACRO_LBW_RANGE_MASK_R_MASK 0x3FFFFFF
31 #define DMA_MACRO_LBW_RANGE_BASE_R_SHIFT 0
32 #define DMA_MACRO_LBW_RANGE_BASE_R_MASK 0x3FFFFFF
35 #define DMA_MACRO_HBW_RANGE_HIT_BLOCK_R_SHIFT 0
36 #define DMA_MACRO_HBW_RANGE_HIT_BLOCK_R_MASK 0xFF
39 #define DMA_MACRO_HBW_RANGE_MASK_49_32_R_SHIFT 0
40 #define DMA_MACRO_HBW_RANGE_MASK_49_32_R_MASK 0x3FFFF
[all …]
H A Dpci_nrtr_masks.h23 #define PCI_NRTR_HBW_MAX_CRED_WR_RQ_SHIFT 0
24 #define PCI_NRTR_HBW_MAX_CRED_WR_RQ_MASK 0x3F
26 #define PCI_NRTR_HBW_MAX_CRED_WR_RS_MASK 0x3F00
28 #define PCI_NRTR_HBW_MAX_CRED_RD_RQ_MASK 0x3F0000
30 #define PCI_NRTR_HBW_MAX_CRED_RD_RS_MASK 0x3F000000
33 #define PCI_NRTR_LBW_MAX_CRED_WR_RQ_SHIFT 0
34 #define PCI_NRTR_LBW_MAX_CRED_WR_RQ_MASK 0x3F
36 #define PCI_NRTR_LBW_MAX_CRED_WR_RS_MASK 0x3F00
38 #define PCI_NRTR_LBW_MAX_CRED_RD_RQ_MASK 0x3F0000
40 #define PCI_NRTR_LBW_MAX_CRED_RD_RS_MASK 0x3F000000
[all …]
H A Dtpc0_nrtr_masks.h23 #define TPC0_NRTR_HBW_MAX_CRED_WR_RQ_SHIFT 0
24 #define TPC0_NRTR_HBW_MAX_CRED_WR_RQ_MASK 0x3F
26 #define TPC0_NRTR_HBW_MAX_CRED_WR_RS_MASK 0x3F00
28 #define TPC0_NRTR_HBW_MAX_CRED_RD_RQ_MASK 0x3F0000
30 #define TPC0_NRTR_HBW_MAX_CRED_RD_RS_MASK 0x3F000000
33 #define TPC0_NRTR_LBW_MAX_CRED_WR_RQ_SHIFT 0
34 #define TPC0_NRTR_LBW_MAX_CRED_WR_RQ_MASK 0x3F
36 #define TPC0_NRTR_LBW_MAX_CRED_WR_RS_MASK 0x3F00
38 #define TPC0_NRTR_LBW_MAX_CRED_RD_RQ_MASK 0x3F0000
40 #define TPC0_NRTR_LBW_MAX_CRED_RD_RS_MASK 0x3F000000
[all …]
H A Ddma_nrtr_masks.h23 #define DMA_NRTR_HBW_MAX_CRED_WR_RQ_SHIFT 0
24 #define DMA_NRTR_HBW_MAX_CRED_WR_RQ_MASK 0x3F
26 #define DMA_NRTR_HBW_MAX_CRED_WR_RS_MASK 0x3F00
28 #define DMA_NRTR_HBW_MAX_CRED_RD_RQ_MASK 0x3F0000
30 #define DMA_NRTR_HBW_MAX_CRED_RD_RS_MASK 0x3F000000
33 #define DMA_NRTR_LBW_MAX_CRED_WR_RQ_SHIFT 0
34 #define DMA_NRTR_LBW_MAX_CRED_WR_RQ_MASK 0x3F
36 #define DMA_NRTR_LBW_MAX_CRED_WR_RS_MASK 0x3F00
38 #define DMA_NRTR_LBW_MAX_CRED_RD_RQ_MASK 0x3F0000
40 #define DMA_NRTR_LBW_MAX_CRED_RD_RS_MASK 0x3F000000
[all …]
/linux/sound/soc/mediatek/mt8183/
H A Dmt8183-afe-pcm.c24 MTK_AFE_RATE_8K = 0,
43 MTK_AFE_DAI_MEMIF_RATE_8K = 0,
50 MTK_AFE_PCM_RATE_8K = 0,
139 .fifo_size = 0,
149 int id = snd_soc_rtd_to_cpu(rtd, 0)->id; in mt8183_memif_fs()
294 I_ADDA_UL_CH1, 1, 0),
296 I_I2S0_CH1, 1, 0),
301 I_ADDA_UL_CH2, 1, 0),
303 I_I2S0_CH2, 1, 0),
308 I_ADDA_UL_CH1, 1, 0),
[all …]
/linux/Documentation/devicetree/bindings/iio/adc/
H A Dti,am3359-adc.yaml27 description: List of analog inputs available for ADC. AIN0 = 0, AIN1 = 1 and
37 the start of ADC conversion. Maximum value is 0x3FFFF.
45 to sample (to hold start of conversion high). Maximum value is 0xFF.
72 ti,chan-step-opendelay = <0x098 0x3ffff 0x098 0x0>;
73 ti,chan-step-sampledelay = <0xff 0x0 0xf 0x0>;
/linux/drivers/gpu/drm/msm/adreno/
H A Da6xx_gpu.h61 (((_len) & 0x3FFF) << 18) | ((_reg) & 0x3FFFF))
69 ((((_len) & 0x3FFF) << 18) | ((_reg) & 0x3FFFF))
/linux/sound/soc/mediatek/mt8173/
H A Dmt8173-afe-pcm.c27 #define AUDIO_TOP_CON0 0x0000
28 #define AUDIO_TOP_CON1 0x0004
29 #define AFE_DAC_CON0 0x0010
30 #define AFE_DAC_CON1 0x0014
31 #define AFE_I2S_CON1 0x0034
32 #define AFE_I2S_CON2 0x0038
33 #define AFE_CONN_24BIT 0x006c
34 #define AFE_MEMIF_MSB 0x00cc
36 #define AFE_CONN1 0x0024
37 #define AFE_CONN2 0x0028
[all …]
/linux/drivers/comedi/drivers/
H A Dni_pcimio.c110 RANGE_ext(0, 1)
117 * 0V, 5V, APFI<0,1>, or AO<0...3> and RANGE can
118 * be 10V, 5V, 2V, 1V, APFI<0,1>, AO<0...3>. That's
219 .ai_maxdata = 0xffff,
225 .ao_maxdata = 0x0fff,
233 .ai_maxdata = 0xffff,
239 .ao_maxdata = 0xffff,
248 .ai_maxdata = 0xffff,
254 .ao_maxdata = 0xffff,
262 .ai_maxdata = 0xffff,
[all …]
/linux/tools/testing/selftests/powerpc/include/
H A Dinstructions.h10 (0x7c00060c | (RA) << (31-15) | (RB) << (31-20) | (L) << (31-10))
16 asm volatile(str(COPY(0, %0, 0))";" in copy()
25 asm volatile(str(COPY(0, %0, 1))";" in copy_first()
34 (0x7c00070c | (RA) << (31-15) | (RB) << (31-20) | (L) << (31-10) | (RC) << (31-31))
42 asm volatile(str(PASTE(0, %1, 0, 0))";" in paste()
43 "mfcr %0;" in paste()
55 asm volatile(str(PASTE(0, %1, 1, 1))";" in paste_last()
56 "mfcr %0;" in paste_last()
64 #define PPC_INST_COPY __COPY(0, 0, 0)
65 #define PPC_INST_COPY_FIRST __COPY(0, 0, 1)
[all …]
/linux/arch/arm64/include/asm/
H A Delf.h21 #define R_ARM_NONE 0
156 * registered with atexit, as per the SVR4 ABI. A value of 0 means we have no
159 #define ELF_PLAT_INIT(_r, load_addr) (_r)->regs[0] = 0
181 NEW_AUX_ENT(AT_IGNORE, 0); \
182 } while (0)
192 0x7ff >> (PAGE_SHIFT - 12) : \
193 0x3ffff >> (PAGE_SHIFT - 12))
195 #define STACK_RND_MASK (0x3ffff >> (PAGE_SHIFT - 12))
212 #define COMPAT_ELF_ET_DYN_BASE 0x000400000UL
215 #define EF_ARM_EABI_MASK 0xff000000
[all …]
/linux/drivers/accel/habanalabs/include/gaudi2/asic_reg/
H A Ddcore0_edma0_core_masks.h24 #define DCORE0_EDMA0_CORE_CFG_0_EN_SHIFT 0
25 #define DCORE0_EDMA0_CORE_CFG_0_EN_MASK 0x1
28 #define DCORE0_EDMA0_CORE_CFG_1_HALT_SHIFT 0
29 #define DCORE0_EDMA0_CORE_CFG_1_HALT_MASK 0x1
31 #define DCORE0_EDMA0_CORE_CFG_1_FLUSH_MASK 0x2
34 #define DCORE0_EDMA0_CORE_PROT_VAL_SHIFT 0
35 #define DCORE0_EDMA0_CORE_PROT_VAL_MASK 0x1
37 #define DCORE0_EDMA0_CORE_PROT_ERR_VAL_MASK 0x2
40 #define DCORE0_EDMA0_CORE_CKG_HBW_RBUF_SHIFT 0
41 #define DCORE0_EDMA0_CORE_CKG_HBW_RBUF_MASK 0x1
[all …]
H A Darc_farm_kdma_masks.h24 #define ARC_FARM_KDMA_CFG_0_EN_SHIFT 0
25 #define ARC_FARM_KDMA_CFG_0_EN_MASK 0x1
28 #define ARC_FARM_KDMA_CFG_1_HALT_SHIFT 0
29 #define ARC_FARM_KDMA_CFG_1_HALT_MASK 0x1
31 #define ARC_FARM_KDMA_CFG_1_FLUSH_MASK 0x2
34 #define ARC_FARM_KDMA_PROT_VAL_SHIFT 0
35 #define ARC_FARM_KDMA_PROT_VAL_MASK 0x1
37 #define ARC_FARM_KDMA_PROT_ERR_VAL_MASK 0x2
40 #define ARC_FARM_KDMA_CKG_HBW_RBUF_SHIFT 0
41 #define ARC_FARM_KDMA_CKG_HBW_RBUF_MASK 0x1
[all …]
H A Dpdma0_core_masks.h24 #define PDMA0_CORE_CFG_0_EN_SHIFT 0
25 #define PDMA0_CORE_CFG_0_EN_MASK 0x1
28 #define PDMA0_CORE_CFG_1_HALT_SHIFT 0
29 #define PDMA0_CORE_CFG_1_HALT_MASK 0x1
31 #define PDMA0_CORE_CFG_1_FLUSH_MASK 0x2
34 #define PDMA0_CORE_PROT_VAL_SHIFT 0
35 #define PDMA0_CORE_PROT_VAL_MASK 0x1
37 #define PDMA0_CORE_PROT_ERR_VAL_MASK 0x2
40 #define PDMA0_CORE_CKG_HBW_RBUF_SHIFT 0
41 #define PDMA0_CORE_CKG_HBW_RBUF_MASK 0x1
[all …]
/linux/drivers/video/fbdev/omap/
H A Dsossi.c24 #define OMAP_SOSSI_BASE 0xfffbac00
25 #define SOSSI_ID_REG 0x00
26 #define SOSSI_INIT1_REG 0x04
27 #define SOSSI_INIT2_REG 0x08
28 #define SOSSI_INIT3_REG 0x0c
29 #define SOSSI_FIFO_REG 0x10
30 #define SOSSI_REOTABLE_REG 0x14
31 #define SOSSI_TEARING_REG 0x18
32 #define SOSSI_INIT1B_REG 0x1c
33 #define SOSSI_FIFOB_REG 0x20
[all …]
/linux/drivers/net/ethernet/netronome/nfp/nfpcore/
H A Dnfp_arm.h12 #define NFP_ARM_QUEUE(_q) (0x100000 + (0x800 * ((_q) & 0xff)))
13 #define NFP_ARM_IM 0x200000
14 #define NFP_ARM_EM 0x300000
15 #define NFP_ARM_GCSR 0x400000
16 #define NFP_ARM_MPCORE 0x800000
17 #define NFP_ARM_PL310 0xa00000
19 #define NFP_ARM_GCSR_BULK_BAR(_bar) (0x0 + (0x4 * ((_bar) & 0x7)))
20 #define NFP_ARM_GCSR_BULK_BAR_TYPE (0x1 << 31)
21 #define NFP_ARM_GCSR_BULK_BAR_TYPE_BULK (0x0)
22 #define NFP_ARM_GCSR_BULK_BAR_TYPE_EXPA (0x80000000)
[all …]
/linux/drivers/gpu/drm/tests/
H A Ddrm_plane_helper_test.c20 DRM_MODE("1024x768", 0, 65000, 1024, 1048,
21 1184, 1344, 0, 768, 771, 777, 806, 0,
79 return 0; in drm_plane_helper_init()
88 KUNIT_ASSERT_GE_MSG(test, plane_state->src.x1, 0, in check_src_eq()
89 "src x coordinate %x should never be below 0, src: " DRM_RECT_FP_FMT, in check_src_eq()
92 KUNIT_ASSERT_GE_MSG(test, plane_state->src.y1, 0, in check_src_eq()
93 "src y coordinate %x should never be below 0, src: " DRM_RECT_FP_FMT, in check_src_eq()
122 0, params->msg); in drm_test_check_plane_state()
140 .src = { 0, 0,
143 .crtc = { 0, 0, 2048, 2048 },
[all …]
/linux/include/linux/
H A Dkdev_t.h43 return (minor & 0xff) | (major << 8) | ((minor & ~0xff) << 12); in new_encode_dev()
48 unsigned major = (dev & 0xfff00) >> 8; in new_decode_dev()
49 unsigned minor = (dev & 0xff) | ((dev >> 12) & 0xfff00); in new_decode_dev()
75 return (dev >> 18) & 0x3fff; in sysv_major()
80 return dev & 0x3ffff; in sysv_minor()
/linux/include/uapi/linux/can/
H A Dj1939.h19 #define J1939_MAX_UNICAST_ADDR 0xfd
20 #define J1939_IDLE_ADDR 0xfe
21 #define J1939_NO_ADDR 0xff /* == broadcast or no addr */
22 #define J1939_NO_NAME 0
23 #define J1939_PGN_REQUEST 0x0ea00 /* Request PG */
24 #define J1939_PGN_ADDRESS_CLAIMED 0x0ee00 /* Address Claimed */
25 #define J1939_PGN_ADDRESS_COMMANDED 0x0fed8 /* Commanded Address */
26 #define J1939_PGN_PDU1_MAX 0x3ff00
27 #define J1939_PGN_MAX 0x3ffff
28 #define J1939_NO_PGN 0x40000
[all …]

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