Lines Matching +full:0 +full:x3ffff
27 #define AUDIO_TOP_CON0 0x0000
28 #define AUDIO_TOP_CON1 0x0004
29 #define AFE_DAC_CON0 0x0010
30 #define AFE_DAC_CON1 0x0014
31 #define AFE_I2S_CON1 0x0034
32 #define AFE_I2S_CON2 0x0038
33 #define AFE_CONN_24BIT 0x006c
34 #define AFE_MEMIF_MSB 0x00cc
36 #define AFE_CONN1 0x0024
37 #define AFE_CONN2 0x0028
38 #define AFE_CONN3 0x002c
39 #define AFE_CONN7 0x0460
40 #define AFE_CONN8 0x0464
41 #define AFE_HDMI_CONN0 0x0390
44 #define AFE_DL1_BASE 0x0040
45 #define AFE_DL1_CUR 0x0044
46 #define AFE_DL1_END 0x0048
47 #define AFE_DL2_BASE 0x0050
48 #define AFE_DL2_CUR 0x0054
49 #define AFE_AWB_BASE 0x0070
50 #define AFE_AWB_CUR 0x007c
51 #define AFE_VUL_BASE 0x0080
52 #define AFE_VUL_CUR 0x008c
53 #define AFE_VUL_END 0x0088
54 #define AFE_DAI_BASE 0x0090
55 #define AFE_DAI_CUR 0x009c
56 #define AFE_MOD_PCM_BASE 0x0330
57 #define AFE_MOD_PCM_CUR 0x033c
58 #define AFE_HDMI_OUT_BASE 0x0374
59 #define AFE_HDMI_OUT_CUR 0x0378
60 #define AFE_HDMI_OUT_END 0x037c
62 #define AFE_ADDA_TOP_CON0 0x0120
63 #define AFE_ADDA2_TOP_CON0 0x0600
65 #define AFE_HDMI_OUT_CON0 0x0370
67 #define AFE_IRQ_MCU_CON 0x03a0
68 #define AFE_IRQ_STATUS 0x03a4
69 #define AFE_IRQ_CLR 0x03a8
70 #define AFE_IRQ_CNT1 0x03ac
71 #define AFE_IRQ_CNT2 0x03b0
72 #define AFE_IRQ_MCU_EN 0x03b4
73 #define AFE_IRQ_CNT5 0x03bc
74 #define AFE_IRQ_CNT7 0x03dc
76 #define AFE_TDM_CON1 0x0548
77 #define AFE_TDM_CON2 0x054c
79 #define AFE_IRQ_STATUS_BITS 0xff
81 /* AUDIO_TOP_CON0 (0x0000) */
82 #define AUD_TCON0_PDN_SPDF (0x1 << 21)
83 #define AUD_TCON0_PDN_HDMI (0x1 << 20)
84 #define AUD_TCON0_PDN_24M (0x1 << 9)
85 #define AUD_TCON0_PDN_22M (0x1 << 8)
86 #define AUD_TCON0_PDN_AFE (0x1 << 2)
88 /* AFE_I2S_CON1 (0x0034) */
89 #define AFE_I2S_CON1_LOW_JITTER_CLK (0x1 << 12)
90 #define AFE_I2S_CON1_RATE(x) (((x) & 0xf) << 8)
91 #define AFE_I2S_CON1_FORMAT_I2S (0x1 << 3)
92 #define AFE_I2S_CON1_EN (0x1 << 0)
94 /* AFE_I2S_CON2 (0x0038) */
95 #define AFE_I2S_CON2_LOW_JITTER_CLK (0x1 << 12)
96 #define AFE_I2S_CON2_RATE(x) (((x) & 0xf) << 8)
97 #define AFE_I2S_CON2_FORMAT_I2S (0x1 << 3)
98 #define AFE_I2S_CON2_EN (0x1 << 0)
100 /* AFE_CONN_24BIT (0x006c) */
101 #define AFE_CONN_24BIT_O04 (0x1 << 4)
102 #define AFE_CONN_24BIT_O03 (0x1 << 3)
104 /* AFE_HDMI_CONN0 (0x0390) */
105 #define AFE_HDMI_CONN0_O37_I37 (0x7 << 21)
106 #define AFE_HDMI_CONN0_O36_I36 (0x6 << 18)
107 #define AFE_HDMI_CONN0_O35_I33 (0x3 << 15)
108 #define AFE_HDMI_CONN0_O34_I32 (0x2 << 12)
109 #define AFE_HDMI_CONN0_O33_I35 (0x5 << 9)
110 #define AFE_HDMI_CONN0_O32_I34 (0x4 << 6)
111 #define AFE_HDMI_CONN0_O31_I31 (0x1 << 3)
112 #define AFE_HDMI_CONN0_O30_I30 (0x0 << 0)
114 /* AFE_TDM_CON1 (0x0548) */
116 #define AFE_TDM_CON1_32_BCK_CYCLES (0x2 << 12)
117 #define AFE_TDM_CON1_WLEN_32BIT (0x2 << 8)
118 #define AFE_TDM_CON1_MSB_ALIGNED (0x1 << 4)
119 #define AFE_TDM_CON1_1_BCK_DELAY (0x1 << 3)
120 #define AFE_TDM_CON1_LRCK_INV (0x1 << 2)
121 #define AFE_TDM_CON1_BCK_INV (0x1 << 1)
122 #define AFE_TDM_CON1_EN (0x1 << 0)
125 AFE_TDM_CH_START_O30_O31 = 0,
161 .fifo_size = 0,
170 { .rate = 8000, .regvalue = 0 },
189 for (i = 0; i < ARRAY_SIZE(mt8173_afe_i2s_rates); i++) in mt8173_afe_i2s_fs()
201 if (fs < 0) in mt8173_afe_set_i2s()
205 regmap_update_bits(afe->regmap, AFE_ADDA_TOP_CON0, 0x1, 0x1); in mt8173_afe_set_i2s()
206 regmap_update_bits(afe->regmap, AFE_ADDA2_TOP_CON0, 0x1, 0x1); in mt8173_afe_set_i2s()
221 return 0; in mt8173_afe_set_i2s()
233 regmap_update_bits(afe->regmap, AFE_I2S_CON2, 0x1, enable); in mt8173_afe_set_i2s_enable()
236 regmap_update_bits(afe->regmap, AFE_I2S_CON1, 0x1, enable); in mt8173_afe_set_i2s_enable()
259 return 0; in mt8173_afe_dais_enable_clks()
283 return 0; in mt8173_afe_dais_set_clks()
299 return 0; in mt8173_afe_i2s_startup()
302 AUD_TCON0_PDN_22M | AUD_TCON0_PDN_24M, 0); in mt8173_afe_i2s_startup()
303 return 0; in mt8173_afe_i2s_startup()
329 runtime->rate * 256, NULL, 0); in mt8173_afe_i2s_prepare()
331 runtime->rate * 256, NULL, 0); in mt8173_afe_i2s_prepare()
339 return 0; in mt8173_afe_i2s_prepare()
349 return 0; in mt8173_afe_hdmi_startup()
353 return 0; in mt8173_afe_hdmi_startup()
423 val = 0; in mt8173_afe_hdmi_prepare()
425 regmap_update_bits(afe->regmap, AFE_TDM_CON2, 0x0000ffff, val); in mt8173_afe_hdmi_prepare()
428 0x000000f0, runtime->channels << 4); in mt8173_afe_hdmi_prepare()
429 return 0; in mt8173_afe_hdmi_prepare()
443 AUD_TCON0_PDN_HDMI | AUD_TCON0_PDN_SPDF, 0); in mt8173_afe_hdmi_trigger()
457 regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0, 0x1, 0x1); in mt8173_afe_hdmi_trigger()
460 regmap_update_bits(afe->regmap, AFE_TDM_CON1, 0x1, 0x1); in mt8173_afe_hdmi_trigger()
462 return 0; in mt8173_afe_hdmi_trigger()
466 regmap_update_bits(afe->regmap, AFE_TDM_CON1, 0x1, 0); in mt8173_afe_hdmi_trigger()
469 regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0, 0x1, 0); in mt8173_afe_hdmi_trigger()
474 return 0; in mt8173_afe_hdmi_trigger()
486 struct mtk_base_afe_memif *memif = &afe->memif[snd_soc_rtd_to_cpu(rtd, 0)->id]; in mt8173_memif_fs()
493 fs = 0; in mt8173_memif_fs()
611 SOC_DAPM_SINGLE_AUTODISABLE("I05 Switch", AFE_CONN1, 21, 1, 0),
615 SOC_DAPM_SINGLE_AUTODISABLE("I06 Switch", AFE_CONN2, 6, 1, 0),
619 SOC_DAPM_SINGLE_AUTODISABLE("I03 Switch", AFE_CONN3, 0, 1, 0),
620 SOC_DAPM_SINGLE_AUTODISABLE("I17 Switch", AFE_CONN7, 30, 1, 0),
624 SOC_DAPM_SINGLE_AUTODISABLE("I04 Switch", AFE_CONN3, 3, 1, 0),
625 SOC_DAPM_SINGLE_AUTODISABLE("I18 Switch", AFE_CONN8, 0, 1, 0),
630 SND_SOC_DAPM_MIXER("I03", SND_SOC_NOPM, 0, 0, NULL, 0),
631 SND_SOC_DAPM_MIXER("I04", SND_SOC_NOPM, 0, 0, NULL, 0),
632 SND_SOC_DAPM_MIXER("I05", SND_SOC_NOPM, 0, 0, NULL, 0),
633 SND_SOC_DAPM_MIXER("I06", SND_SOC_NOPM, 0, 0, NULL, 0),
634 SND_SOC_DAPM_MIXER("I17", SND_SOC_NOPM, 0, 0, NULL, 0),
635 SND_SOC_DAPM_MIXER("I18", SND_SOC_NOPM, 0, 0, NULL, 0),
637 SND_SOC_DAPM_MIXER("O03", SND_SOC_NOPM, 0, 0,
639 SND_SOC_DAPM_MIXER("O04", SND_SOC_NOPM, 0, 0,
641 SND_SOC_DAPM_MIXER("O09", SND_SOC_NOPM, 0, 0,
643 SND_SOC_DAPM_MIXER("O10", SND_SOC_NOPM, 0, 0,
708 .fs_shift = 0,
709 .fs_maskbit = 0xf,
716 .msb_shift = 0,
725 .fs_maskbit = 0xf,
741 .fs_maskbit = 0xf,
757 .fs_maskbit = 0x3,
773 .fs_maskbit = 0xf,
789 .fs_maskbit = 0x3,
820 .irq_cnt_shift = 0,
821 .irq_cnt_maskbit = 0x3ffff,
823 .irq_en_shift = 0,
826 .irq_fs_maskbit = 0xf,
828 .irq_clr_shift = 0,
833 .irq_cnt_maskbit = 0x3ffff,
838 .irq_fs_maskbit = 0xf,
845 .irq_cnt_shift = 0,
846 .irq_cnt_maskbit = 0x3ffff,
851 .irq_fs_maskbit = 0xf,
858 .irq_cnt_maskbit = 0x3ffff,
863 .irq_fs_maskbit = 0xf,
869 .irq_cnt_shift = 0,
870 .irq_cnt_maskbit = 0x3ffff,
875 .irq_fs_maskbit = 0xf,
882 .irq_cnt_maskbit = 0x3ffff,
887 .irq_fs_maskbit = 0xf,
893 .irq_cnt_shift = 0,
894 .irq_cnt_maskbit = 0x3ffff,
925 for (i = 0; i < MT8173_AFE_MEMIF_NUM; i++) { in mt8173_afe_irq_handler()
929 if (memif->irq_usage < 0) in mt8173_afe_irq_handler()
954 regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0); in mt8173_afe_runtime_suspend()
967 return 0; in mt8173_afe_runtime_suspend()
1003 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0, AUD_TCON0_PDN_AFE, 0); in mt8173_afe_runtime_resume()
1007 AFE_CONN_24BIT_O03 | AFE_CONN_24BIT_O04, 0); in mt8173_afe_runtime_resume()
1010 regmap_update_bits(afe->regmap, AFE_IRQ_MCU_EN, 0xff, 0xff); in mt8173_afe_runtime_resume()
1013 regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x1); in mt8173_afe_runtime_resume()
1014 return 0; in mt8173_afe_runtime_resume()
1036 for (i = 0; i < ARRAY_SIZE(aud_clks); i++) { in mt8173_afe_init_audio_clk()
1046 return 0; in mt8173_afe_init_audio_clk()
1073 irq_id = platform_get_irq(pdev, 0); in mt8173_afe_pcm_dev_probe()
1074 if (irq_id <= 0) in mt8173_afe_pcm_dev_probe()
1075 return irq_id < 0 ? irq_id : -ENXIO; in mt8173_afe_pcm_dev_probe()
1077 afe->base_addr = devm_platform_ioremap_resource(pdev, 0); in mt8173_afe_pcm_dev_probe()
1106 for (i = 0; i < afe->irqs_size; i++) { in mt8173_afe_pcm_dev_probe()
1134 NULL, 0); in mt8173_afe_pcm_dev_probe()
1183 0, "Afe_ISR_Handle", (void *)afe); in mt8173_afe_pcm_dev_probe()
1190 return 0; in mt8173_afe_pcm_dev_probe()