Lines Matching +full:0 +full:x3ffff
15 #define LCDC_V8_CTRL 0x00
16 #define LCDC_V8_DISP_PARA 0x10
17 #define LCDC_V8_DISP_SIZE 0x14
18 #define LCDC_V8_HSYN_PARA 0x18
19 #define LCDC_V8_VSYN_PARA 0x1c
20 #define LCDC_V8_VSYN_HSYN_WIDTH 0x20
21 #define LCDC_V8_INT_STATUS_D0 0x24
22 #define LCDC_V8_INT_ENABLE_D0 0x28
23 #define LCDC_V8_INT_STATUS_D1 0x30
24 #define LCDC_V8_INT_ENABLE_D1 0x34
25 #define LCDC_V8_CTRLDESCL0_1 0x200
26 #define LCDC_V8_CTRLDESCL0_3 0x208
27 #define LCDC_V8_CTRLDESCL_LOW0_4 0x20c
28 #define LCDC_V8_CTRLDESCL_HIGH0_4 0x210
29 #define LCDC_V8_CTRLDESCL0_5 0x214
30 #define LCDC_V8_CSC0_CTRL 0x21c
31 #define LCDC_V8_CSC0_COEF0 0x220
32 #define LCDC_V8_CSC0_COEF1 0x224
33 #define LCDC_V8_CSC0_COEF2 0x228
34 #define LCDC_V8_CSC0_COEF3 0x22c
35 #define LCDC_V8_CSC0_COEF4 0x230
36 #define LCDC_V8_CSC0_COEF5 0x234
37 #define LCDC_V8_PANIC0_THRES 0x238
45 #define CTRL_BUS_WIDTH_16 (0 << 10)
49 #define CTRL_BUS_WIDTH_MASK (0x3 << 10)
50 #define CTRL_WORD_LENGTH_16 (0 << 8)
58 #define CTRL_RUN BIT(0)
62 #define CTRL1_SET_BYTE_PACKAGING(x) (((x) & 0xf) << 16)
63 #define CTRL1_GET_BYTE_PACKAGING(x) (((x) >> 16) & 0xf)
67 #define CTRL2_SET_OUTSTANDING_REQS_1 0
68 #define CTRL2_SET_OUTSTANDING_REQS_2 (0x1 << 21)
69 #define CTRL2_SET_OUTSTANDING_REQS_4 (0x2 << 21)
70 #define CTRL2_SET_OUTSTANDING_REQS_8 (0x3 << 21)
71 #define CTRL2_SET_OUTSTANDING_REQS_16 (0x4 << 21)
72 #define CTRL2_SET_OUTSTANDING_REQS_MASK (0x7 << 21)
74 #define TRANSFER_COUNT_SET_VCOUNT(x) (((x) & 0xffff) << 16)
75 #define TRANSFER_COUNT_GET_VCOUNT(x) (((x) >> 16) & 0xffff)
76 #define TRANSFER_COUNT_SET_HCOUNT(x) ((x) & 0xffff)
77 #define TRANSFER_COUNT_GET_HCOUNT(x) ((x) & 0xffff)
88 #define VDCTRL0_SET_VSYNC_PULSE_WIDTH(x) ((x) & 0x3ffff)
89 #define VDCTRL0_GET_VSYNC_PULSE_WIDTH(x) ((x) & 0x3ffff)
91 #define VDCTRL2_SET_HSYNC_PERIOD(x) ((x) & 0x3ffff)
92 #define VDCTRL2_GET_HSYNC_PERIOD(x) ((x) & 0x3ffff)
96 #define SET_HOR_WAIT_CNT(x) (((x) & 0xfff) << 16)
97 #define GET_HOR_WAIT_CNT(x) (((x) >> 16) & 0xfff)
98 #define SET_VERT_WAIT_CNT(x) ((x) & 0xffff)
99 #define GET_VERT_WAIT_CNT(x) ((x) & 0xffff)
101 #define VDCTRL4_SET_DOTCLK_DLY(x) (((x) & 0x7) << 29) /* v4 only */
102 #define VDCTRL4_GET_DOTCLK_DLY(x) (((x) >> 29) & 0x7) /* v4 only */
104 #define SET_DOTCLK_H_VALID_DATA_CNT(x) ((x) & 0x3ffff)
111 #define AS_CTRL_ALPHA(a) (((a) & 0xff) << 8)
112 #define AS_CTRL_FORMAT_RGB565 (0xe << 4)
113 #define AS_CTRL_FORMAT_RGB444 (0xd << 4)
114 #define AS_CTRL_FORMAT_RGB555 (0xc << 4)
115 #define AS_CTRL_FORMAT_ARGB4444 (0x9 << 4)
116 #define AS_CTRL_FORMAT_ARGB1555 (0x8 << 4)
117 #define AS_CTRL_FORMAT_RGB888 (0x4 << 4)
118 #define AS_CTRL_FORMAT_ARGB8888 (0x0 << 4)
123 #define AS_CTRL_ALPHA_CTRL_EMBEDDED (0 << 1)
124 #define AS_CTRL_AS_ENABLE BIT(0)
128 #define CTRL_FETCH_START_OPTION_FPV 0
137 #define CTRL_INV_HS BIT(0)
141 #define DISP_PARA_LINE_PATTERN_UYVY_H (0xd << 26)
142 #define DISP_PARA_LINE_PATTERN_RGB565 (0x7 << 26)
143 #define DISP_PARA_LINE_PATTERN_RGB888 (0x0 << 26)
148 #define DISP_PARA_BGND_B_MASK GENMASK(7, 0)
150 #define DISP_SIZE_DELTA_Y(n) (((n) & 0xffff) << 16)
152 #define DISP_SIZE_DELTA_X(n) ((n) & 0xffff)
153 #define DISP_SIZE_DELTA_X_MASK GENMASK(15, 0)
155 #define HSYN_PARA_BP_H(n) (((n) & 0xffff) << 16)
157 #define HSYN_PARA_FP_H(n) ((n) & 0xffff)
158 #define HSYN_PARA_FP_H_MASK GENMASK(15, 0)
160 #define VSYN_PARA_BP_V(n) (((n) & 0xffff) << 16)
162 #define VSYN_PARA_FP_V(n) ((n) & 0xffff)
163 #define VSYN_PARA_FP_V_MASK GENMASK(15, 0)
165 #define VSYN_HSYN_WIDTH_PW_V(n) (((n) & 0xffff) << 16)
167 #define VSYN_HSYN_WIDTH_PW_H(n) ((n) & 0xffff)
168 #define VSYN_HSYN_WIDTH_PW_H_MASK GENMASK(15, 0)
175 #define INT_STATUS_D0_VSYNC BIT(0)
182 #define INT_ENABLE_D0_VSYNC_EN BIT(0)
184 #define INT_STATUS_D1_PLANE_PANIC BIT(0)
186 #define INT_ENABLE_D1_PLANE_PANIC_EN BIT(0)
188 #define CTRLDESCL0_1_HEIGHT(n) (((n) & 0xffff) << 16)
190 #define CTRLDESCL0_1_WIDTH(n) ((n) & 0xffff)
191 #define CTRLDESCL0_1_WIDTH_MASK GENMASK(15, 0)
197 #define CTRLDESCL0_3_PITCH(n) ((n) & 0xffff)
198 #define CTRLDESCL0_3_PITCH_MASK GENMASK(15, 0)
200 #define CTRLDESCL_HIGH0_4_ADDR_HIGH(n) ((n) & 0xf)
201 #define CTRLDESCL_HIGH0_4_ADDR_HIGH_MASK GENMASK(3, 0)
205 #define CTRLDESCL0_5_BPP_16_RGB565 (0x4 << 24)
206 #define CTRLDESCL0_5_BPP_16_ARGB1555 (0x5 << 24)
207 #define CTRLDESCL0_5_BPP_16_ARGB4444 (0x6 << 24)
208 #define CTRLDESCL0_5_BPP_YCbCr422 (0x7 << 24)
209 #define CTRLDESCL0_5_BPP_24_RGB888 (0x8 << 24)
210 #define CTRLDESCL0_5_BPP_32_ARGB8888 (0x9 << 24)
211 #define CTRLDESCL0_5_BPP_32_ABGR8888 (0xa << 24)
213 #define CTRLDESCL0_5_YUV_FORMAT_Y2VY1U (0x0 << 14)
214 #define CTRLDESCL0_5_YUV_FORMAT_Y2UY1V (0x1 << 14)
215 #define CTRLDESCL0_5_YUV_FORMAT_VY2UY1 (0x2 << 14)
216 #define CTRLDESCL0_5_YUV_FORMAT_UY2VY1 (0x3 << 14)
219 #define CSC0_CTRL_CSC_MODE_YUV2RGB (0x0 << 1)
220 #define CSC0_CTRL_CSC_MODE_YCbCr2RGB (0x1 << 1)
221 #define CSC0_CTRL_CSC_MODE_RGB2YUV (0x2 << 1)
222 #define CSC0_CTRL_CSC_MODE_RGB2YCbCr (0x3 << 1)
224 #define CSC0_CTRL_BYPASS BIT(0)
229 #define CSC0_COEF0_A1_MASK GENMASK(10, 0)
234 #define CSC0_COEF1_A3_MASK GENMASK(10, 0)
239 #define CSC0_COEF2_B2_MASK GENMASK(10, 0)
244 #define CSC0_COEF3_C1_MASK GENMASK(10, 0)
249 #define CSC0_COEF4_C3_MASK GENMASK(10, 0)
254 #define CSC0_COEF5_D2_MASK GENMASK(8, 0)
257 #define PANIC0_THRES_HIGH_MASK GENMASK(8, 0)
262 #define LCDIF_MAX_XRES 0xffff
263 #define LCDIF_MAX_YRES 0xffff