14135d8b6SKai Chieh Chuang /* SPDX-License-Identifier: GPL-2.0 */ 2c5e7fca9SKai Chieh Chuang /* 3c5e7fca9SKai Chieh Chuang * mt6797-reg.h -- Mediatek 6797 audio driver reg definition 4c5e7fca9SKai Chieh Chuang * 5c5e7fca9SKai Chieh Chuang * Copyright (c) 2018 MediaTek Inc. 64135d8b6SKai Chieh Chuang * Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com> 7c5e7fca9SKai Chieh Chuang */ 8c5e7fca9SKai Chieh Chuang 9c5e7fca9SKai Chieh Chuang #ifndef _MT6797_REG_H_ 10c5e7fca9SKai Chieh Chuang #define _MT6797_REG_H_ 11c5e7fca9SKai Chieh Chuang 12c5e7fca9SKai Chieh Chuang #define AUDIO_TOP_CON0 0x0000 13c5e7fca9SKai Chieh Chuang #define AUDIO_TOP_CON1 0x0004 14c5e7fca9SKai Chieh Chuang #define AUDIO_TOP_CON3 0x000c 15c5e7fca9SKai Chieh Chuang #define AFE_DAC_CON0 0x0010 16c5e7fca9SKai Chieh Chuang #define AFE_DAC_CON1 0x0014 17c5e7fca9SKai Chieh Chuang #define AFE_I2S_CON 0x0018 18c5e7fca9SKai Chieh Chuang #define AFE_DAIBT_CON0 0x001c 19c5e7fca9SKai Chieh Chuang #define AFE_CONN0 0x0020 20c5e7fca9SKai Chieh Chuang #define AFE_CONN1 0x0024 21c5e7fca9SKai Chieh Chuang #define AFE_CONN2 0x0028 22c5e7fca9SKai Chieh Chuang #define AFE_CONN3 0x002c 23c5e7fca9SKai Chieh Chuang #define AFE_CONN4 0x0030 24c5e7fca9SKai Chieh Chuang #define AFE_I2S_CON1 0x0034 25c5e7fca9SKai Chieh Chuang #define AFE_I2S_CON2 0x0038 26c5e7fca9SKai Chieh Chuang #define AFE_MRGIF_CON 0x003c 27c5e7fca9SKai Chieh Chuang #define AFE_DL1_BASE 0x0040 28c5e7fca9SKai Chieh Chuang #define AFE_DL1_CUR 0x0044 29c5e7fca9SKai Chieh Chuang #define AFE_DL1_END 0x0048 30c5e7fca9SKai Chieh Chuang #define AFE_I2S_CON3 0x004c 31c5e7fca9SKai Chieh Chuang #define AFE_DL2_BASE 0x0050 32c5e7fca9SKai Chieh Chuang #define AFE_DL2_CUR 0x0054 33c5e7fca9SKai Chieh Chuang #define AFE_DL2_END 0x0058 34c5e7fca9SKai Chieh Chuang #define AFE_CONN5 0x005c 35c5e7fca9SKai Chieh Chuang #define AFE_CONN_24BIT 0x006c 36c5e7fca9SKai Chieh Chuang #define AFE_AWB_BASE 0x0070 37c5e7fca9SKai Chieh Chuang #define AFE_AWB_END 0x0078 38c5e7fca9SKai Chieh Chuang #define AFE_AWB_CUR 0x007c 39c5e7fca9SKai Chieh Chuang #define AFE_VUL_BASE 0x0080 40c5e7fca9SKai Chieh Chuang #define AFE_VUL_END 0x0088 41c5e7fca9SKai Chieh Chuang #define AFE_VUL_CUR 0x008c 42c5e7fca9SKai Chieh Chuang #define AFE_DAI_BASE 0x0090 43c5e7fca9SKai Chieh Chuang #define AFE_DAI_END 0x0098 44c5e7fca9SKai Chieh Chuang #define AFE_DAI_CUR 0x009c 45c5e7fca9SKai Chieh Chuang #define AFE_CONN6 0x00bc 46c5e7fca9SKai Chieh Chuang #define AFE_MEMIF_MSB 0x00cc 47c5e7fca9SKai Chieh Chuang #define AFE_MEMIF_MON0 0x00d0 48c5e7fca9SKai Chieh Chuang #define AFE_MEMIF_MON1 0x00d4 49c5e7fca9SKai Chieh Chuang #define AFE_MEMIF_MON2 0x00d8 50c5e7fca9SKai Chieh Chuang #define AFE_MEMIF_MON4 0x00e0 51c5e7fca9SKai Chieh Chuang #define AFE_ADDA_DL_SRC2_CON0 0x0108 52c5e7fca9SKai Chieh Chuang #define AFE_ADDA_DL_SRC2_CON1 0x010c 53c5e7fca9SKai Chieh Chuang #define AFE_ADDA_UL_SRC_CON0 0x0114 54c5e7fca9SKai Chieh Chuang #define AFE_ADDA_UL_SRC_CON1 0x0118 55c5e7fca9SKai Chieh Chuang #define AFE_ADDA_TOP_CON0 0x0120 56c5e7fca9SKai Chieh Chuang #define AFE_ADDA_UL_DL_CON0 0x0124 57c5e7fca9SKai Chieh Chuang #define AFE_ADDA_SRC_DEBUG 0x012c 58c5e7fca9SKai Chieh Chuang #define AFE_ADDA_SRC_DEBUG_MON0 0x0130 59c5e7fca9SKai Chieh Chuang #define AFE_ADDA_SRC_DEBUG_MON1 0x0134 60c5e7fca9SKai Chieh Chuang #define AFE_ADDA_NEWIF_CFG0 0x0138 61c5e7fca9SKai Chieh Chuang #define AFE_ADDA_NEWIF_CFG1 0x013c 62c5e7fca9SKai Chieh Chuang #define AFE_ADDA_NEWIF_CFG2 0x0140 63c5e7fca9SKai Chieh Chuang #define AFE_DMA_CTL 0x0150 64c5e7fca9SKai Chieh Chuang #define AFE_DMA_MON0 0x0154 65c5e7fca9SKai Chieh Chuang #define AFE_DMA_MON1 0x0158 66c5e7fca9SKai Chieh Chuang #define AFE_SIDETONE_DEBUG 0x01d0 67c5e7fca9SKai Chieh Chuang #define AFE_SIDETONE_MON 0x01d4 68c5e7fca9SKai Chieh Chuang #define AFE_SIDETONE_CON0 0x01e0 69c5e7fca9SKai Chieh Chuang #define AFE_SIDETONE_COEFF 0x01e4 70c5e7fca9SKai Chieh Chuang #define AFE_SIDETONE_CON1 0x01e8 71c5e7fca9SKai Chieh Chuang #define AFE_SIDETONE_GAIN 0x01ec 72c5e7fca9SKai Chieh Chuang #define AFE_SGEN_CON0 0x01f0 73c5e7fca9SKai Chieh Chuang #define AFE_SINEGEN_CON_TDM 0x01fc 74c5e7fca9SKai Chieh Chuang #define AFE_TOP_CON0 0x0200 75c5e7fca9SKai Chieh Chuang #define AFE_ADDA_PREDIS_CON0 0x0260 76c5e7fca9SKai Chieh Chuang #define AFE_ADDA_PREDIS_CON1 0x0264 77c5e7fca9SKai Chieh Chuang #define AFE_MRGIF_MON0 0x0270 78c5e7fca9SKai Chieh Chuang #define AFE_MRGIF_MON1 0x0274 79c5e7fca9SKai Chieh Chuang #define AFE_MRGIF_MON2 0x0278 80c5e7fca9SKai Chieh Chuang #define AFE_I2S_MON 0x027c 81c5e7fca9SKai Chieh Chuang #define AFE_MOD_DAI_BASE 0x0330 82c5e7fca9SKai Chieh Chuang #define AFE_MOD_DAI_END 0x0338 83c5e7fca9SKai Chieh Chuang #define AFE_MOD_DAI_CUR 0x033c 84c5e7fca9SKai Chieh Chuang #define AFE_VUL_D2_BASE 0x0350 85c5e7fca9SKai Chieh Chuang #define AFE_VUL_D2_END 0x0358 86c5e7fca9SKai Chieh Chuang #define AFE_VUL_D2_CUR 0x035c 87c5e7fca9SKai Chieh Chuang #define AFE_DL3_BASE 0x0360 88c5e7fca9SKai Chieh Chuang #define AFE_DL3_CUR 0x0364 89c5e7fca9SKai Chieh Chuang #define AFE_DL3_END 0x0368 90c5e7fca9SKai Chieh Chuang #define AFE_HDMI_OUT_CON0 0x0370 91c5e7fca9SKai Chieh Chuang #define AFE_HDMI_BASE 0x0374 92c5e7fca9SKai Chieh Chuang #define AFE_HDMI_CUR 0x0378 93c5e7fca9SKai Chieh Chuang #define AFE_HDMI_END 0x037c 94c5e7fca9SKai Chieh Chuang #define AFE_HDMI_CONN0 0x0390 95c5e7fca9SKai Chieh Chuang #define AFE_IRQ3_MCU_CNT_MON 0x0398 96c5e7fca9SKai Chieh Chuang #define AFE_IRQ4_MCU_CNT_MON 0x039c 97c5e7fca9SKai Chieh Chuang #define AFE_IRQ_MCU_CON 0x03a0 98c5e7fca9SKai Chieh Chuang #define AFE_IRQ_MCU_STATUS 0x03a4 99c5e7fca9SKai Chieh Chuang #define AFE_IRQ_MCU_CLR 0x03a8 100c5e7fca9SKai Chieh Chuang #define AFE_IRQ_MCU_CNT1 0x03ac 101c5e7fca9SKai Chieh Chuang #define AFE_IRQ_MCU_CNT2 0x03b0 102c5e7fca9SKai Chieh Chuang #define AFE_IRQ_MCU_EN 0x03b4 103c5e7fca9SKai Chieh Chuang #define AFE_IRQ_MCU_MON2 0x03b8 104c5e7fca9SKai Chieh Chuang #define AFE_IRQ_MCU_CNT5 0x03bc 105c5e7fca9SKai Chieh Chuang #define AFE_IRQ1_MCU_CNT_MON 0x03c0 106c5e7fca9SKai Chieh Chuang #define AFE_IRQ2_MCU_CNT_MON 0x03c4 107c5e7fca9SKai Chieh Chuang #define AFE_IRQ1_MCU_EN_CNT_MON 0x03c8 108c5e7fca9SKai Chieh Chuang #define AFE_IRQ5_MCU_CNT_MON 0x03cc 109c5e7fca9SKai Chieh Chuang #define AFE_MEMIF_MINLEN 0x03d0 110c5e7fca9SKai Chieh Chuang #define AFE_MEMIF_MAXLEN 0x03d4 111c5e7fca9SKai Chieh Chuang #define AFE_MEMIF_PBUF_SIZE 0x03d8 112c5e7fca9SKai Chieh Chuang #define AFE_IRQ_MCU_CNT7 0x03dc 113c5e7fca9SKai Chieh Chuang #define AFE_IRQ7_MCU_CNT_MON 0x03e0 114c5e7fca9SKai Chieh Chuang #define AFE_IRQ_MCU_CNT3 0x03e4 115c5e7fca9SKai Chieh Chuang #define AFE_IRQ_MCU_CNT4 0x03e8 116c5e7fca9SKai Chieh Chuang #define AFE_APLL1_TUNER_CFG 0x03f0 117c5e7fca9SKai Chieh Chuang #define AFE_APLL2_TUNER_CFG 0x03f4 118c5e7fca9SKai Chieh Chuang #define AFE_MEMIF_HD_MODE 0x03f8 119c5e7fca9SKai Chieh Chuang #define AFE_MEMIF_HDALIGN 0x03fc 120c5e7fca9SKai Chieh Chuang #define AFE_GAIN1_CON0 0x0410 121c5e7fca9SKai Chieh Chuang #define AFE_GAIN1_CON1 0x0414 122c5e7fca9SKai Chieh Chuang #define AFE_GAIN1_CON2 0x0418 123c5e7fca9SKai Chieh Chuang #define AFE_GAIN1_CON3 0x041c 124c5e7fca9SKai Chieh Chuang #define AFE_CONN7 0x0420 125c5e7fca9SKai Chieh Chuang #define AFE_GAIN1_CUR 0x0424 126c5e7fca9SKai Chieh Chuang #define AFE_GAIN2_CON0 0x0428 127c5e7fca9SKai Chieh Chuang #define AFE_GAIN2_CON1 0x042c 128c5e7fca9SKai Chieh Chuang #define AFE_GAIN2_CON2 0x0430 129c5e7fca9SKai Chieh Chuang #define AFE_GAIN2_CON3 0x0434 130c5e7fca9SKai Chieh Chuang #define AFE_CONN8 0x0438 131c5e7fca9SKai Chieh Chuang #define AFE_GAIN2_CUR 0x043c 132c5e7fca9SKai Chieh Chuang #define AFE_CONN9 0x0440 133c5e7fca9SKai Chieh Chuang #define AFE_CONN10 0x0444 134c5e7fca9SKai Chieh Chuang #define AFE_CONN11 0x0448 135c5e7fca9SKai Chieh Chuang #define AFE_CONN12 0x044c 136c5e7fca9SKai Chieh Chuang #define AFE_CONN13 0x0450 137c5e7fca9SKai Chieh Chuang #define AFE_CONN14 0x0454 138c5e7fca9SKai Chieh Chuang #define AFE_CONN15 0x0458 139c5e7fca9SKai Chieh Chuang #define AFE_CONN16 0x045c 140c5e7fca9SKai Chieh Chuang #define AFE_CONN17 0x0460 141c5e7fca9SKai Chieh Chuang #define AFE_CONN18 0x0464 142c5e7fca9SKai Chieh Chuang #define AFE_CONN19 0x0468 143c5e7fca9SKai Chieh Chuang #define AFE_CONN20 0x046c 144c5e7fca9SKai Chieh Chuang #define AFE_CONN21 0x0470 145c5e7fca9SKai Chieh Chuang #define AFE_CONN22 0x0474 146c5e7fca9SKai Chieh Chuang #define AFE_CONN23 0x0478 147c5e7fca9SKai Chieh Chuang #define AFE_CONN24 0x047c 148c5e7fca9SKai Chieh Chuang #define AFE_CONN_RS 0x0494 149c5e7fca9SKai Chieh Chuang #define AFE_CONN_DI 0x0498 150c5e7fca9SKai Chieh Chuang #define AFE_CONN25 0x04b0 151c5e7fca9SKai Chieh Chuang #define AFE_CONN26 0x04b4 152c5e7fca9SKai Chieh Chuang #define AFE_CONN27 0x04b8 153c5e7fca9SKai Chieh Chuang #define AFE_CONN28 0x04bc 154c5e7fca9SKai Chieh Chuang #define AFE_CONN29 0x04c0 155c5e7fca9SKai Chieh Chuang #define AFE_SRAM_DELSEL_CON0 0x04f0 156c5e7fca9SKai Chieh Chuang #define AFE_SRAM_DELSEL_CON1 0x04f4 157c5e7fca9SKai Chieh Chuang #define AFE_ASRC_CON0 0x0500 158c5e7fca9SKai Chieh Chuang #define AFE_ASRC_CON1 0x0504 159c5e7fca9SKai Chieh Chuang #define AFE_ASRC_CON2 0x0508 160c5e7fca9SKai Chieh Chuang #define AFE_ASRC_CON3 0x050c 161c5e7fca9SKai Chieh Chuang #define AFE_ASRC_CON4 0x0510 162c5e7fca9SKai Chieh Chuang #define AFE_ASRC_CON5 0x0514 163c5e7fca9SKai Chieh Chuang #define AFE_ASRC_CON6 0x0518 164c5e7fca9SKai Chieh Chuang #define AFE_ASRC_CON7 0x051c 165c5e7fca9SKai Chieh Chuang #define AFE_ASRC_CON8 0x0520 166c5e7fca9SKai Chieh Chuang #define AFE_ASRC_CON9 0x0524 167c5e7fca9SKai Chieh Chuang #define AFE_ASRC_CON10 0x0528 168c5e7fca9SKai Chieh Chuang #define AFE_ASRC_CON11 0x052c 169c5e7fca9SKai Chieh Chuang #define PCM_INTF_CON1 0x0530 170c5e7fca9SKai Chieh Chuang #define PCM_INTF_CON2 0x0538 171c5e7fca9SKai Chieh Chuang #define PCM2_INTF_CON 0x053c 172c5e7fca9SKai Chieh Chuang #define AFE_TDM_CON1 0x0548 173c5e7fca9SKai Chieh Chuang #define AFE_TDM_CON2 0x054c 174c5e7fca9SKai Chieh Chuang #define AFE_ASRC_CON13 0x0550 175c5e7fca9SKai Chieh Chuang #define AFE_ASRC_CON14 0x0554 176c5e7fca9SKai Chieh Chuang #define AFE_ASRC_CON15 0x0558 177c5e7fca9SKai Chieh Chuang #define AFE_ASRC_CON16 0x055c 178c5e7fca9SKai Chieh Chuang #define AFE_ASRC_CON17 0x0560 179c5e7fca9SKai Chieh Chuang #define AFE_ASRC_CON18 0x0564 180c5e7fca9SKai Chieh Chuang #define AFE_ASRC_CON19 0x0568 181c5e7fca9SKai Chieh Chuang #define AFE_ASRC_CON20 0x056c 182c5e7fca9SKai Chieh Chuang #define AFE_ASRC_CON21 0x0570 183c5e7fca9SKai Chieh Chuang #define CLK_AUDDIV_0 0x05a0 184c5e7fca9SKai Chieh Chuang #define CLK_AUDDIV_1 0x05a4 185c5e7fca9SKai Chieh Chuang #define CLK_AUDDIV_2 0x05a8 186c5e7fca9SKai Chieh Chuang #define CLK_AUDDIV_3 0x05ac 187c5e7fca9SKai Chieh Chuang #define AUDIO_TOP_DBG_CON 0x05c8 188c5e7fca9SKai Chieh Chuang #define AUDIO_TOP_DBG_MON0 0x05cc 189c5e7fca9SKai Chieh Chuang #define AUDIO_TOP_DBG_MON1 0x05d0 190c5e7fca9SKai Chieh Chuang #define AUDIO_TOP_DBG_MON2 0x05d4 191c5e7fca9SKai Chieh Chuang #define AFE_ADDA2_TOP_CON0 0x0600 192c5e7fca9SKai Chieh Chuang #define AFE_ASRC4_CON0 0x06c0 193c5e7fca9SKai Chieh Chuang #define AFE_ASRC4_CON1 0x06c4 194c5e7fca9SKai Chieh Chuang #define AFE_ASRC4_CON2 0x06c8 195c5e7fca9SKai Chieh Chuang #define AFE_ASRC4_CON3 0x06cc 196c5e7fca9SKai Chieh Chuang #define AFE_ASRC4_CON4 0x06d0 197c5e7fca9SKai Chieh Chuang #define AFE_ASRC4_CON5 0x06d4 198c5e7fca9SKai Chieh Chuang #define AFE_ASRC4_CON6 0x06d8 199c5e7fca9SKai Chieh Chuang #define AFE_ASRC4_CON7 0x06dc 200c5e7fca9SKai Chieh Chuang #define AFE_ASRC4_CON8 0x06e0 201c5e7fca9SKai Chieh Chuang #define AFE_ASRC4_CON9 0x06e4 202c5e7fca9SKai Chieh Chuang #define AFE_ASRC4_CON10 0x06e8 203c5e7fca9SKai Chieh Chuang #define AFE_ASRC4_CON11 0x06ec 204c5e7fca9SKai Chieh Chuang #define AFE_ASRC4_CON12 0x06f0 205c5e7fca9SKai Chieh Chuang #define AFE_ASRC4_CON13 0x06f4 206c5e7fca9SKai Chieh Chuang #define AFE_ASRC4_CON14 0x06f8 207c5e7fca9SKai Chieh Chuang #define AFE_ASRC2_CON0 0x0700 208c5e7fca9SKai Chieh Chuang #define AFE_ASRC2_CON1 0x0704 209c5e7fca9SKai Chieh Chuang #define AFE_ASRC2_CON2 0x0708 210c5e7fca9SKai Chieh Chuang #define AFE_ASRC2_CON3 0x070c 211c5e7fca9SKai Chieh Chuang #define AFE_ASRC2_CON4 0x0710 212c5e7fca9SKai Chieh Chuang #define AFE_ASRC2_CON5 0x0714 213c5e7fca9SKai Chieh Chuang #define AFE_ASRC2_CON6 0x0718 214c5e7fca9SKai Chieh Chuang #define AFE_ASRC2_CON7 0x071c 215c5e7fca9SKai Chieh Chuang #define AFE_ASRC2_CON8 0x0720 216c5e7fca9SKai Chieh Chuang #define AFE_ASRC2_CON9 0x0724 217c5e7fca9SKai Chieh Chuang #define AFE_ASRC2_CON10 0x0728 218c5e7fca9SKai Chieh Chuang #define AFE_ASRC2_CON11 0x072c 219c5e7fca9SKai Chieh Chuang #define AFE_ASRC2_CON12 0x0730 220c5e7fca9SKai Chieh Chuang #define AFE_ASRC2_CON13 0x0734 221c5e7fca9SKai Chieh Chuang #define AFE_ASRC2_CON14 0x0738 222c5e7fca9SKai Chieh Chuang #define AFE_ASRC3_CON0 0x0740 223c5e7fca9SKai Chieh Chuang #define AFE_ASRC3_CON1 0x0744 224c5e7fca9SKai Chieh Chuang #define AFE_ASRC3_CON2 0x0748 225c5e7fca9SKai Chieh Chuang #define AFE_ASRC3_CON3 0x074c 226c5e7fca9SKai Chieh Chuang #define AFE_ASRC3_CON4 0x0750 227c5e7fca9SKai Chieh Chuang #define AFE_ASRC3_CON5 0x0754 228c5e7fca9SKai Chieh Chuang #define AFE_ASRC3_CON6 0x0758 229c5e7fca9SKai Chieh Chuang #define AFE_ASRC3_CON7 0x075c 230c5e7fca9SKai Chieh Chuang #define AFE_ASRC3_CON8 0x0760 231c5e7fca9SKai Chieh Chuang #define AFE_ASRC3_CON9 0x0764 232c5e7fca9SKai Chieh Chuang #define AFE_ASRC3_CON10 0x0768 233c5e7fca9SKai Chieh Chuang #define AFE_ASRC3_CON11 0x076c 234c5e7fca9SKai Chieh Chuang #define AFE_ASRC3_CON12 0x0770 235c5e7fca9SKai Chieh Chuang #define AFE_ASRC3_CON13 0x0774 236c5e7fca9SKai Chieh Chuang #define AFE_ASRC3_CON14 0x0778 237c5e7fca9SKai Chieh Chuang #define AFE_GENERAL_REG0 0x0800 238c5e7fca9SKai Chieh Chuang #define AFE_GENERAL_REG1 0x0804 239c5e7fca9SKai Chieh Chuang #define AFE_GENERAL_REG2 0x0808 240c5e7fca9SKai Chieh Chuang #define AFE_GENERAL_REG3 0x080c 241c5e7fca9SKai Chieh Chuang #define AFE_GENERAL_REG4 0x0810 242c5e7fca9SKai Chieh Chuang #define AFE_GENERAL_REG5 0x0814 243c5e7fca9SKai Chieh Chuang #define AFE_GENERAL_REG6 0x0818 244c5e7fca9SKai Chieh Chuang #define AFE_GENERAL_REG7 0x081c 245c5e7fca9SKai Chieh Chuang #define AFE_GENERAL_REG8 0x0820 246c5e7fca9SKai Chieh Chuang #define AFE_GENERAL_REG9 0x0824 247c5e7fca9SKai Chieh Chuang #define AFE_GENERAL_REG10 0x0828 248c5e7fca9SKai Chieh Chuang #define AFE_GENERAL_REG11 0x082c 249c5e7fca9SKai Chieh Chuang #define AFE_GENERAL_REG12 0x0830 250c5e7fca9SKai Chieh Chuang #define AFE_GENERAL_REG13 0x0834 251c5e7fca9SKai Chieh Chuang #define AFE_GENERAL_REG14 0x0838 252c5e7fca9SKai Chieh Chuang #define AFE_GENERAL_REG15 0x083c 253c5e7fca9SKai Chieh Chuang #define AFE_CBIP_CFG0 0x0840 254c5e7fca9SKai Chieh Chuang #define AFE_CBIP_MON0 0x0844 255c5e7fca9SKai Chieh Chuang #define AFE_CBIP_SLV_MUX_MON0 0x0848 256c5e7fca9SKai Chieh Chuang #define AFE_CBIP_SLV_DECODER_MON0 0x084c 257c5e7fca9SKai Chieh Chuang 258c5e7fca9SKai Chieh Chuang #define AFE_MAX_REGISTER AFE_CBIP_SLV_DECODER_MON0 259c5e7fca9SKai Chieh Chuang #define AFE_IRQ_STATUS_BITS 0x5f 260c5e7fca9SKai Chieh Chuang 261c5e7fca9SKai Chieh Chuang /* AUDIO_TOP_CON0 */ 262c5e7fca9SKai Chieh Chuang #define AHB_IDLE_EN_INT_SFT 30 263c5e7fca9SKai Chieh Chuang #define AHB_IDLE_EN_INT_MASK 0x1 264c5e7fca9SKai Chieh Chuang #define AHB_IDLE_EN_INT_MASK_SFT (0x1 << 30) 265c5e7fca9SKai Chieh Chuang #define AHB_IDLE_EN_EXT_SFT 29 266c5e7fca9SKai Chieh Chuang #define AHB_IDLE_EN_EXT_MASK 0x1 267c5e7fca9SKai Chieh Chuang #define AHB_IDLE_EN_EXT_MASK_SFT (0x1 << 29) 268c5e7fca9SKai Chieh Chuang #define PDN_TML_SFT 27 269c5e7fca9SKai Chieh Chuang #define PDN_TML_MASK 0x1 270c5e7fca9SKai Chieh Chuang #define PDN_TML_MASK_SFT (0x1 << 27) 271c5e7fca9SKai Chieh Chuang #define PDN_DAC_PREDIS_SFT 26 272c5e7fca9SKai Chieh Chuang #define PDN_DAC_PREDIS_MASK 0x1 273c5e7fca9SKai Chieh Chuang #define PDN_DAC_PREDIS_MASK_SFT (0x1 << 26) 274c5e7fca9SKai Chieh Chuang #define PDN_DAC_SFT 25 275c5e7fca9SKai Chieh Chuang #define PDN_DAC_MASK 0x1 276c5e7fca9SKai Chieh Chuang #define PDN_DAC_MASK_SFT (0x1 << 25) 277c5e7fca9SKai Chieh Chuang #define PDN_ADC_SFT 24 278c5e7fca9SKai Chieh Chuang #define PDN_ADC_MASK 0x1 279c5e7fca9SKai Chieh Chuang #define PDN_ADC_MASK_SFT (0x1 << 24) 280c5e7fca9SKai Chieh Chuang #define PDN_TDM_CK_SFT 20 281c5e7fca9SKai Chieh Chuang #define PDN_TDM_CK_MASK 0x1 282c5e7fca9SKai Chieh Chuang #define PDN_TDM_CK_MASK_SFT (0x1 << 20) 283c5e7fca9SKai Chieh Chuang #define PDN_APLL_TUNER_SFT 19 284c5e7fca9SKai Chieh Chuang #define PDN_APLL_TUNER_MASK 0x1 285c5e7fca9SKai Chieh Chuang #define PDN_APLL_TUNER_MASK_SFT (0x1 << 19) 286c5e7fca9SKai Chieh Chuang #define PDN_APLL2_TUNER_SFT 18 287c5e7fca9SKai Chieh Chuang #define PDN_APLL2_TUNER_MASK 0x1 288c5e7fca9SKai Chieh Chuang #define PDN_APLL2_TUNER_MASK_SFT (0x1 << 18) 289c5e7fca9SKai Chieh Chuang #define APB3_SEL_SFT 14 290c5e7fca9SKai Chieh Chuang #define APB3_SEL_MASK 0x1 291c5e7fca9SKai Chieh Chuang #define APB3_SEL_MASK_SFT (0x1 << 14) 292c5e7fca9SKai Chieh Chuang #define APB_R2T_SFT 13 293c5e7fca9SKai Chieh Chuang #define APB_R2T_MASK 0x1 294c5e7fca9SKai Chieh Chuang #define APB_R2T_MASK_SFT (0x1 << 13) 295c5e7fca9SKai Chieh Chuang #define APB_W2T_SFT 12 296c5e7fca9SKai Chieh Chuang #define APB_W2T_MASK 0x1 297c5e7fca9SKai Chieh Chuang #define APB_W2T_MASK_SFT (0x1 << 12) 298c5e7fca9SKai Chieh Chuang #define PDN_24M_SFT 9 299c5e7fca9SKai Chieh Chuang #define PDN_24M_MASK 0x1 300c5e7fca9SKai Chieh Chuang #define PDN_24M_MASK_SFT (0x1 << 9) 301c5e7fca9SKai Chieh Chuang #define PDN_22M_SFT 8 302c5e7fca9SKai Chieh Chuang #define PDN_22M_MASK 0x1 303c5e7fca9SKai Chieh Chuang #define PDN_22M_MASK_SFT (0x1 << 8) 304c5e7fca9SKai Chieh Chuang #define PDN_ADDA4_ADC_SFT 7 305c5e7fca9SKai Chieh Chuang #define PDN_ADDA4_ADC_MASK 0x1 306c5e7fca9SKai Chieh Chuang #define PDN_ADDA4_ADC_MASK_SFT (0x1 << 7) 307c5e7fca9SKai Chieh Chuang #define PDN_I2S_SFT 6 308c5e7fca9SKai Chieh Chuang #define PDN_I2S_MASK 0x1 309c5e7fca9SKai Chieh Chuang #define PDN_I2S_MASK_SFT (0x1 << 6) 310c5e7fca9SKai Chieh Chuang #define PDN_AFE_SFT 2 311c5e7fca9SKai Chieh Chuang #define PDN_AFE_MASK 0x1 312c5e7fca9SKai Chieh Chuang #define PDN_AFE_MASK_SFT (0x1 << 2) 313c5e7fca9SKai Chieh Chuang 314c5e7fca9SKai Chieh Chuang /* AUDIO_TOP_CON1 */ 315c5e7fca9SKai Chieh Chuang #define PDN_ADC_HIRES_TML_SFT 17 316c5e7fca9SKai Chieh Chuang #define PDN_ADC_HIRES_TML_MASK 0x1 317c5e7fca9SKai Chieh Chuang #define PDN_ADC_HIRES_TML_MASK_SFT (0x1 << 17) 318c5e7fca9SKai Chieh Chuang #define PDN_ADC_HIRES_SFT 16 319c5e7fca9SKai Chieh Chuang #define PDN_ADC_HIRES_MASK 0x1 320c5e7fca9SKai Chieh Chuang #define PDN_ADC_HIRES_MASK_SFT (0x1 << 16) 321c5e7fca9SKai Chieh Chuang #define I2S4_BCLK_SW_CG_SFT 7 322c5e7fca9SKai Chieh Chuang #define I2S4_BCLK_SW_CG_MASK 0x1 323c5e7fca9SKai Chieh Chuang #define I2S4_BCLK_SW_CG_MASK_SFT (0x1 << 7) 324c5e7fca9SKai Chieh Chuang #define I2S3_BCLK_SW_CG_SFT 6 325c5e7fca9SKai Chieh Chuang #define I2S3_BCLK_SW_CG_MASK 0x1 326c5e7fca9SKai Chieh Chuang #define I2S3_BCLK_SW_CG_MASK_SFT (0x1 << 6) 327c5e7fca9SKai Chieh Chuang #define I2S2_BCLK_SW_CG_SFT 5 328c5e7fca9SKai Chieh Chuang #define I2S2_BCLK_SW_CG_MASK 0x1 329c5e7fca9SKai Chieh Chuang #define I2S2_BCLK_SW_CG_MASK_SFT (0x1 << 5) 330c5e7fca9SKai Chieh Chuang #define I2S1_BCLK_SW_CG_SFT 4 331c5e7fca9SKai Chieh Chuang #define I2S1_BCLK_SW_CG_MASK 0x1 332c5e7fca9SKai Chieh Chuang #define I2S1_BCLK_SW_CG_MASK_SFT (0x1 << 4) 333c5e7fca9SKai Chieh Chuang #define I2S_SOFT_RST2_SFT 2 334c5e7fca9SKai Chieh Chuang #define I2S_SOFT_RST2_MASK 0x1 335c5e7fca9SKai Chieh Chuang #define I2S_SOFT_RST2_MASK_SFT (0x1 << 2) 336c5e7fca9SKai Chieh Chuang #define I2S_SOFT_RST_SFT 1 337c5e7fca9SKai Chieh Chuang #define I2S_SOFT_RST_MASK 0x1 338c5e7fca9SKai Chieh Chuang #define I2S_SOFT_RST_MASK_SFT (0x1 << 1) 339c5e7fca9SKai Chieh Chuang 340c5e7fca9SKai Chieh Chuang /* AFE_DAC_CON0 */ 341c5e7fca9SKai Chieh Chuang #define AFE_AWB_RETM_SFT 31 342c5e7fca9SKai Chieh Chuang #define AFE_AWB_RETM_MASK 0x1 343c5e7fca9SKai Chieh Chuang #define AFE_AWB_RETM_MASK_SFT (0x1 << 31) 344c5e7fca9SKai Chieh Chuang #define AFE_DL1_DATA2_RETM_SFT 30 345c5e7fca9SKai Chieh Chuang #define AFE_DL1_DATA2_RETM_MASK 0x1 346c5e7fca9SKai Chieh Chuang #define AFE_DL1_DATA2_RETM_MASK_SFT (0x1 << 30) 347c5e7fca9SKai Chieh Chuang #define AFE_DL2_RETM_SFT 29 348c5e7fca9SKai Chieh Chuang #define AFE_DL2_RETM_MASK 0x1 349c5e7fca9SKai Chieh Chuang #define AFE_DL2_RETM_MASK_SFT (0x1 << 29) 350c5e7fca9SKai Chieh Chuang #define AFE_DL1_RETM_SFT 28 351c5e7fca9SKai Chieh Chuang #define AFE_DL1_RETM_MASK 0x1 352c5e7fca9SKai Chieh Chuang #define AFE_DL1_RETM_MASK_SFT (0x1 << 28) 353c5e7fca9SKai Chieh Chuang #define AFE_ON_RETM_SFT 27 354c5e7fca9SKai Chieh Chuang #define AFE_ON_RETM_MASK 0x1 355c5e7fca9SKai Chieh Chuang #define AFE_ON_RETM_MASK_SFT (0x1 << 27) 356c5e7fca9SKai Chieh Chuang #define MOD_DAI_DUP_WR_SFT 26 357c5e7fca9SKai Chieh Chuang #define MOD_DAI_DUP_WR_MASK 0x1 358c5e7fca9SKai Chieh Chuang #define MOD_DAI_DUP_WR_MASK_SFT (0x1 << 26) 359c5e7fca9SKai Chieh Chuang #define DAI_MODE_SFT 24 360c5e7fca9SKai Chieh Chuang #define DAI_MODE_MASK 0x3 361c5e7fca9SKai Chieh Chuang #define DAI_MODE_MASK_SFT (0x3 << 24) 362c5e7fca9SKai Chieh Chuang #define VUL_DATA2_MODE_SFT 20 363c5e7fca9SKai Chieh Chuang #define VUL_DATA2_MODE_MASK 0xf 364c5e7fca9SKai Chieh Chuang #define VUL_DATA2_MODE_MASK_SFT (0xf << 20) 365c5e7fca9SKai Chieh Chuang #define DL1_DATA2_MODE_SFT 16 366c5e7fca9SKai Chieh Chuang #define DL1_DATA2_MODE_MASK 0xf 367c5e7fca9SKai Chieh Chuang #define DL1_DATA2_MODE_MASK_SFT (0xf << 16) 368c5e7fca9SKai Chieh Chuang #define DL3_MODE_SFT 12 369c5e7fca9SKai Chieh Chuang #define DL3_MODE_MASK 0xf 370c5e7fca9SKai Chieh Chuang #define DL3_MODE_MASK_SFT (0xf << 12) 371c5e7fca9SKai Chieh Chuang #define VUL_DATA2_R_MONO_SFT 11 372c5e7fca9SKai Chieh Chuang #define VUL_DATA2_R_MONO_MASK 0x1 373c5e7fca9SKai Chieh Chuang #define VUL_DATA2_R_MONO_MASK_SFT (0x1 << 11) 374c5e7fca9SKai Chieh Chuang #define VUL_DATA2_DATA_SFT 10 375c5e7fca9SKai Chieh Chuang #define VUL_DATA2_DATA_MASK 0x1 376c5e7fca9SKai Chieh Chuang #define VUL_DATA2_DATA_MASK_SFT (0x1 << 10) 377c5e7fca9SKai Chieh Chuang #define VUL_DATA2_ON_SFT 9 378c5e7fca9SKai Chieh Chuang #define VUL_DATA2_ON_MASK 0x1 379c5e7fca9SKai Chieh Chuang #define VUL_DATA2_ON_MASK_SFT (0x1 << 9) 380c5e7fca9SKai Chieh Chuang #define DL1_DATA2_ON_SFT 8 381c5e7fca9SKai Chieh Chuang #define DL1_DATA2_ON_MASK 0x1 382c5e7fca9SKai Chieh Chuang #define DL1_DATA2_ON_MASK_SFT (0x1 << 8) 383c5e7fca9SKai Chieh Chuang #define MOD_DAI_ON_SFT 7 384c5e7fca9SKai Chieh Chuang #define MOD_DAI_ON_MASK 0x1 385c5e7fca9SKai Chieh Chuang #define MOD_DAI_ON_MASK_SFT (0x1 << 7) 386c5e7fca9SKai Chieh Chuang #define AWB_ON_SFT 6 387c5e7fca9SKai Chieh Chuang #define AWB_ON_MASK 0x1 388c5e7fca9SKai Chieh Chuang #define AWB_ON_MASK_SFT (0x1 << 6) 389c5e7fca9SKai Chieh Chuang #define DL3_ON_SFT 5 390c5e7fca9SKai Chieh Chuang #define DL3_ON_MASK 0x1 391c5e7fca9SKai Chieh Chuang #define DL3_ON_MASK_SFT (0x1 << 5) 392c5e7fca9SKai Chieh Chuang #define DAI_ON_SFT 4 393c5e7fca9SKai Chieh Chuang #define DAI_ON_MASK 0x1 394c5e7fca9SKai Chieh Chuang #define DAI_ON_MASK_SFT (0x1 << 4) 395c5e7fca9SKai Chieh Chuang #define VUL_ON_SFT 3 396c5e7fca9SKai Chieh Chuang #define VUL_ON_MASK 0x1 397c5e7fca9SKai Chieh Chuang #define VUL_ON_MASK_SFT (0x1 << 3) 398c5e7fca9SKai Chieh Chuang #define DL2_ON_SFT 2 399c5e7fca9SKai Chieh Chuang #define DL2_ON_MASK 0x1 400c5e7fca9SKai Chieh Chuang #define DL2_ON_MASK_SFT (0x1 << 2) 401c5e7fca9SKai Chieh Chuang #define DL1_ON_SFT 1 402c5e7fca9SKai Chieh Chuang #define DL1_ON_MASK 0x1 403c5e7fca9SKai Chieh Chuang #define DL1_ON_MASK_SFT (0x1 << 1) 404c5e7fca9SKai Chieh Chuang #define AFE_ON_SFT 0 405c5e7fca9SKai Chieh Chuang #define AFE_ON_MASK 0x1 406c5e7fca9SKai Chieh Chuang #define AFE_ON_MASK_SFT (0x1 << 0) 407c5e7fca9SKai Chieh Chuang 408c5e7fca9SKai Chieh Chuang /* AFE_DAC_CON1 */ 409c5e7fca9SKai Chieh Chuang #define MOD_DAI_MODE_SFT 30 410c5e7fca9SKai Chieh Chuang #define MOD_DAI_MODE_MASK 0x3 411c5e7fca9SKai Chieh Chuang #define MOD_DAI_MODE_MASK_SFT (0x3 << 30) 412c5e7fca9SKai Chieh Chuang #define DAI_DUP_WR_SFT 29 413c5e7fca9SKai Chieh Chuang #define DAI_DUP_WR_MASK 0x1 414c5e7fca9SKai Chieh Chuang #define DAI_DUP_WR_MASK_SFT (0x1 << 29) 415c5e7fca9SKai Chieh Chuang #define VUL_R_MONO_SFT 28 416c5e7fca9SKai Chieh Chuang #define VUL_R_MONO_MASK 0x1 417c5e7fca9SKai Chieh Chuang #define VUL_R_MONO_MASK_SFT (0x1 << 28) 418c5e7fca9SKai Chieh Chuang #define VUL_DATA_SFT 27 419c5e7fca9SKai Chieh Chuang #define VUL_DATA_MASK 0x1 420c5e7fca9SKai Chieh Chuang #define VUL_DATA_MASK_SFT (0x1 << 27) 421c5e7fca9SKai Chieh Chuang #define AXI_2X1_CG_DISABLE_SFT 26 422c5e7fca9SKai Chieh Chuang #define AXI_2X1_CG_DISABLE_MASK 0x1 423c5e7fca9SKai Chieh Chuang #define AXI_2X1_CG_DISABLE_MASK_SFT (0x1 << 26) 424c5e7fca9SKai Chieh Chuang #define AWB_R_MONO_SFT 25 425c5e7fca9SKai Chieh Chuang #define AWB_R_MONO_MASK 0x1 426c5e7fca9SKai Chieh Chuang #define AWB_R_MONO_MASK_SFT (0x1 << 25) 427c5e7fca9SKai Chieh Chuang #define AWB_DATA_SFT 24 428c5e7fca9SKai Chieh Chuang #define AWB_DATA_MASK 0x1 429c5e7fca9SKai Chieh Chuang #define AWB_DATA_MASK_SFT (0x1 << 24) 430c5e7fca9SKai Chieh Chuang #define DL3_DATA_SFT 23 431c5e7fca9SKai Chieh Chuang #define DL3_DATA_MASK 0x1 432c5e7fca9SKai Chieh Chuang #define DL3_DATA_MASK_SFT (0x1 << 23) 433c5e7fca9SKai Chieh Chuang #define DL2_DATA_SFT 22 434c5e7fca9SKai Chieh Chuang #define DL2_DATA_MASK 0x1 435c5e7fca9SKai Chieh Chuang #define DL2_DATA_MASK_SFT (0x1 << 22) 436c5e7fca9SKai Chieh Chuang #define DL1_DATA_SFT 21 437c5e7fca9SKai Chieh Chuang #define DL1_DATA_MASK 0x1 438c5e7fca9SKai Chieh Chuang #define DL1_DATA_MASK_SFT (0x1 << 21) 439c5e7fca9SKai Chieh Chuang #define DL1_DATA2_DATA_SFT 20 440c5e7fca9SKai Chieh Chuang #define DL1_DATA2_DATA_MASK 0x1 441c5e7fca9SKai Chieh Chuang #define DL1_DATA2_DATA_MASK_SFT (0x1 << 20) 442c5e7fca9SKai Chieh Chuang #define VUL_MODE_SFT 16 443c5e7fca9SKai Chieh Chuang #define VUL_MODE_MASK 0xf 444c5e7fca9SKai Chieh Chuang #define VUL_MODE_MASK_SFT (0xf << 16) 445c5e7fca9SKai Chieh Chuang #define AWB_MODE_SFT 12 446c5e7fca9SKai Chieh Chuang #define AWB_MODE_MASK 0xf 447c5e7fca9SKai Chieh Chuang #define AWB_MODE_MASK_SFT (0xf << 12) 448c5e7fca9SKai Chieh Chuang #define I2S_MODE_SFT 8 449c5e7fca9SKai Chieh Chuang #define I2S_MODE_MASK 0xf 450c5e7fca9SKai Chieh Chuang #define I2S_MODE_MASK_SFT (0xf << 8) 451c5e7fca9SKai Chieh Chuang #define DL2_MODE_SFT 4 452c5e7fca9SKai Chieh Chuang #define DL2_MODE_MASK 0xf 453c5e7fca9SKai Chieh Chuang #define DL2_MODE_MASK_SFT (0xf << 4) 454c5e7fca9SKai Chieh Chuang #define DL1_MODE_SFT 0 455c5e7fca9SKai Chieh Chuang #define DL1_MODE_MASK 0xf 456c5e7fca9SKai Chieh Chuang #define DL1_MODE_MASK_SFT (0xf << 0) 457c5e7fca9SKai Chieh Chuang 458c5e7fca9SKai Chieh Chuang /* AFE_ADDA_DL_SRC2_CON0 */ 459c5e7fca9SKai Chieh Chuang #define DL_2_INPUT_MODE_CTL_SFT 28 460c5e7fca9SKai Chieh Chuang #define DL_2_INPUT_MODE_CTL_MASK 0xf 461c5e7fca9SKai Chieh Chuang #define DL_2_INPUT_MODE_CTL_MASK_SFT (0xf << 28) 462c5e7fca9SKai Chieh Chuang #define DL_2_CH1_SATURATION_EN_CTL_SFT 27 463c5e7fca9SKai Chieh Chuang #define DL_2_CH1_SATURATION_EN_CTL_MASK 0x1 464c5e7fca9SKai Chieh Chuang #define DL_2_CH1_SATURATION_EN_CTL_MASK_SFT (0x1 << 27) 465c5e7fca9SKai Chieh Chuang #define DL_2_CH2_SATURATION_EN_CTL_SFT 26 466c5e7fca9SKai Chieh Chuang #define DL_2_CH2_SATURATION_EN_CTL_MASK 0x1 467c5e7fca9SKai Chieh Chuang #define DL_2_CH2_SATURATION_EN_CTL_MASK_SFT (0x1 << 26) 468c5e7fca9SKai Chieh Chuang #define DL_2_OUTPUT_SEL_CTL_SFT 24 469c5e7fca9SKai Chieh Chuang #define DL_2_OUTPUT_SEL_CTL_MASK 0x3 470c5e7fca9SKai Chieh Chuang #define DL_2_OUTPUT_SEL_CTL_MASK_SFT (0x3 << 24) 471c5e7fca9SKai Chieh Chuang #define DL_2_FADEIN_0START_EN_SFT 16 472c5e7fca9SKai Chieh Chuang #define DL_2_FADEIN_0START_EN_MASK 0x3 473c5e7fca9SKai Chieh Chuang #define DL_2_FADEIN_0START_EN_MASK_SFT (0x3 << 16) 474c5e7fca9SKai Chieh Chuang #define DL_DISABLE_HW_CG_CTL_SFT 15 475c5e7fca9SKai Chieh Chuang #define DL_DISABLE_HW_CG_CTL_MASK 0x1 476c5e7fca9SKai Chieh Chuang #define DL_DISABLE_HW_CG_CTL_MASK_SFT (0x1 << 15) 477c5e7fca9SKai Chieh Chuang #define C_DATA_EN_SEL_CTL_PRE_SFT 14 478c5e7fca9SKai Chieh Chuang #define C_DATA_EN_SEL_CTL_PRE_MASK 0x1 479c5e7fca9SKai Chieh Chuang #define C_DATA_EN_SEL_CTL_PRE_MASK_SFT (0x1 << 14) 480c5e7fca9SKai Chieh Chuang #define DL_2_SIDE_TONE_ON_CTL_PRE_SFT 13 481c5e7fca9SKai Chieh Chuang #define DL_2_SIDE_TONE_ON_CTL_PRE_MASK 0x1 482c5e7fca9SKai Chieh Chuang #define DL_2_SIDE_TONE_ON_CTL_PRE_MASK_SFT (0x1 << 13) 483c5e7fca9SKai Chieh Chuang #define DL_2_MUTE_CH1_OFF_CTL_PRE_SFT 12 484c5e7fca9SKai Chieh Chuang #define DL_2_MUTE_CH1_OFF_CTL_PRE_MASK 0x1 485c5e7fca9SKai Chieh Chuang #define DL_2_MUTE_CH1_OFF_CTL_PRE_MASK_SFT (0x1 << 12) 486c5e7fca9SKai Chieh Chuang #define DL_2_MUTE_CH2_OFF_CTL_PRE_SFT 11 487c5e7fca9SKai Chieh Chuang #define DL_2_MUTE_CH2_OFF_CTL_PRE_MASK 0x1 488c5e7fca9SKai Chieh Chuang #define DL_2_MUTE_CH2_OFF_CTL_PRE_MASK_SFT (0x1 << 11) 489c5e7fca9SKai Chieh Chuang #define DL2_ARAMPSP_CTL_PRE_SFT 9 490c5e7fca9SKai Chieh Chuang #define DL2_ARAMPSP_CTL_PRE_MASK 0x3 491c5e7fca9SKai Chieh Chuang #define DL2_ARAMPSP_CTL_PRE_MASK_SFT (0x3 << 9) 492c5e7fca9SKai Chieh Chuang #define DL_2_IIRMODE_CTL_PRE_SFT 6 493c5e7fca9SKai Chieh Chuang #define DL_2_IIRMODE_CTL_PRE_MASK 0x7 494c5e7fca9SKai Chieh Chuang #define DL_2_IIRMODE_CTL_PRE_MASK_SFT (0x7 << 6) 495c5e7fca9SKai Chieh Chuang #define DL_2_VOICE_MODE_CTL_PRE_SFT 5 496c5e7fca9SKai Chieh Chuang #define DL_2_VOICE_MODE_CTL_PRE_MASK 0x1 497c5e7fca9SKai Chieh Chuang #define DL_2_VOICE_MODE_CTL_PRE_MASK_SFT (0x1 << 5) 498c5e7fca9SKai Chieh Chuang #define D2_2_MUTE_CH1_ON_CTL_PRE_SFT 4 499c5e7fca9SKai Chieh Chuang #define D2_2_MUTE_CH1_ON_CTL_PRE_MASK 0x1 500c5e7fca9SKai Chieh Chuang #define D2_2_MUTE_CH1_ON_CTL_PRE_MASK_SFT (0x1 << 4) 501c5e7fca9SKai Chieh Chuang #define D2_2_MUTE_CH2_ON_CTL_PRE_SFT 3 502c5e7fca9SKai Chieh Chuang #define D2_2_MUTE_CH2_ON_CTL_PRE_MASK 0x1 503c5e7fca9SKai Chieh Chuang #define D2_2_MUTE_CH2_ON_CTL_PRE_MASK_SFT (0x1 << 3) 504c5e7fca9SKai Chieh Chuang #define DL_2_IIR_ON_CTL_PRE_SFT 2 505c5e7fca9SKai Chieh Chuang #define DL_2_IIR_ON_CTL_PRE_MASK 0x1 506c5e7fca9SKai Chieh Chuang #define DL_2_IIR_ON_CTL_PRE_MASK_SFT (0x1 << 2) 507c5e7fca9SKai Chieh Chuang #define DL_2_GAIN_ON_CTL_PRE_SFT 1 508c5e7fca9SKai Chieh Chuang #define DL_2_GAIN_ON_CTL_PRE_MASK 0x1 509c5e7fca9SKai Chieh Chuang #define DL_2_GAIN_ON_CTL_PRE_MASK_SFT (0x1 << 1) 510c5e7fca9SKai Chieh Chuang #define DL_2_SRC_ON_TMP_CTL_PRE_SFT 0 511c5e7fca9SKai Chieh Chuang #define DL_2_SRC_ON_TMP_CTL_PRE_MASK 0x1 512c5e7fca9SKai Chieh Chuang #define DL_2_SRC_ON_TMP_CTL_PRE_MASK_SFT (0x1 << 0) 513c5e7fca9SKai Chieh Chuang 514c5e7fca9SKai Chieh Chuang /* AFE_ADDA_DL_SRC2_CON1 */ 515c5e7fca9SKai Chieh Chuang #define DL_2_GAIN_CTL_PRE_SFT 16 516c5e7fca9SKai Chieh Chuang #define DL_2_GAIN_CTL_PRE_MASK 0xffff 517c5e7fca9SKai Chieh Chuang #define DL_2_GAIN_CTL_PRE_MASK_SFT (0xffff << 16) 518c5e7fca9SKai Chieh Chuang #define DL_2_GAIN_MODE_CTL_SFT 0 519c5e7fca9SKai Chieh Chuang #define DL_2_GAIN_MODE_CTL_MASK 0x1 520c5e7fca9SKai Chieh Chuang #define DL_2_GAIN_MODE_CTL_MASK_SFT (0x1 << 0) 521c5e7fca9SKai Chieh Chuang 522c5e7fca9SKai Chieh Chuang /* AFE_ADDA_UL_SRC_CON0 */ 523c5e7fca9SKai Chieh Chuang #define C_COMB_OUT_SIN_GEN_CTL_SFT 31 524c5e7fca9SKai Chieh Chuang #define C_COMB_OUT_SIN_GEN_CTL_MASK 0x1 525c5e7fca9SKai Chieh Chuang #define C_COMB_OUT_SIN_GEN_CTL_MASK_SFT (0x1 << 31) 526c5e7fca9SKai Chieh Chuang #define C_BASEBAND_SIN_GEN_CTL_SFT 30 527c5e7fca9SKai Chieh Chuang #define C_BASEBAND_SIN_GEN_CTL_MASK 0x1 528c5e7fca9SKai Chieh Chuang #define C_BASEBAND_SIN_GEN_CTL_MASK_SFT (0x1 << 30) 529c5e7fca9SKai Chieh Chuang #define C_DIGMIC_PHASE_SEL_CH1_CTL_SFT 27 530c5e7fca9SKai Chieh Chuang #define C_DIGMIC_PHASE_SEL_CH1_CTL_MASK 0x7 531c5e7fca9SKai Chieh Chuang #define C_DIGMIC_PHASE_SEL_CH1_CTL_MASK_SFT (0x7 << 27) 532c5e7fca9SKai Chieh Chuang #define C_DIGMIC_PHASE_SEL_CH2_CTL_SFT 24 533c5e7fca9SKai Chieh Chuang #define C_DIGMIC_PHASE_SEL_CH2_CTL_MASK 0x7 534c5e7fca9SKai Chieh Chuang #define C_DIGMIC_PHASE_SEL_CH2_CTL_MASK_SFT (0x7 << 24) 535c5e7fca9SKai Chieh Chuang #define C_TWO_DIGITAL_MIC_CTL_SFT 23 536c5e7fca9SKai Chieh Chuang #define C_TWO_DIGITAL_MIC_CTL_MASK 0x1 537c5e7fca9SKai Chieh Chuang #define C_TWO_DIGITAL_MIC_CTL_MASK_SFT (0x1 << 23) 538c5e7fca9SKai Chieh Chuang #define UL_MODE_3P25M_CH2_CTL_SFT 22 539c5e7fca9SKai Chieh Chuang #define UL_MODE_3P25M_CH2_CTL_MASK 0x1 540c5e7fca9SKai Chieh Chuang #define UL_MODE_3P25M_CH2_CTL_MASK_SFT (0x1 << 22) 541c5e7fca9SKai Chieh Chuang #define UL_MODE_3P25M_CH1_CTL_SFT 21 542c5e7fca9SKai Chieh Chuang #define UL_MODE_3P25M_CH1_CTL_MASK 0x1 543c5e7fca9SKai Chieh Chuang #define UL_MODE_3P25M_CH1_CTL_MASK_SFT (0x1 << 21) 544c5e7fca9SKai Chieh Chuang #define UL_SRC_USE_CIC_OUT_CTL_SFT 20 545c5e7fca9SKai Chieh Chuang #define UL_SRC_USE_CIC_OUT_CTL_MASK 0x1 546c5e7fca9SKai Chieh Chuang #define UL_SRC_USE_CIC_OUT_CTL_MASK_SFT (0x1 << 20) 547c5e7fca9SKai Chieh Chuang #define UL_VOICE_MODE_CH1_CH2_CTL_SFT 17 548c5e7fca9SKai Chieh Chuang #define UL_VOICE_MODE_CH1_CH2_CTL_MASK 0x7 549c5e7fca9SKai Chieh Chuang #define UL_VOICE_MODE_CH1_CH2_CTL_MASK_SFT (0x7 << 17) 550c5e7fca9SKai Chieh Chuang #define DMIC_LOW_POWER_MODE_CTL_SFT 14 551c5e7fca9SKai Chieh Chuang #define DMIC_LOW_POWER_MODE_CTL_MASK 0x3 552c5e7fca9SKai Chieh Chuang #define DMIC_LOW_POWER_MODE_CTL_MASK_SFT (0x3 << 14) 553c5e7fca9SKai Chieh Chuang #define DMIC_48K_SEL_CTL_SFT 13 554c5e7fca9SKai Chieh Chuang #define DMIC_48K_SEL_CTL_MASK 0x1 555c5e7fca9SKai Chieh Chuang #define DMIC_48K_SEL_CTL_MASK_SFT (0x1 << 13) 556c5e7fca9SKai Chieh Chuang #define UL_DISABLE_HW_CG_CTL_SFT 12 557c5e7fca9SKai Chieh Chuang #define UL_DISABLE_HW_CG_CTL_MASK 0x1 558c5e7fca9SKai Chieh Chuang #define UL_DISABLE_HW_CG_CTL_MASK_SFT (0x1 << 12) 559c5e7fca9SKai Chieh Chuang #define UL_IIR_ON_TMP_CTL_SFT 10 560c5e7fca9SKai Chieh Chuang #define UL_IIR_ON_TMP_CTL_MASK 0x1 561c5e7fca9SKai Chieh Chuang #define UL_IIR_ON_TMP_CTL_MASK_SFT (0x1 << 10) 562c5e7fca9SKai Chieh Chuang #define UL_IIRMODE_CTL_SFT 7 563c5e7fca9SKai Chieh Chuang #define UL_IIRMODE_CTL_MASK 0x7 564c5e7fca9SKai Chieh Chuang #define UL_IIRMODE_CTL_MASK_SFT (0x7 << 7) 565c5e7fca9SKai Chieh Chuang #define DIGMIC_3P25M_1P625M_SEL_CTL_SFT 5 566c5e7fca9SKai Chieh Chuang #define DIGMIC_3P25M_1P625M_SEL_CTL_MASK 0x1 567c5e7fca9SKai Chieh Chuang #define DIGMIC_3P25M_1P625M_SEL_CTL_MASK_SFT (0x1 << 5) 568c5e7fca9SKai Chieh Chuang #define AGC_260K_SEL_CH2_CTL_SFT 4 569c5e7fca9SKai Chieh Chuang #define AGC_260K_SEL_CH2_CTL_MASK 0x1 570c5e7fca9SKai Chieh Chuang #define AGC_260K_SEL_CH2_CTL_MASK_SFT (0x1 << 4) 571c5e7fca9SKai Chieh Chuang #define AGC_260K_SEL_CH1_CTL_SFT 3 572c5e7fca9SKai Chieh Chuang #define AGC_260K_SEL_CH1_CTL_MASK 0x1 573c5e7fca9SKai Chieh Chuang #define AGC_260K_SEL_CH1_CTL_MASK_SFT (0x1 << 3) 574c5e7fca9SKai Chieh Chuang #define UL_LOOP_BACK_MODE_CTL_SFT 2 575c5e7fca9SKai Chieh Chuang #define UL_LOOP_BACK_MODE_CTL_MASK 0x1 576c5e7fca9SKai Chieh Chuang #define UL_LOOP_BACK_MODE_CTL_MASK_SFT (0x1 << 2) 577c5e7fca9SKai Chieh Chuang #define UL_SDM_3_LEVEL_CTL_SFT 1 578c5e7fca9SKai Chieh Chuang #define UL_SDM_3_LEVEL_CTL_MASK 0x1 579c5e7fca9SKai Chieh Chuang #define UL_SDM_3_LEVEL_CTL_MASK_SFT (0x1 << 1) 580c5e7fca9SKai Chieh Chuang #define UL_SRC_ON_TMP_CTL_SFT 0 581c5e7fca9SKai Chieh Chuang #define UL_SRC_ON_TMP_CTL_MASK 0x1 582c5e7fca9SKai Chieh Chuang #define UL_SRC_ON_TMP_CTL_MASK_SFT (0x1 << 0) 583c5e7fca9SKai Chieh Chuang 584c5e7fca9SKai Chieh Chuang /* AFE_ADDA_UL_SRC_CON1 */ 585c5e7fca9SKai Chieh Chuang #define C_SDM_RESET_CTL_SFT 31 586c5e7fca9SKai Chieh Chuang #define C_SDM_RESET_CTL_MASK 0x1 587c5e7fca9SKai Chieh Chuang #define C_SDM_RESET_CTL_MASK_SFT (0x1 << 31) 588c5e7fca9SKai Chieh Chuang #define ADITHON_CTL_SFT 30 589c5e7fca9SKai Chieh Chuang #define ADITHON_CTL_MASK 0x1 590c5e7fca9SKai Chieh Chuang #define ADITHON_CTL_MASK_SFT (0x1 << 30) 591c5e7fca9SKai Chieh Chuang #define ADITHVAL_CTL_SFT 28 592c5e7fca9SKai Chieh Chuang #define ADITHVAL_CTL_MASK 0x3 593c5e7fca9SKai Chieh Chuang #define ADITHVAL_CTL_MASK_SFT (0x3 << 28) 594c5e7fca9SKai Chieh Chuang #define C_DAC_EN_CTL_SFT 27 595c5e7fca9SKai Chieh Chuang #define C_DAC_EN_CTL_MASK 0x1 596c5e7fca9SKai Chieh Chuang #define C_DAC_EN_CTL_MASK_SFT (0x1 << 27) 597c5e7fca9SKai Chieh Chuang #define C_MUTE_SW_CTL_SFT 26 598c5e7fca9SKai Chieh Chuang #define C_MUTE_SW_CTL_MASK 0x1 599c5e7fca9SKai Chieh Chuang #define C_MUTE_SW_CTL_MASK_SFT (0x1 << 26) 600c5e7fca9SKai Chieh Chuang #define ASDM_SRC_SEL_CTL_SFT 25 601c5e7fca9SKai Chieh Chuang #define ASDM_SRC_SEL_CTL_MASK 0x1 602c5e7fca9SKai Chieh Chuang #define ASDM_SRC_SEL_CTL_MASK_SFT (0x1 << 25) 603c5e7fca9SKai Chieh Chuang #define C_AMP_DIV_CH2_CTL_SFT 21 604c5e7fca9SKai Chieh Chuang #define C_AMP_DIV_CH2_CTL_MASK 0x7 605c5e7fca9SKai Chieh Chuang #define C_AMP_DIV_CH2_CTL_MASK_SFT (0x7 << 21) 606c5e7fca9SKai Chieh Chuang #define C_FREQ_DIV_CH2_CTL_SFT 16 607c5e7fca9SKai Chieh Chuang #define C_FREQ_DIV_CH2_CTL_MASK 0x1f 608c5e7fca9SKai Chieh Chuang #define C_FREQ_DIV_CH2_CTL_MASK_SFT (0x1f << 16) 609c5e7fca9SKai Chieh Chuang #define C_SINE_MODE_CH2_CTL_SFT 12 610c5e7fca9SKai Chieh Chuang #define C_SINE_MODE_CH2_CTL_MASK 0xf 611c5e7fca9SKai Chieh Chuang #define C_SINE_MODE_CH2_CTL_MASK_SFT (0xf << 12) 612c5e7fca9SKai Chieh Chuang #define C_AMP_DIV_CH1_CTL_SFT 9 613c5e7fca9SKai Chieh Chuang #define C_AMP_DIV_CH1_CTL_MASK 0x7 614c5e7fca9SKai Chieh Chuang #define C_AMP_DIV_CH1_CTL_MASK_SFT (0x7 << 9) 615c5e7fca9SKai Chieh Chuang #define C_FREQ_DIV_CH1_CTL_SFT 4 616c5e7fca9SKai Chieh Chuang #define C_FREQ_DIV_CH1_CTL_MASK 0x1f 617c5e7fca9SKai Chieh Chuang #define C_FREQ_DIV_CH1_CTL_MASK_SFT (0x1f << 4) 618c5e7fca9SKai Chieh Chuang #define C_SINE_MODE_CH1_CTL_SFT 0 619c5e7fca9SKai Chieh Chuang #define C_SINE_MODE_CH1_CTL_MASK 0xf 620c5e7fca9SKai Chieh Chuang #define C_SINE_MODE_CH1_CTL_MASK_SFT (0xf << 0) 621c5e7fca9SKai Chieh Chuang 622c5e7fca9SKai Chieh Chuang /* AFE_ADDA_TOP_CON0 */ 623c5e7fca9SKai Chieh Chuang #define C_LOOP_BACK_MODE_CTL_SFT 12 624c5e7fca9SKai Chieh Chuang #define C_LOOP_BACK_MODE_CTL_MASK 0xf 625c5e7fca9SKai Chieh Chuang #define C_LOOP_BACK_MODE_CTL_MASK_SFT (0xf << 12) 626c5e7fca9SKai Chieh Chuang #define C_EXT_ADC_CTL_SFT 0 627c5e7fca9SKai Chieh Chuang #define C_EXT_ADC_CTL_MASK 0x1 628c5e7fca9SKai Chieh Chuang #define C_EXT_ADC_CTL_MASK_SFT (0x1 << 0) 629c5e7fca9SKai Chieh Chuang 630c5e7fca9SKai Chieh Chuang /* AFE_ADDA_UL_DL_CON0 */ 631c5e7fca9SKai Chieh Chuang #define AFE_UL_DL_CON0_RESERVED_SFT 1 632c5e7fca9SKai Chieh Chuang #define AFE_UL_DL_CON0_RESERVED_MASK 0x3fff 633c5e7fca9SKai Chieh Chuang #define AFE_UL_DL_CON0_RESERVED_MASK_SFT (0x3fff << 1) 634c5e7fca9SKai Chieh Chuang #define ADDA_AFE_ON_SFT 0 635c5e7fca9SKai Chieh Chuang #define ADDA_AFE_ON_MASK 0x1 636c5e7fca9SKai Chieh Chuang #define ADDA_AFE_ON_MASK_SFT (0x1 << 0) 637c5e7fca9SKai Chieh Chuang 638c5e7fca9SKai Chieh Chuang /* AFE_IRQ_MCU_CON */ 639c5e7fca9SKai Chieh Chuang #define IRQ7_MCU_MODE_SFT 24 640c5e7fca9SKai Chieh Chuang #define IRQ7_MCU_MODE_MASK 0xf 641c5e7fca9SKai Chieh Chuang #define IRQ7_MCU_MODE_MASK_SFT (0xf << 24) 642c5e7fca9SKai Chieh Chuang #define IRQ4_MCU_MODE_SFT 20 643c5e7fca9SKai Chieh Chuang #define IRQ4_MCU_MODE_MASK 0xf 644c5e7fca9SKai Chieh Chuang #define IRQ4_MCU_MODE_MASK_SFT (0xf << 20) 645c5e7fca9SKai Chieh Chuang #define IRQ3_MCU_MODE_SFT 16 646c5e7fca9SKai Chieh Chuang #define IRQ3_MCU_MODE_MASK 0xf 647c5e7fca9SKai Chieh Chuang #define IRQ3_MCU_MODE_MASK_SFT (0xf << 16) 648c5e7fca9SKai Chieh Chuang #define IRQ7_MCU_ON_SFT 14 649c5e7fca9SKai Chieh Chuang #define IRQ7_MCU_ON_MASK 0x1 650c5e7fca9SKai Chieh Chuang #define IRQ7_MCU_ON_MASK_SFT (0x1 << 14) 651c5e7fca9SKai Chieh Chuang #define IRQ5_MCU_ON_SFT 12 652c5e7fca9SKai Chieh Chuang #define IRQ5_MCU_ON_MASK 0x1 653c5e7fca9SKai Chieh Chuang #define IRQ5_MCU_ON_MASK_SFT (0x1 << 12) 654c5e7fca9SKai Chieh Chuang #define IRQ2_MCU_MODE_SFT 8 655c5e7fca9SKai Chieh Chuang #define IRQ2_MCU_MODE_MASK 0xf 656c5e7fca9SKai Chieh Chuang #define IRQ2_MCU_MODE_MASK_SFT (0xf << 8) 657c5e7fca9SKai Chieh Chuang #define IRQ1_MCU_MODE_SFT 4 658c5e7fca9SKai Chieh Chuang #define IRQ1_MCU_MODE_MASK 0xf 659c5e7fca9SKai Chieh Chuang #define IRQ1_MCU_MODE_MASK_SFT (0xf << 4) 660c5e7fca9SKai Chieh Chuang #define IRQ4_MCU_ON_SFT 3 661c5e7fca9SKai Chieh Chuang #define IRQ4_MCU_ON_MASK 0x1 662c5e7fca9SKai Chieh Chuang #define IRQ4_MCU_ON_MASK_SFT (0x1 << 3) 663c5e7fca9SKai Chieh Chuang #define IRQ3_MCU_ON_SFT 2 664c5e7fca9SKai Chieh Chuang #define IRQ3_MCU_ON_MASK 0x1 665c5e7fca9SKai Chieh Chuang #define IRQ3_MCU_ON_MASK_SFT (0x1 << 2) 666c5e7fca9SKai Chieh Chuang #define IRQ2_MCU_ON_SFT 1 667c5e7fca9SKai Chieh Chuang #define IRQ2_MCU_ON_MASK 0x1 668c5e7fca9SKai Chieh Chuang #define IRQ2_MCU_ON_MASK_SFT (0x1 << 1) 669c5e7fca9SKai Chieh Chuang #define IRQ1_MCU_ON_SFT 0 670c5e7fca9SKai Chieh Chuang #define IRQ1_MCU_ON_MASK 0x1 671c5e7fca9SKai Chieh Chuang #define IRQ1_MCU_ON_MASK_SFT (0x1 << 0) 672c5e7fca9SKai Chieh Chuang 673c5e7fca9SKai Chieh Chuang /* AFE_IRQ_MCU_EN */ 674c5e7fca9SKai Chieh Chuang #define AFE_IRQ_CM4_EN_SFT 16 675c5e7fca9SKai Chieh Chuang #define AFE_IRQ_CM4_EN_MASK 0x7f 676c5e7fca9SKai Chieh Chuang #define AFE_IRQ_CM4_EN_MASK_SFT (0x7f << 16) 677c5e7fca9SKai Chieh Chuang #define AFE_IRQ_MD32_EN_SFT 8 678c5e7fca9SKai Chieh Chuang #define AFE_IRQ_MD32_EN_MASK 0x7f 679c5e7fca9SKai Chieh Chuang #define AFE_IRQ_MD32_EN_MASK_SFT (0x7f << 8) 680c5e7fca9SKai Chieh Chuang #define AFE_IRQ_MCU_EN_SFT 0 681c5e7fca9SKai Chieh Chuang #define AFE_IRQ_MCU_EN_MASK 0x7f 682c5e7fca9SKai Chieh Chuang #define AFE_IRQ_MCU_EN_MASK_SFT (0x7f << 0) 683c5e7fca9SKai Chieh Chuang 684c5e7fca9SKai Chieh Chuang /* AFE_IRQ_MCU_CLR */ 685c5e7fca9SKai Chieh Chuang #define IRQ7_MCU_CLR_SFT 6 686c5e7fca9SKai Chieh Chuang #define IRQ7_MCU_CLR_MASK 0x1 687c5e7fca9SKai Chieh Chuang #define IRQ7_MCU_CLR_MASK_SFT (0x1 << 6) 688c5e7fca9SKai Chieh Chuang #define IRQ5_MCU_CLR_SFT 4 689c5e7fca9SKai Chieh Chuang #define IRQ5_MCU_CLR_MASK 0x1 690c5e7fca9SKai Chieh Chuang #define IRQ5_MCU_CLR_MASK_SFT (0x1 << 4) 691c5e7fca9SKai Chieh Chuang #define IRQ4_MCU_CLR_SFT 3 692c5e7fca9SKai Chieh Chuang #define IRQ4_MCU_CLR_MASK 0x1 693c5e7fca9SKai Chieh Chuang #define IRQ4_MCU_CLR_MASK_SFT (0x1 << 3) 694c5e7fca9SKai Chieh Chuang #define IRQ3_MCU_CLR_SFT 2 695c5e7fca9SKai Chieh Chuang #define IRQ3_MCU_CLR_MASK 0x1 696c5e7fca9SKai Chieh Chuang #define IRQ3_MCU_CLR_MASK_SFT (0x1 << 2) 697c5e7fca9SKai Chieh Chuang #define IRQ2_MCU_CLR_SFT 1 698c5e7fca9SKai Chieh Chuang #define IRQ2_MCU_CLR_MASK 0x1 699c5e7fca9SKai Chieh Chuang #define IRQ2_MCU_CLR_MASK_SFT (0x1 << 1) 700c5e7fca9SKai Chieh Chuang #define IRQ1_MCU_CLR_SFT 0 701c5e7fca9SKai Chieh Chuang #define IRQ1_MCU_CLR_MASK 0x1 702c5e7fca9SKai Chieh Chuang #define IRQ1_MCU_CLR_MASK_SFT (0x1 << 0) 703c5e7fca9SKai Chieh Chuang 704c5e7fca9SKai Chieh Chuang /* AFE_IRQ_MCU_CNT1 */ 705c5e7fca9SKai Chieh Chuang #define AFE_IRQ_MCU_CNT1_SFT 0 706c5e7fca9SKai Chieh Chuang #define AFE_IRQ_MCU_CNT1_MASK 0x3ffff 707c5e7fca9SKai Chieh Chuang #define AFE_IRQ_MCU_CNT1_MASK_SFT (0x3ffff << 0) 708c5e7fca9SKai Chieh Chuang 709c5e7fca9SKai Chieh Chuang /* AFE_IRQ_MCU_CNT2 */ 710c5e7fca9SKai Chieh Chuang #define AFE_IRQ_MCU_CNT2_SFT 0 711c5e7fca9SKai Chieh Chuang #define AFE_IRQ_MCU_CNT2_MASK 0x3ffff 712c5e7fca9SKai Chieh Chuang #define AFE_IRQ_MCU_CNT2_MASK_SFT (0x3ffff << 0) 713c5e7fca9SKai Chieh Chuang 714c5e7fca9SKai Chieh Chuang /* AFE_IRQ_MCU_CNT3 */ 715c5e7fca9SKai Chieh Chuang #define AFE_IRQ_MCU_CNT3_SFT 0 716c5e7fca9SKai Chieh Chuang #define AFE_IRQ_MCU_CNT3_MASK 0x3ffff 717c5e7fca9SKai Chieh Chuang #define AFE_IRQ_MCU_CNT3_MASK_SFT (0x3ffff << 0) 718c5e7fca9SKai Chieh Chuang 719c5e7fca9SKai Chieh Chuang /* AFE_IRQ_MCU_CNT4 */ 720c5e7fca9SKai Chieh Chuang #define AFE_IRQ_MCU_CNT4_SFT 0 721c5e7fca9SKai Chieh Chuang #define AFE_IRQ_MCU_CNT4_MASK 0x3ffff 722c5e7fca9SKai Chieh Chuang #define AFE_IRQ_MCU_CNT4_MASK_SFT (0x3ffff << 0) 723c5e7fca9SKai Chieh Chuang 724c5e7fca9SKai Chieh Chuang /* AFE_IRQ_MCU_CNT5 */ 725c5e7fca9SKai Chieh Chuang #define AFE_IRQ_MCU_CNT5_SFT 0 726c5e7fca9SKai Chieh Chuang #define AFE_IRQ_MCU_CNT5_MASK 0x3ffff 727c5e7fca9SKai Chieh Chuang #define AFE_IRQ_MCU_CNT5_MASK_SFT (0x3ffff << 0) 728c5e7fca9SKai Chieh Chuang 729c5e7fca9SKai Chieh Chuang /* AFE_IRQ_MCU_CNT7 */ 730c5e7fca9SKai Chieh Chuang #define AFE_IRQ_MCU_CNT7_SFT 0 731c5e7fca9SKai Chieh Chuang #define AFE_IRQ_MCU_CNT7_MASK 0x3ffff 732c5e7fca9SKai Chieh Chuang #define AFE_IRQ_MCU_CNT7_MASK_SFT (0x3ffff << 0) 733c5e7fca9SKai Chieh Chuang 734c5e7fca9SKai Chieh Chuang /* AFE_MEMIF_MSB */ 735c5e7fca9SKai Chieh Chuang #define CPU_COMPACT_MODE_SFT 23 736c5e7fca9SKai Chieh Chuang #define CPU_COMPACT_MODE_MASK 0x1 737c5e7fca9SKai Chieh Chuang #define CPU_COMPACT_MODE_MASK_SFT (0x1 << 23) 738c5e7fca9SKai Chieh Chuang #define CPU_HD_ALIGN_SFT 22 739c5e7fca9SKai Chieh Chuang #define CPU_HD_ALIGN_MASK 0x1 740c5e7fca9SKai Chieh Chuang #define CPU_HD_ALIGN_MASK_SFT (0x1 << 22) 741c5e7fca9SKai Chieh Chuang 742c5e7fca9SKai Chieh Chuang /* AFE_MEMIF_HD_MODE */ 743c5e7fca9SKai Chieh Chuang #define HDMI_HD_SFT 20 744c5e7fca9SKai Chieh Chuang #define HDMI_HD_MASK 0x3 745c5e7fca9SKai Chieh Chuang #define HDMI_HD_MASK_SFT (0x3 << 20) 746c5e7fca9SKai Chieh Chuang #define MOD_DAI_HD_SFT 18 747c5e7fca9SKai Chieh Chuang #define MOD_DAI_HD_MASK 0x3 748c5e7fca9SKai Chieh Chuang #define MOD_DAI_HD_MASK_SFT (0x3 << 18) 749c5e7fca9SKai Chieh Chuang #define DAI_HD_SFT 16 750c5e7fca9SKai Chieh Chuang #define DAI_HD_MASK 0x3 751c5e7fca9SKai Chieh Chuang #define DAI_HD_MASK_SFT (0x3 << 16) 752c5e7fca9SKai Chieh Chuang #define VUL_DATA2_HD_SFT 12 753c5e7fca9SKai Chieh Chuang #define VUL_DATA2_HD_MASK 0x3 754c5e7fca9SKai Chieh Chuang #define VUL_DATA2_HD_MASK_SFT (0x3 << 12) 755c5e7fca9SKai Chieh Chuang #define VUL_HD_SFT 10 756c5e7fca9SKai Chieh Chuang #define VUL_HD_MASK 0x3 757c5e7fca9SKai Chieh Chuang #define VUL_HD_MASK_SFT (0x3 << 10) 758c5e7fca9SKai Chieh Chuang #define AWB_HD_SFT 8 759c5e7fca9SKai Chieh Chuang #define AWB_HD_MASK 0x3 760c5e7fca9SKai Chieh Chuang #define AWB_HD_MASK_SFT (0x3 << 8) 761c5e7fca9SKai Chieh Chuang #define DL3_HD_SFT 6 762c5e7fca9SKai Chieh Chuang #define DL3_HD_MASK 0x3 763c5e7fca9SKai Chieh Chuang #define DL3_HD_MASK_SFT (0x3 << 6) 764c5e7fca9SKai Chieh Chuang #define DL2_HD_SFT 4 765c5e7fca9SKai Chieh Chuang #define DL2_HD_MASK 0x3 766c5e7fca9SKai Chieh Chuang #define DL2_HD_MASK_SFT (0x3 << 4) 767c5e7fca9SKai Chieh Chuang #define DL1_DATA2_HD_SFT 2 768c5e7fca9SKai Chieh Chuang #define DL1_DATA2_HD_MASK 0x3 769c5e7fca9SKai Chieh Chuang #define DL1_DATA2_HD_MASK_SFT (0x3 << 2) 770c5e7fca9SKai Chieh Chuang #define DL1_HD_SFT 0 771c5e7fca9SKai Chieh Chuang #define DL1_HD_MASK 0x3 772c5e7fca9SKai Chieh Chuang #define DL1_HD_MASK_SFT (0x3 << 0) 773c5e7fca9SKai Chieh Chuang 774c5e7fca9SKai Chieh Chuang /* AFE_MEMIF_HDALIGN */ 775c5e7fca9SKai Chieh Chuang #define HDMI_NORMAL_MODE_SFT 26 776c5e7fca9SKai Chieh Chuang #define HDMI_NORMAL_MODE_MASK 0x1 777c5e7fca9SKai Chieh Chuang #define HDMI_NORMAL_MODE_MASK_SFT (0x1 << 26) 778c5e7fca9SKai Chieh Chuang #define MOD_DAI_NORMAL_MODE_SFT 25 779c5e7fca9SKai Chieh Chuang #define MOD_DAI_NORMAL_MODE_MASK 0x1 780c5e7fca9SKai Chieh Chuang #define MOD_DAI_NORMAL_MODE_MASK_SFT (0x1 << 25) 781c5e7fca9SKai Chieh Chuang #define DAI_NORMAL_MODE_SFT 24 782c5e7fca9SKai Chieh Chuang #define DAI_NORMAL_MODE_MASK 0x1 783c5e7fca9SKai Chieh Chuang #define DAI_NORMAL_MODE_MASK_SFT (0x1 << 24) 784c5e7fca9SKai Chieh Chuang #define VUL_DATA2_NORMAL_MODE_SFT 22 785c5e7fca9SKai Chieh Chuang #define VUL_DATA2_NORMAL_MODE_MASK 0x1 786c5e7fca9SKai Chieh Chuang #define VUL_DATA2_NORMAL_MODE_MASK_SFT (0x1 << 22) 787c5e7fca9SKai Chieh Chuang #define VUL_NORMAL_MODE_SFT 21 788c5e7fca9SKai Chieh Chuang #define VUL_NORMAL_MODE_MASK 0x1 789c5e7fca9SKai Chieh Chuang #define VUL_NORMAL_MODE_MASK_SFT (0x1 << 21) 790c5e7fca9SKai Chieh Chuang #define AWB_NORMAL_MODE_SFT 20 791c5e7fca9SKai Chieh Chuang #define AWB_NORMAL_MODE_MASK 0x1 792c5e7fca9SKai Chieh Chuang #define AWB_NORMAL_MODE_MASK_SFT (0x1 << 20) 793c5e7fca9SKai Chieh Chuang #define DL3_NORMAL_MODE_SFT 19 794c5e7fca9SKai Chieh Chuang #define DL3_NORMAL_MODE_MASK 0x1 795c5e7fca9SKai Chieh Chuang #define DL3_NORMAL_MODE_MASK_SFT (0x1 << 19) 796c5e7fca9SKai Chieh Chuang #define DL2_NORMAL_MODE_SFT 18 797c5e7fca9SKai Chieh Chuang #define DL2_NORMAL_MODE_MASK 0x1 798c5e7fca9SKai Chieh Chuang #define DL2_NORMAL_MODE_MASK_SFT (0x1 << 18) 799c5e7fca9SKai Chieh Chuang #define DL1_DATA2_NORMAL_MODE_SFT 17 800c5e7fca9SKai Chieh Chuang #define DL1_DATA2_NORMAL_MODE_MASK 0x1 801c5e7fca9SKai Chieh Chuang #define DL1_DATA2_NORMAL_MODE_MASK_SFT (0x1 << 17) 802c5e7fca9SKai Chieh Chuang #define DL1_NORMAL_MODE_SFT 16 803c5e7fca9SKai Chieh Chuang #define DL1_NORMAL_MODE_MASK 0x1 804c5e7fca9SKai Chieh Chuang #define DL1_NORMAL_MODE_MASK_SFT (0x1 << 16) 805c5e7fca9SKai Chieh Chuang #define HDMI_HD_ALIGN_SFT 10 806c5e7fca9SKai Chieh Chuang #define HDMI_HD_ALIGN_MASK 0x1 807c5e7fca9SKai Chieh Chuang #define HDMI_HD_ALIGN_MASK_SFT (0x1 << 10) 808c5e7fca9SKai Chieh Chuang #define MOD_DAI_HD_ALIGN_SFT 9 809c5e7fca9SKai Chieh Chuang #define MOD_DAI_HD_ALIGN_MASK 0x1 810c5e7fca9SKai Chieh Chuang #define MOD_DAI_HD_ALIGN_MASK_SFT (0x1 << 9) 811c5e7fca9SKai Chieh Chuang #define DAI_ALIGN_SFT 8 812c5e7fca9SKai Chieh Chuang #define DAI_ALIGN_MASK 0x1 813c5e7fca9SKai Chieh Chuang #define DAI_ALIGN_MASK_SFT (0x1 << 8) 814c5e7fca9SKai Chieh Chuang #define VUL2_HD_ALIGN_SFT 7 815c5e7fca9SKai Chieh Chuang #define VUL2_HD_ALIGN_MASK 0x1 816c5e7fca9SKai Chieh Chuang #define VUL2_HD_ALIGN_MASK_SFT (0x1 << 7) 817c5e7fca9SKai Chieh Chuang #define VUL_DATA2_HD_ALIGN_SFT 6 818c5e7fca9SKai Chieh Chuang #define VUL_DATA2_HD_ALIGN_MASK 0x1 819c5e7fca9SKai Chieh Chuang #define VUL_DATA2_HD_ALIGN_MASK_SFT (0x1 << 6) 820c5e7fca9SKai Chieh Chuang #define VUL_HD_ALIGN_SFT 5 821c5e7fca9SKai Chieh Chuang #define VUL_HD_ALIGN_MASK 0x1 822c5e7fca9SKai Chieh Chuang #define VUL_HD_ALIGN_MASK_SFT (0x1 << 5) 823c5e7fca9SKai Chieh Chuang #define AWB_HD_ALIGN_SFT 4 824c5e7fca9SKai Chieh Chuang #define AWB_HD_ALIGN_MASK 0x1 825c5e7fca9SKai Chieh Chuang #define AWB_HD_ALIGN_MASK_SFT (0x1 << 4) 826c5e7fca9SKai Chieh Chuang #define DL3_HD_ALIGN_SFT 3 827c5e7fca9SKai Chieh Chuang #define DL3_HD_ALIGN_MASK 0x1 828c5e7fca9SKai Chieh Chuang #define DL3_HD_ALIGN_MASK_SFT (0x1 << 3) 829c5e7fca9SKai Chieh Chuang #define DL2_HD_ALIGN_SFT 2 830c5e7fca9SKai Chieh Chuang #define DL2_HD_ALIGN_MASK 0x1 831c5e7fca9SKai Chieh Chuang #define DL2_HD_ALIGN_MASK_SFT (0x1 << 2) 832c5e7fca9SKai Chieh Chuang #define DL1_DATA2_HD_ALIGN_SFT 1 833c5e7fca9SKai Chieh Chuang #define DL1_DATA2_HD_ALIGN_MASK 0x1 834c5e7fca9SKai Chieh Chuang #define DL1_DATA2_HD_ALIGN_MASK_SFT (0x1 << 1) 835c5e7fca9SKai Chieh Chuang #define DL1_HD_ALIGN_SFT 0 836c5e7fca9SKai Chieh Chuang #define DL1_HD_ALIGN_MASK 0x1 837c5e7fca9SKai Chieh Chuang #define DL1_HD_ALIGN_MASK_SFT (0x1 << 0) 838*314b355fSKai Chieh Chuang 839*314b355fSKai Chieh Chuang /* PCM_INTF_CON1 */ 840*314b355fSKai Chieh Chuang #define PCM_FIX_VALUE_SEL_SFT 31 841*314b355fSKai Chieh Chuang #define PCM_FIX_VALUE_SEL_MASK 0x1 842*314b355fSKai Chieh Chuang #define PCM_FIX_VALUE_SEL_MASK_SFT (0x1 << 31) 843*314b355fSKai Chieh Chuang #define PCM_BUFFER_LOOPBACK_SFT 30 844*314b355fSKai Chieh Chuang #define PCM_BUFFER_LOOPBACK_MASK 0x1 845*314b355fSKai Chieh Chuang #define PCM_BUFFER_LOOPBACK_MASK_SFT (0x1 << 30) 846*314b355fSKai Chieh Chuang #define PCM_PARALLEL_LOOPBACK_SFT 29 847*314b355fSKai Chieh Chuang #define PCM_PARALLEL_LOOPBACK_MASK 0x1 848*314b355fSKai Chieh Chuang #define PCM_PARALLEL_LOOPBACK_MASK_SFT (0x1 << 29) 849*314b355fSKai Chieh Chuang #define PCM_SERIAL_LOOPBACK_SFT 28 850*314b355fSKai Chieh Chuang #define PCM_SERIAL_LOOPBACK_MASK 0x1 851*314b355fSKai Chieh Chuang #define PCM_SERIAL_LOOPBACK_MASK_SFT (0x1 << 28) 852*314b355fSKai Chieh Chuang #define PCM_DAI_PCM_LOOPBACK_SFT 27 853*314b355fSKai Chieh Chuang #define PCM_DAI_PCM_LOOPBACK_MASK 0x1 854*314b355fSKai Chieh Chuang #define PCM_DAI_PCM_LOOPBACK_MASK_SFT (0x1 << 27) 855*314b355fSKai Chieh Chuang #define PCM_I2S_PCM_LOOPBACK_SFT 26 856*314b355fSKai Chieh Chuang #define PCM_I2S_PCM_LOOPBACK_MASK 0x1 857*314b355fSKai Chieh Chuang #define PCM_I2S_PCM_LOOPBACK_MASK_SFT (0x1 << 26) 858*314b355fSKai Chieh Chuang #define PCM_SYNC_DELSEL_SFT 25 859*314b355fSKai Chieh Chuang #define PCM_SYNC_DELSEL_MASK 0x1 860*314b355fSKai Chieh Chuang #define PCM_SYNC_DELSEL_MASK_SFT (0x1 << 25) 861*314b355fSKai Chieh Chuang #define PCM_TX_LR_SWAP_SFT 24 862*314b355fSKai Chieh Chuang #define PCM_TX_LR_SWAP_MASK 0x1 863*314b355fSKai Chieh Chuang #define PCM_TX_LR_SWAP_MASK_SFT (0x1 << 24) 864*314b355fSKai Chieh Chuang #define PCM_SYNC_OUT_INV_SFT 23 865*314b355fSKai Chieh Chuang #define PCM_SYNC_OUT_INV_MASK 0x1 866*314b355fSKai Chieh Chuang #define PCM_SYNC_OUT_INV_MASK_SFT (0x1 << 23) 867*314b355fSKai Chieh Chuang #define PCM_BCLK_OUT_INV_SFT 22 868*314b355fSKai Chieh Chuang #define PCM_BCLK_OUT_INV_MASK 0x1 869*314b355fSKai Chieh Chuang #define PCM_BCLK_OUT_INV_MASK_SFT (0x1 << 22) 870*314b355fSKai Chieh Chuang #define PCM_SYNC_IN_INV_SFT 21 871*314b355fSKai Chieh Chuang #define PCM_SYNC_IN_INV_MASK 0x1 872*314b355fSKai Chieh Chuang #define PCM_SYNC_IN_INV_MASK_SFT (0x1 << 21) 873*314b355fSKai Chieh Chuang #define PCM_BCLK_IN_INV_SFT 20 874*314b355fSKai Chieh Chuang #define PCM_BCLK_IN_INV_MASK 0x1 875*314b355fSKai Chieh Chuang #define PCM_BCLK_IN_INV_MASK_SFT (0x1 << 20) 876*314b355fSKai Chieh Chuang #define PCM_TX_LCH_RPT_SFT 19 877*314b355fSKai Chieh Chuang #define PCM_TX_LCH_RPT_MASK 0x1 878*314b355fSKai Chieh Chuang #define PCM_TX_LCH_RPT_MASK_SFT (0x1 << 19) 879*314b355fSKai Chieh Chuang #define PCM_VBT_16K_MODE_SFT 18 880*314b355fSKai Chieh Chuang #define PCM_VBT_16K_MODE_MASK 0x1 881*314b355fSKai Chieh Chuang #define PCM_VBT_16K_MODE_MASK_SFT (0x1 << 18) 882*314b355fSKai Chieh Chuang #define PCM_EXT_MODEM_SFT 17 883*314b355fSKai Chieh Chuang #define PCM_EXT_MODEM_MASK 0x1 884*314b355fSKai Chieh Chuang #define PCM_EXT_MODEM_MASK_SFT (0x1 << 17) 885*314b355fSKai Chieh Chuang #define PCM_24BIT_SFT 16 886*314b355fSKai Chieh Chuang #define PCM_24BIT_MASK 0x1 887*314b355fSKai Chieh Chuang #define PCM_24BIT_MASK_SFT (0x1 << 16) 888*314b355fSKai Chieh Chuang #define PCM_WLEN_SFT 14 889*314b355fSKai Chieh Chuang #define PCM_WLEN_MASK 0x3 890*314b355fSKai Chieh Chuang #define PCM_WLEN_MASK_SFT (0x3 << 14) 891*314b355fSKai Chieh Chuang #define PCM_SYNC_LENGTH_SFT 9 892*314b355fSKai Chieh Chuang #define PCM_SYNC_LENGTH_MASK 0x1f 893*314b355fSKai Chieh Chuang #define PCM_SYNC_LENGTH_MASK_SFT (0x1f << 9) 894*314b355fSKai Chieh Chuang #define PCM_SYNC_TYPE_SFT 8 895*314b355fSKai Chieh Chuang #define PCM_SYNC_TYPE_MASK 0x1 896*314b355fSKai Chieh Chuang #define PCM_SYNC_TYPE_MASK_SFT (0x1 << 8) 897*314b355fSKai Chieh Chuang #define PCM_BT_MODE_SFT 7 898*314b355fSKai Chieh Chuang #define PCM_BT_MODE_MASK 0x1 899*314b355fSKai Chieh Chuang #define PCM_BT_MODE_MASK_SFT (0x1 << 7) 900*314b355fSKai Chieh Chuang #define PCM_BYP_ASRC_SFT 6 901*314b355fSKai Chieh Chuang #define PCM_BYP_ASRC_MASK 0x1 902*314b355fSKai Chieh Chuang #define PCM_BYP_ASRC_MASK_SFT (0x1 << 6) 903*314b355fSKai Chieh Chuang #define PCM_SLAVE_SFT 5 904*314b355fSKai Chieh Chuang #define PCM_SLAVE_MASK 0x1 905*314b355fSKai Chieh Chuang #define PCM_SLAVE_MASK_SFT (0x1 << 5) 906*314b355fSKai Chieh Chuang #define PCM_MODE_SFT 3 907*314b355fSKai Chieh Chuang #define PCM_MODE_MASK 0x3 908*314b355fSKai Chieh Chuang #define PCM_MODE_MASK_SFT (0x3 << 3) 909*314b355fSKai Chieh Chuang #define PCM_FMT_SFT 1 910*314b355fSKai Chieh Chuang #define PCM_FMT_MASK 0x3 911*314b355fSKai Chieh Chuang #define PCM_FMT_MASK_SFT (0x3 << 1) 912*314b355fSKai Chieh Chuang #define PCM_EN_SFT 0 913*314b355fSKai Chieh Chuang #define PCM_EN_MASK 0x1 914*314b355fSKai Chieh Chuang #define PCM_EN_MASK_SFT (0x1 << 0) 915*314b355fSKai Chieh Chuang 916*314b355fSKai Chieh Chuang /* PCM_INTF_CON2 */ 917*314b355fSKai Chieh Chuang #define PCM1_TX_FIFO_OV_SFT 31 918*314b355fSKai Chieh Chuang #define PCM1_TX_FIFO_OV_MASK 0x1 919*314b355fSKai Chieh Chuang #define PCM1_TX_FIFO_OV_MASK_SFT (0x1 << 31) 920*314b355fSKai Chieh Chuang #define PCM1_RX_FIFO_OV_SFT 30 921*314b355fSKai Chieh Chuang #define PCM1_RX_FIFO_OV_MASK 0x1 922*314b355fSKai Chieh Chuang #define PCM1_RX_FIFO_OV_MASK_SFT (0x1 << 30) 923*314b355fSKai Chieh Chuang #define PCM2_TX_FIFO_OV_SFT 29 924*314b355fSKai Chieh Chuang #define PCM2_TX_FIFO_OV_MASK 0x1 925*314b355fSKai Chieh Chuang #define PCM2_TX_FIFO_OV_MASK_SFT (0x1 << 29) 926*314b355fSKai Chieh Chuang #define PCM2_RX_FIFO_OV_SFT 28 927*314b355fSKai Chieh Chuang #define PCM2_RX_FIFO_OV_MASK 0x1 928*314b355fSKai Chieh Chuang #define PCM2_RX_FIFO_OV_MASK_SFT (0x1 << 28) 929*314b355fSKai Chieh Chuang #define PCM1_SYNC_GLITCH_SFT 27 930*314b355fSKai Chieh Chuang #define PCM1_SYNC_GLITCH_MASK 0x1 931*314b355fSKai Chieh Chuang #define PCM1_SYNC_GLITCH_MASK_SFT (0x1 << 27) 932*314b355fSKai Chieh Chuang #define PCM2_SYNC_GLITCH_SFT 26 933*314b355fSKai Chieh Chuang #define PCM2_SYNC_GLITCH_MASK 0x1 934*314b355fSKai Chieh Chuang #define PCM2_SYNC_GLITCH_MASK_SFT (0x1 << 26) 935*314b355fSKai Chieh Chuang #define PCM1_PCM2_LOOPBACK_SFT 15 936*314b355fSKai Chieh Chuang #define PCM1_PCM2_LOOPBACK_MASK 0x1 937*314b355fSKai Chieh Chuang #define PCM1_PCM2_LOOPBACK_MASK_SFT (0x1 << 15) 938*314b355fSKai Chieh Chuang #define DAI_PCM_LOOPBACK_CH_SFT 13 939*314b355fSKai Chieh Chuang #define DAI_PCM_LOOPBACK_CH_MASK 0x1 940*314b355fSKai Chieh Chuang #define DAI_PCM_LOOPBACK_CH_MASK_SFT (0x1 << 13) 941*314b355fSKai Chieh Chuang #define I2S_PCM_LOOPBACK_CH_SFT 12 942*314b355fSKai Chieh Chuang #define I2S_PCM_LOOPBACK_CH_MASK 0x1 943*314b355fSKai Chieh Chuang #define I2S_PCM_LOOPBACK_CH_MASK_SFT (0x1 << 12) 944*314b355fSKai Chieh Chuang #define PCM_USE_MD3_SFT 8 945*314b355fSKai Chieh Chuang #define PCM_USE_MD3_MASK 0x1 946*314b355fSKai Chieh Chuang #define PCM_USE_MD3_MASK_SFT (0x1 << 8) 947*314b355fSKai Chieh Chuang #define TX_FIX_VALUE_SFT 0 948*314b355fSKai Chieh Chuang #define TX_FIX_VALUE_MASK 0xff 949*314b355fSKai Chieh Chuang #define TX_FIX_VALUE_MASK_SFT (0xff << 0) 950*314b355fSKai Chieh Chuang 951*314b355fSKai Chieh Chuang /* PCM2_INTF_CON */ 952*314b355fSKai Chieh Chuang #define PCM2_TX_FIX_VALUE_SFT 24 953*314b355fSKai Chieh Chuang #define PCM2_TX_FIX_VALUE_MASK 0xff 954*314b355fSKai Chieh Chuang #define PCM2_TX_FIX_VALUE_MASK_SFT (0xff << 24) 955*314b355fSKai Chieh Chuang #define PCM2_FIX_VALUE_SEL_SFT 23 956*314b355fSKai Chieh Chuang #define PCM2_FIX_VALUE_SEL_MASK 0x1 957*314b355fSKai Chieh Chuang #define PCM2_FIX_VALUE_SEL_MASK_SFT (0x1 << 23) 958*314b355fSKai Chieh Chuang #define PCM2_BUFFER_LOOPBACK_SFT 22 959*314b355fSKai Chieh Chuang #define PCM2_BUFFER_LOOPBACK_MASK 0x1 960*314b355fSKai Chieh Chuang #define PCM2_BUFFER_LOOPBACK_MASK_SFT (0x1 << 22) 961*314b355fSKai Chieh Chuang #define PCM2_PARALLEL_LOOPBACK_SFT 21 962*314b355fSKai Chieh Chuang #define PCM2_PARALLEL_LOOPBACK_MASK 0x1 963*314b355fSKai Chieh Chuang #define PCM2_PARALLEL_LOOPBACK_MASK_SFT (0x1 << 21) 964*314b355fSKai Chieh Chuang #define PCM2_SERIAL_LOOPBACK_SFT 20 965*314b355fSKai Chieh Chuang #define PCM2_SERIAL_LOOPBACK_MASK 0x1 966*314b355fSKai Chieh Chuang #define PCM2_SERIAL_LOOPBACK_MASK_SFT (0x1 << 20) 967*314b355fSKai Chieh Chuang #define PCM2_DAI_PCM_LOOPBACK_SFT 19 968*314b355fSKai Chieh Chuang #define PCM2_DAI_PCM_LOOPBACK_MASK 0x1 969*314b355fSKai Chieh Chuang #define PCM2_DAI_PCM_LOOPBACK_MASK_SFT (0x1 << 19) 970*314b355fSKai Chieh Chuang #define PCM2_I2S_PCM_LOOPBACK_SFT 18 971*314b355fSKai Chieh Chuang #define PCM2_I2S_PCM_LOOPBACK_MASK 0x1 972*314b355fSKai Chieh Chuang #define PCM2_I2S_PCM_LOOPBACK_MASK_SFT (0x1 << 18) 973*314b355fSKai Chieh Chuang #define PCM2_SYNC_DELSEL_SFT 17 974*314b355fSKai Chieh Chuang #define PCM2_SYNC_DELSEL_MASK 0x1 975*314b355fSKai Chieh Chuang #define PCM2_SYNC_DELSEL_MASK_SFT (0x1 << 17) 976*314b355fSKai Chieh Chuang #define PCM2_TX_LR_SWAP_SFT 16 977*314b355fSKai Chieh Chuang #define PCM2_TX_LR_SWAP_MASK 0x1 978*314b355fSKai Chieh Chuang #define PCM2_TX_LR_SWAP_MASK_SFT (0x1 << 16) 979*314b355fSKai Chieh Chuang #define PCM2_SYNC_IN_INV_SFT 15 980*314b355fSKai Chieh Chuang #define PCM2_SYNC_IN_INV_MASK 0x1 981*314b355fSKai Chieh Chuang #define PCM2_SYNC_IN_INV_MASK_SFT (0x1 << 15) 982*314b355fSKai Chieh Chuang #define PCM2_BCLK_IN_INV_SFT 14 983*314b355fSKai Chieh Chuang #define PCM2_BCLK_IN_INV_MASK 0x1 984*314b355fSKai Chieh Chuang #define PCM2_BCLK_IN_INV_MASK_SFT (0x1 << 14) 985*314b355fSKai Chieh Chuang #define PCM2_TX_LCH_RPT_SFT 13 986*314b355fSKai Chieh Chuang #define PCM2_TX_LCH_RPT_MASK 0x1 987*314b355fSKai Chieh Chuang #define PCM2_TX_LCH_RPT_MASK_SFT (0x1 << 13) 988*314b355fSKai Chieh Chuang #define PCM2_VBT_16K_MODE_SFT 12 989*314b355fSKai Chieh Chuang #define PCM2_VBT_16K_MODE_MASK 0x1 990*314b355fSKai Chieh Chuang #define PCM2_VBT_16K_MODE_MASK_SFT (0x1 << 12) 991*314b355fSKai Chieh Chuang #define PCM2_LOOPBACK_CH_SEL_SFT 10 992*314b355fSKai Chieh Chuang #define PCM2_LOOPBACK_CH_SEL_MASK 0x3 993*314b355fSKai Chieh Chuang #define PCM2_LOOPBACK_CH_SEL_MASK_SFT (0x3 << 10) 994*314b355fSKai Chieh Chuang #define PCM2_TX2_BT_MODE_SFT 8 995*314b355fSKai Chieh Chuang #define PCM2_TX2_BT_MODE_MASK 0x1 996*314b355fSKai Chieh Chuang #define PCM2_TX2_BT_MODE_MASK_SFT (0x1 << 8) 997*314b355fSKai Chieh Chuang #define PCM2_BT_MODE_SFT 7 998*314b355fSKai Chieh Chuang #define PCM2_BT_MODE_MASK 0x1 999*314b355fSKai Chieh Chuang #define PCM2_BT_MODE_MASK_SFT (0x1 << 7) 1000*314b355fSKai Chieh Chuang #define PCM2_AFIFO_SFT 6 1001*314b355fSKai Chieh Chuang #define PCM2_AFIFO_MASK 0x1 1002*314b355fSKai Chieh Chuang #define PCM2_AFIFO_MASK_SFT (0x1 << 6) 1003*314b355fSKai Chieh Chuang #define PCM2_WLEN_SFT 5 1004*314b355fSKai Chieh Chuang #define PCM2_WLEN_MASK 0x1 1005*314b355fSKai Chieh Chuang #define PCM2_WLEN_MASK_SFT (0x1 << 5) 1006*314b355fSKai Chieh Chuang #define PCM2_MODE_SFT 3 1007*314b355fSKai Chieh Chuang #define PCM2_MODE_MASK 0x3 1008*314b355fSKai Chieh Chuang #define PCM2_MODE_MASK_SFT (0x3 << 3) 1009*314b355fSKai Chieh Chuang #define PCM2_FMT_SFT 1 1010*314b355fSKai Chieh Chuang #define PCM2_FMT_MASK 0x3 1011*314b355fSKai Chieh Chuang #define PCM2_FMT_MASK_SFT (0x3 << 1) 1012*314b355fSKai Chieh Chuang #define PCM2_EN_SFT 0 1013*314b355fSKai Chieh Chuang #define PCM2_EN_MASK 0x1 1014*314b355fSKai Chieh Chuang #define PCM2_EN_MASK_SFT (0x1 << 0) 1015c5e7fca9SKai Chieh Chuang #endif 1016