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/linux/arch/sh/include/mach-common/mach/
H A Dtitan.h14 #define TITAN_IRQ_WAN evt2irq(0x240) /* eth0 (WAN) */
15 #define TITAN_IRQ_LAN evt2irq(0x2a0) /* eth1 (LAN) */
16 #define TITAN_IRQ_MPCIA evt2irq(0x300) /* mPCI A */
17 #define TITAN_IRQ_MPCIB evt2irq(0x360) /* mPCI B */
18 #define TITAN_IRQ_USB evt2irq(0x360) /* USB */
H A Dlboxre2.h12 #define IRQ_CF1 evt2irq(0x320) /* CF1 */
13 #define IRQ_CF0 evt2irq(0x340) /* CF0 */
14 #define IRQ_INTD evt2irq(0x360) /* INTD */
15 #define IRQ_ETH1 evt2irq(0x380) /* Ether1 */
16 #define IRQ_ETH0 evt2irq(0x3a0) /* Ether0 */
17 #define IRQ_INTA evt2irq(0x3c0) /* INTA */
/linux/drivers/gpu/drm/amd/include/asic_reg/dpcs/
H A Ddpcs_3_0_3_offset.h14 // base address: 0x0
15 …DPCSTX0_DPCSTX_TX_CLOCK_CNTL 0x2928
17 …DPCSTX0_DPCSTX_TX_CNTL 0x2929
19 …DPCSTX0_DPCSTX_CBUS_CNTL 0x292a
21 …DPCSTX0_DPCSTX_INTERRUPT_CNTL 0x292b
23 …DPCSTX0_DPCSTX_PLL_UPDATE_ADDR 0x292c
25 …DPCSTX0_DPCSTX_PLL_UPDATE_DATA 0x292d
30 // base address: 0x0
31 …RDPCSTX0_RDPCSTX_CNTL 0x2930
33 …RDPCSTX0_RDPCSTX_CLOCK_CNTL 0x2931
[all …]
H A Ddpcs_2_0_3_offset.h25 // base address: 0x0
26 …DPCSTX0_DPCSTX_TX_CLOCK_CNTL 0x2928
28 …DPCSTX0_DPCSTX_TX_CNTL 0x2929
30 …DPCSTX0_DPCSTX_CBUS_CNTL 0x292a
32 …DPCSTX0_DPCSTX_INTERRUPT_CNTL 0x292b
34 …DPCSTX0_DPCSTX_PLL_UPDATE_ADDR 0x292c
36 …DPCSTX0_DPCSTX_PLL_UPDATE_DATA 0x292d
41 // base address: 0x0
42 …RDPCSTX0_RDPCSTX_CNTL 0x2930
44 …RDPCSTX0_RDPCSTX_CLOCK_CNTL 0x2931
[all …]
H A Ddpcs_2_1_0_offset.h27 // base address: 0x0
28 …DPCSTX0_DPCSTX_TX_CLOCK_CNTL 0x2928
30 …DPCSTX0_DPCSTX_TX_CNTL 0x2929
32 …DPCSTX0_DPCSTX_CBUS_CNTL 0x292a
34 …DPCSTX0_DPCSTX_INTERRUPT_CNTL 0x292b
36 …DPCSTX0_DPCSTX_PLL_UPDATE_ADDR 0x292c
38 …DPCSTX0_DPCSTX_PLL_UPDATE_DATA 0x292d
40 …DPCSTX0_DPCSTX_DEBUG_CONFIG 0x292e
45 // base address: 0x0
46 …RDPCSTX0_RDPCSTX_CNTL 0x2930
[all …]
H A Ddpcs_3_0_0_offset.h14 // base address: 0x0
15 …DPCSTX0_DPCSTX_TX_CLOCK_CNTL 0x2928
17 …DPCSTX0_DPCSTX_TX_CNTL 0x2929
19 …DPCSTX0_DPCSTX_CBUS_CNTL 0x292a
21 …DPCSTX0_DPCSTX_INTERRUPT_CNTL 0x292b
23 …DPCSTX0_DPCSTX_PLL_UPDATE_ADDR 0x292c
25 …DPCSTX0_DPCSTX_PLL_UPDATE_DATA 0x292d
27 …DPCSTX0_DPCSTX_DEBUG_CONFIG 0x292e
32 // base address: 0x0
33 …RDPCSTX0_RDPCSTX_CNTL 0x2930
[all …]
H A Ddpcs_2_0_0_offset.h27 // base address: 0x0
28 …DPCSTX0_DPCSTX_TX_CLOCK_CNTL 0x2928
30 …DPCSTX0_DPCSTX_TX_CNTL 0x2929
32 …DPCSTX0_DPCSTX_CBUS_CNTL 0x292a
34 …DPCSTX0_DPCSTX_INTERRUPT_CNTL 0x292b
36 …DPCSTX0_DPCSTX_PLL_UPDATE_ADDR 0x292c
38 …DPCSTX0_DPCSTX_PLL_UPDATE_DATA 0x292d
40 …DPCSTX0_DPCSTX_DEBUG_CONFIG 0x292e
45 // base address: 0x0
46 …RDPCSTX0_RDPCSTX_CNTL 0x2930
[all …]
/linux/arch/sh/drivers/pci/
H A Dfixups-snapgear.c26 case 11: irq = evt2irq(0x300); break; /* USB */ in pcibios_map_platform_irq()
27 case 12: irq = evt2irq(0x360); break; /* PCMCIA */ in pcibios_map_platform_irq()
28 case 13: irq = evt2irq(0x2a0); break; /* eth0 */ in pcibios_map_platform_irq()
29 case 14: irq = evt2irq(0x300); break; /* eth1 */ in pcibios_map_platform_irq()
30 case 15: irq = evt2irq(0x360); break; /* safenet (unused) */ in pcibios_map_platform_irq()
/linux/drivers/gpu/drm/ci/xfails/
H A Di915-kbl-flakes.txt1 # Board Name: hp-x360-14-G1-sona
5 # Linux Version: 6.9.0-rc7
/linux/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hwio.h13 #define DISP_INTF_SEL 0x004
14 #define INTR_EN 0x010
15 #define INTR_STATUS 0x014
16 #define INTR_CLEAR 0x018
17 #define INTR2_EN 0x008
18 #define INTR2_STATUS 0x00c
19 #define SSPP_SPARE 0x028
20 #define INTR2_CLEAR 0x02c
21 #define HIST_INTR_EN 0x01c
22 #define HIST_INTR_STATUS 0x020
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mn-pinfunc.h14 …ne MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x020 0x25C 0x000 0x0 0x0
15 …ne MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x020 0x25C 0x55C 0x1 0x3
16 …ne MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x024 0x260 0x000 0x0 0x0
17 …ne MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x024 0x260 0x56C 0x1 0x3
18 …ne MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0
19 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x000 0x1 0x0
20 …ne MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0
21 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0
22 …ne MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0
23 …ne MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0
[all …]
/linux/arch/sh/include/mach-landisk/mach/
H A Diodata_landisk.h16 #define PA_USB 0xa4000000 /* USB Controller M66590 */
18 #define PA_ATARST 0xb0000000 /* ATA/FATA Access Control Register */
19 #define PA_LED 0xb0000001 /* LED Control Register */
20 #define PA_STATUS 0xb0000002 /* Switch Status Register */
21 #define PA_SHUTDOWN 0xb0000003 /* Shutdown Control Register */
22 #define PA_PCIPME 0xb0000004 /* PCI PME Status Register */
23 #define PA_IMASK 0xb0000005 /* Interrupt Mask Register */
25 #define PA_PWRINT_CLR 0xb0000006 /* Shutdown Interrupt clear Register */
27 #define PA_PIDE_OFFSET 0x40 /* CF IDE Offset */
28 #define PA_SIDE_OFFSET 0x40 /* HDD IDE Offset */
[all …]
/linux/include/linux/bcma/
H A Dbcma_driver_gmac_cmn.h7 #define BCMA_GMAC_CMN_STAG0 0x000
8 #define BCMA_GMAC_CMN_STAG1 0x004
9 #define BCMA_GMAC_CMN_STAG2 0x008
10 #define BCMA_GMAC_CMN_STAG3 0x00C
11 #define BCMA_GMAC_CMN_PARSER_CTL 0x020
12 #define BCMA_GMAC_CMN_MIB_MAX_LEN 0x024
13 #define BCMA_GMAC_CMN_PHY_ACCESS 0x100
14 #define BCMA_GMAC_CMN_PA_DATA_MASK 0x0000ffff
15 #define BCMA_GMAC_CMN_PA_ADDR_MASK 0x001f0000
17 #define BCMA_GMAC_CMN_PA_REG_MASK 0x1f000000
[all …]
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dti,dra7-iodelay.yaml30 const: 0
64 reg = <0x4844a000 0x0d1c>;
66 #size-cells = <0>;
71 0x18c A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A19_IN */
72 0x1a4 A_DELAY_PS(265) G_DELAY_PS(360) /* CFG_GPMC_A20_IN */
73 0x1b0 A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A21_IN */
74 0x1bc A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A22_IN */
75 0x1c8 A_DELAY_PS(287) G_DELAY_PS(420) /* CFG_GPMC_A23_IN */
76 0x1d4 A_DELAY_PS(144) G_DELAY_PS(240) /* CFG_GPMC_A24_IN */
77 0x1e0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_IN */
[all …]
/linux/sound/hda/codecs/realtek/
H A Dalc269.c52 static const hda_nid_t alc269_ignore[] = { 0x1d, 0 }; in alc269_parse_auto_config()
53 static const hda_nid_t alc269_ssids[] = { 0, 0x1b, 0x14, 0x21 }; in alc269_parse_auto_config()
54 static const hda_nid_t alc269va_ssids[] = { 0x15, 0x1b, 0x14, 0 }; in alc269_parse_auto_config()
104 int report = 0; in alc_headset_btn_callback()
131 case 0x10ec0215: in alc_disable_headset_jack_key()
132 case 0x10ec0225: in alc_disable_headset_jack_key()
133 case 0x10ec0285: in alc_disable_headset_jack_key()
134 case 0x10ec0287: in alc_disable_headset_jack_key()
135 case 0x10ec0295: in alc_disable_headset_jack_key()
136 case 0x10ec0289: in alc_disable_headset_jack_key()
[all …]
/linux/drivers/phy/qualcomm/
H A Dphy-qcom-qmp-qserdes-txrx-v10_60.h9 #define QSERDES_V10_60_TXRX_RES_CODE_LANE_OFFSET_TX 0x034
10 #define QSERDES_V10_60_TXRX_RES_CODE_LANE_OFFSET_RX 0x038
11 #define QSERDES_V10_60_TXRX_LANE_MODE_1 0x080
12 #define QSERDES_V10_60_TXRX_LANE_MODE_2 0x084
13 #define QSERDES_V10_60_TXRX_LANE_MODE_3 0x088
14 #define QSERDES_V10_60_TXRX_UCDR_FASTLOCK_FO_GAIN_RATE1 0x0c8
15 #define QSERDES_V10_60_TXRX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x0cc
16 #define QSERDES_V10_60_TXRX_UCDR_FASTLOCK_FO_GAIN_RATE3 0x0d0
17 #define QSERDES_V10_60_TXRX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x0d4
18 #define QSERDES_V10_60_TXRX_UCDR_FASTLOCK_SO_GAIN_RATE1 0x0e0
[all …]
/linux/drivers/hwmon/
H A Dgigabyte_waterforce.c3 * hwmon driver for Gigabyte AORUS Waterforce AIO CPU coolers: X240, X280 and X360.
18 #define USB_VENDOR_ID_GIGABYTE 0x1044
19 #define USB_PRODUCT_ID_WATERFORCE 0x7a4d /* Gigabyte AORUS WATERFORCE X240, X280 and X360 */
24 #define WATERFORCE_TEMP_SENSOR 0xD
25 #define WATERFORCE_FAN_SPEED 0x02
26 #define WATERFORCE_PUMP_SPEED 0x05
27 #define WATERFORCE_FAN_DUTY 0x08
28 #define WATERFORCE_PUMP_DUTY 0x09
31 static const u8 get_status_cmd[] = { 0x99, 0xDA };
35 static const u8 get_firmware_ver_cmd[] = { 0x99, 0xD6 };
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimxrt1050-pinfunc.h10 #define IMX_PAD_SION 0x40000000
17 #define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0
18 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0
19 #define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1
20 #define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0
21 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0
22 #define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0
24 #define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0
25 #define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0
26 #define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1
[all …]
H A Dimxrt1170-pinfunc.h10 #define IMX_PAD_SION 0x40000000
17 #define IOMUXC_GPIO_LPSR_00_FLEXCAN3_TX 0x000 0x040 0x0 0x0 0x0
18 #define IOMUXC_GPIO_LPSR_00_MIC_CLK 0x000 0x040 0x0 0x1 0x0
19 #define IOMUXC_GPIO_LPSR_00_MQS_RIGHT 0x000 0x040 0x0 0x2 0x0
20 #define IOMUXC_GPIO_LPSR_00_ARM_CM4_EVENTO 0x000 0x040 0x0 0x3 0x0
21 #define IOMUXC_GPIO_LPSR_00_GPIO_MUX6_IO00 0x000 0x040 0x0 0x5 0x0
22 #define IOMUXC_GPIO_LPSR_00_LPUART12_TXD 0x000 0x040 0x0B0 0x6 0x0
23 #define IOMUXC_GPIO_LPSR_00_SAI4_MCLK 0x000 0x040 0x0C8 0x7 0x0
24 #define IOMUXC_GPIO_LPSR_00_GPIO12_IO00 0x000 0x040 0x0 0xA 0x0
26 #define IOMUXC_GPIO_LPSR_01_FLEXCAN3_RX 0x004 0x044 0x080 0x0 0x0
[all …]
H A Dimx6sl-pinfunc.h13 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0
14 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0
15 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0
16 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0
17 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0
18 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0
19 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0
20 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0
21 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0
22 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0
[all …]
H A Dimx6dl-pinfunc.h13 #define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x04c 0x360 0x000 0x0 0x0
14 #define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x04c 0x360 0x000 0x1 0x0
15 #define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x04c 0x360 0x7f8 0x2 0x0
16 #define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x04c 0x360 0x000 0x3 0x0
17 #define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x04c 0x360 0x8fc 0x3 0x0
18 #define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x04c 0x360 0x000 0x5 0x0
19 #define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x04c 0x360 0x000 0x7 0x0
20 #define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x050 0x364 0x000 0x0 0x0
21 #define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 0x050 0x364 0x000 0x1 0x0
22 #define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x050 0x364 0x800 0x2 0x0
[all …]
/linux/drivers/net/wireless/intersil/p54/
H A Dp54usb.h19 #define NET2280_BASE 0x10000000
20 #define NET2280_BASE2 0x20000000
30 #define NET2280_CLK_STOP (0 << LOCAL_CLOCK_FREQUENCY)
44 #define NET2280_DEVINIT 0x00
45 #define NET2280_USBIRQENB1 0x24
46 #define NET2280_IRQSTAT1 0x2c
47 #define NET2280_FIFOCTL 0x38
48 #define NET2280_GPIOCTL 0x50
49 #define NET2280_RELNUM 0x88
50 #define NET2280_EPA_RSP 0x324
[all …]
/linux/drivers/platform/x86/intel/
H A Dvbtn.c21 /* Returned when NOT in tablet mode on some HP Stream x360 11 models */
22 #define VGBS_TABLET_MODE_FLAG_ALT 0x10
23 /* When NOT in tablet mode, VGBS returns with the flag 0x40 */
24 #define VGBS_TABLET_MODE_FLAG 0x40
25 #define VGBS_DOCK_MODE_FLAG 0x80
34 {"INT33D6", 0},
35 {"", 0},
41 { KE_KEY, 0xC0, { KEY_POWER } }, /* power key press */
42 { KE_IGNORE, 0xC1, { KEY_POWER } }, /* power key release */
43 { KE_KEY, 0xC2, { KEY_LEFTMETA } }, /* 'Windows' key press */
[all …]
/linux/include/dt-bindings/clock/
H A Dam4.h8 #define AM4_CLKCTRL_OFFSET 0x20
12 #define AM4_L3S_TSC_CLKCTRL_OFFSET 0x120
14 #define AM4_L3S_TSC_ADC_TSC_CLKCTRL AM4_L3S_TSC_CLKCTRL_INDEX(0x120)
17 #define AM4_L4_WKUP_AON_CLKCTRL_OFFSET 0x228
19 #define AM4_L4_WKUP_AON_WKUP_M3_CLKCTRL AM4_L4_WKUP_AON_CLKCTRL_INDEX(0x228)
20 #define AM4_L4_WKUP_AON_COUNTER_32K_CLKCTRL AM4_L4_WKUP_AON_CLKCTRL_INDEX(0x230)
23 #define AM4_L4_WKUP_CLKCTRL_OFFSET 0x220
25 #define AM4_L4_WKUP_L4_WKUP_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x220)
26 #define AM4_L4_WKUP_TIMER1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x328)
27 #define AM4_L4_WKUP_WD_TIMER2_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x338)
[all …]
/linux/arch/sh/include/mach-sdk7786/mach/
H A Dfpga.h9 #define SRSTR 0x000
10 #define SRSTR_MAGIC 0x1971 /* Fixed magical read value */
12 #define INTASR 0x010
13 #define INTAMR 0x020
14 #define MODSWR 0x030
15 #define INTTESTR 0x040
16 #define SYSSR 0x050
17 #define NRGPR 0x060
19 #define NMISR 0x070
20 #define NMISR_MAN_NMI BIT(0)
[all …]

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