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/linux/Documentation/devicetree/bindings/phy/
H A Dqcom,msm8996-qmp-pcie-phy.yaml57 "^phy@[0-9a-f]+$":
92 const: 0
98 const: 0
130 reg = <0x34000 0x488>;
133 ranges = <0x0 0x34000 0x4000>;
149 reg = <0x1000 0x130>,
150 <0x1200 0x200>,
151 <0x1400 0x1dc>;
156 #clock-cells = <0>;
159 #phy-cells = <0>;
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Dam57-pruss.dtsi11 reg = <0x4b226000 0x4>,
12 <0x4b226004 0x4>;
23 clocks = <&l4per2_clkctrl DRA7_L4PER2_PRUSS1_CLKCTRL 0>;
27 ranges = <0x00000000 0x4b200000 0x80000>;
29 pruss1: pruss@0 {
31 reg = <0x0 0x80000>;
36 pruss1_mem: memories@0 {
37 reg = <0x0 0x2000>,
38 <0x2000 0x2000>,
39 <0x10000 0x8000>;
[all …]
H A Dam4372.dtsi20 memory@0 {
22 reg = <0 0>;
42 #size-cells = <0>;
43 cpu: cpu@0 {
47 reg = <0>;
77 opp-supported-hw = <0xFF 0x01>;
85 opp-supported-hw = <0xFF 0x04>;
92 opp-supported-hw = <0xFF 0x08>;
99 opp-supported-hw = <0xFF 0x10>;
106 opp-supported-hw = <0xFF 0x20>;
[all …]
H A Domap5-l4.dtsi1 &l4_cfg { /* 0x4a000000 */
4 clocks = <&l4cfg_clkctrl OMAP5_L4_CFG_CLKCTRL 0>;
6 reg = <0x4a000000 0x800>,
7 <0x4a000800 0x800>,
8 <0x4a001000 0x1000>;
12 ranges = <0x00000000 0x4a000000 0x080000>, /* segment 0 */
13 <0x00080000 0x4a080000 0x080000>, /* segment 1 */
14 <0x00100000 0x4a100000 0x080000>, /* segment 2 */
15 <0x00180000 0x4a180000 0x080000>, /* segment 3 */
16 <0x00200000 0x4a200000 0x080000>, /* segment 4 */
[all …]
H A Domap4-l4.dtsi2 &l4_cfg { /* 0x4a000000 */
5 clocks = <&l4_cfg_clkctrl OMAP4_L4_CFG_CLKCTRL 0>;
7 reg = <0x4a000000 0x800>,
8 <0x4a000800 0x800>,
9 <0x4a001000 0x1000>;
13 ranges = <0x00000000 0x4a000000 0x080000>, /* segment 0 */
14 <0x00080000 0x4a080000 0x080000>, /* segment 1 */
15 <0x00100000 0x4a100000 0x080000>, /* segment 2 */
16 <0x00180000 0x4a180000 0x080000>, /* segment 3 */
17 <0x00200000 0x4a200000 0x080000>, /* segment 4 */
[all …]
/linux/include/linux/mfd/
H A Drsmu.h16 RSMU_CM = 0x34000,
17 RSMU_SABRE = 0x33810,
18 RSMU_SL = 0x19850,
/linux/drivers/gpu/drm/msm/disp/mdp5/
H A Dmdp5_cfg.c22 0,
35 .base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 },
36 .flush_hw_mask = 0x0003ffff,
40 .base = { 0x01100, 0x01500, 0x01900 },
45 0,
49 .base = { 0x01d00, 0x02100, 0x02500 },
53 0,
57 .base = { 0x02900, 0x02d00 },
60 0,
64 .base = { 0x03100, 0x03500, 0x03900, 0x03d00, 0x04100 },
[all …]
/linux/Documentation/devicetree/bindings/remoteproc/
H A Dti,pru-rproc.yaml19 The K3 SoCs containing ICSSG v1.0 (eg: AM65x SR1.0) also have two Auxiliary
21 containing the revised ICSSG v1.1 (eg: J721E, AM65x SR2.0) have an extra two
46 - ti,am654-tx-pru # for Tx_PRUs in K3 AM65x SR2.0 SoCs
90 pattern: "^rtu@[0-9a-f]+$"
102 pattern: "^txpru@[0-9a-f]+"
106 pattern: "^pru@[0-9a-f]+$"
119 pruss_tm: target-module@300000 { /* 0x4a300000, ap 9 04.0 */
123 ranges = <0x0 0x300000 0x80000>;
125 pruss: pruss@0 {
127 reg = <0x0 0x80000>;
[all …]
/linux/arch/arm/mach-mv78xx0/
H A Dmv78xx0.h17 * f0800000 PCIe #0 I/O space
29 * fee00000 f0800000 64K PCIe #0 I/O space
39 #define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000
40 #define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000
41 #define MV78XX0_CORE_REGS_VIRT_BASE IOMEM(0xfe400000)
42 #define MV78XX0_CORE_REGS_PHYS_BASE 0xfe400000
45 #define MV78XX0_PCIE_IO_PHYS_BASE(i) (0xf0800000 + ((i) << 20))
48 #define MV78XX0_REGS_PHYS_BASE 0xf1000000
49 #define MV78XX0_REGS_VIRT_BASE IOMEM(0xfec00000)
52 #define MV78XX0_SRAM_PHYS_BASE (0xf2200000)
[all …]
/linux/arch/mips/boot/dts/loongson/
H A Dloongson1b.dtsi57 reg = <0x1fe78030 0x8>;
66 reg = <0x420 0x8>;
71 reg = <0x1160 0x4>;
82 reg = <0x100000 0x100>;
84 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
90 reg = <0x108000 0x100>;
98 reg = <0x110000 0x10000>;
111 reg = <0x120000 0x10000>;
126 reg = <0x1c030 0x10>;
134 reg = <0x1c060 0xc>;
[all …]
/linux/arch/powerpc/boot/dts/fsl/
H A Db4si-post.dtsi37 alloc-ranges = <0 0 0x10000 0>;
42 alloc-ranges = <0 0 0x10000 0>;
47 alloc-ranges = <0 0 0x10000 0>;
54 interrupts = <25 2 0 0>;
57 /* controller at 0x200000 */
63 bus-range = <0x0 0xff>;
64 interrupts = <20 2 0 0>;
66 pcie@0 {
71 reg = <0 0 0 0 0>;
72 interrupts = <20 2 0 0>;
[all …]
H A Dt2081si-post.dtsi37 alloc-ranges = <0 0 0x10000 0>;
42 alloc-ranges = <0 0 0x10000 0>;
47 alloc-ranges = <0 0 0x10000 0>;
54 interrupts = <25 2 0 0>;
57 /* controller at 0x240000 */
59 compatible = "fsl,t2080-pcie", "fsl,qoriq-pcie-v3.0", "fsl,qoriq-pcie";
63 bus-range = <0x0 0xff>;
64 interrupts = <20 2 0 0>;
66 pcie@0 {
67 reg = <0 0 0 0 0>;
[all …]
H A Dt4240si-post.dtsi37 alloc-ranges = <0 0 0x10000 0>;
42 alloc-ranges = <0 0 0x10000 0>;
47 alloc-ranges = <0 0 0x10000 0>;
54 interrupts = <25 2 0 0>;
57 /* controller at 0x240000 */
59 compatible = "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0";
63 bus-range = <0x0 0xff>;
64 interrupts = <20 2 0 0>;
65 pcie@0 {
70 reg = <0 0 0 0 0>;
[all …]
/linux/arch/arm/boot/dts/broadcom/
H A Dbcm-hr2.dtsi45 #size-cells = <0>;
47 cpu0: cpu@0 {
51 reg = <0x0>;
64 ranges = <0x00000000 0x19000000 0x00023000>;
68 a9pll: arm_clk@0 {
69 #clock-cells = <0>;
72 reg = <0x0 0x1000>;
77 reg = <0x20200 0x100>;
84 reg = <0x20600 0x20>;
92 reg = <0x20620 0x20>;
[all …]
H A Dbcm-nsp.dtsi54 #size-cells = <0>;
56 cpu0: cpu@0 {
60 reg = <0x0>;
68 secondary-boot-reg = <0xffff0fec>;
69 reg = <0x1>;
82 ranges = <0x00000000 0x19000000 0x00023000>;
86 a9pll: arm_clk@0 {
87 #clock-cells = <0>;
90 reg = <0x00000 0x1000>;
95 reg = <0x20200 0x100>;
[all …]
/linux/arch/mips/include/asm/sn/sn0/
H A Dkldir.h28 * 0x2000000 (32M) +-----------------------------------------+
30 * 0x1F80000 (31.5M) +-----------------------------------------+
32 * 0x1C00000 (30M) +-----------------------------------------+
34 * 0x0800000 (28M) +-----------------------------------------+
36 * 0x1B00000 (27M) +-----------------------------------------+
38 * 0x1A00000 (26M) +-----------------------------------------+
40 * 0x1800000 (24M) +-----------------------------------------+
42 * 0x1600000 (22M) +-----------------------------------------+
48 * 0x190000 (2M--) +-----------------------------------------+
51 * 0x34000 (208K) +-----------------------------------------+
[all …]
/linux/drivers/net/wireless/ath/ath10k/
H A Dcoredump.c21 {0x800, 0x810},
22 {0x820, 0x82C},
23 {0x830, 0x8F4},
24 {0x90C, 0x91C},
25 {0xA14, 0xA18},
26 {0xA84, 0xA94},
27 {0xAA8, 0xAD4},
28 {0xADC, 0xB40},
29 {0x1000, 0x10A4},
30 {0x10BC, 0x111C},
[all …]
/linux/arch/arm/boot/dts/marvell/
H A Darmada-xp-mv78260.dtsi27 #size-cells = <0>;
30 cpu@0 {
33 reg = <0>;
34 clocks = <&cpuclk 0>;
49 * MV78260 has 3 PCIe units Gen2.0: Two units can be
62 bus-range = <0x00 0xff>;
65 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
66 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
67 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
68 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
[all …]
H A Darmada-xp-mv78460.dtsi28 #size-cells = <0>;
31 cpu@0 {
34 reg = <0>;
35 clocks = <&cpuclk 0>;
66 * MV78460 has 4 PCIe units Gen2.0: Two units can be
79 bus-range = <0x00 0xff>;
82 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
83 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
84 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
85 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
[all …]
H A Darmada-38x.dtsi42 pcie-mem-aperture = <0xe0000000 0x8000000>;
43 pcie-io-aperture = <0xe8000000 0x100000>;
47 reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
52 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
53 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
56 clocks = <&coreclk 0>;
62 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
63 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
66 clocks = <&coreclk 0>;
72 reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
[all …]
/linux/arch/arm64/boot/dts/ti/
H A Dk3-am65-main.dtsi12 reg = <0x0 0x70000000 0x0 0x200000>;
15 ranges = <0x0 0x0 0x70000000 0x200000>;
17 atf-sram@0 {
18 reg = <0x0 0x20000>;
22 reg = <0xf0000 0x10000>;
26 reg = <0x100000 0x100000>;
37 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
38 <0x00 0x01880000 0x00 0x90000>, /* GICR */
39 <0x00 0x6f000000 0x00 0x2000>, /* GICC */
40 <0x00 0x6f010000 0x00 0x1000>, /* GICH */
[all …]
/linux/drivers/net/ethernet/microchip/lan966x/
H A Dlan966x_main.c17 #define XTR_EOF_0 0x00000080U
18 #define XTR_EOF_1 0x01000080U
19 #define XTR_EOF_2 0x02000080U
20 #define XTR_EOF_3 0x03000080U
21 #define XTR_PRUNED 0x04000080U
22 #define XTR_ABORT 0x05000080U
23 #define XTR_ESCAPE 0x06000080U
24 #define XTR_NOT_READY 0x07000080U
42 { TARGET_CPU, 0xc0000, 0 }, /* 0xe00c0000 */
43 { TARGET_FDMA, 0xc0400, 0 }, /* 0xe00c0400 */
[all …]
/linux/drivers/interconnect/qcom/
H A Dsm8650.c29 .port_offsets = { 0xc000 },
31 .urg_fwd = 0,
32 .prio_fwd_disable = 0,
47 .port_offsets = { 0xd000 },
49 .urg_fwd = 0,
50 .prio_fwd_disable = 0,
74 .port_offsets = { 0xe000 },
76 .urg_fwd = 0,
77 .prio_fwd_disable = 0,
92 .port_offsets = { 0xf000 },
[all …]
/linux/drivers/clk/qcom/
H A Dgcc-msm8916.c45 .l_reg = 0x21004,
46 .m_reg = 0x21008,
47 .n_reg = 0x2100c,
48 .config_reg = 0x21010,
49 .mode_reg = 0x21000,
50 .status_reg = 0x2101c,
63 .enable_reg = 0x45000,
64 .enable_mask = BIT(0),
76 .l_reg = 0x20004,
77 .m_reg = 0x20008,
[all …]
H A Dgcc-msm8996.c49 .offset = 0x00000,
52 .enable_reg = 0x52000,
53 .enable_mask = BIT(0),
79 .offset = 0x00000,
94 .enable_reg = 0x5200c,
95 .enable_mask = BIT(0),
111 .enable_reg = 0x5200c,
126 .offset = 0x77000,
129 .enable_reg = 0x52000,
143 .offset = 0x77000,
[all …]

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