xref: /linux/arch/arm/boot/dts/ti/omap/am4372.dtsi (revision 621cde16e49b3ecf7d59a8106a20aaebfb4a59a9)
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Device Tree Source for AM4372 SoC
4 *
5 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
6 */
7
8#include <dt-bindings/bus/ti-sysc.h>
9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/clock/am4.h>
12
13/ {
14	compatible = "ti,am4372", "ti,am43";
15	interrupt-parent = <&wakeupgen>;
16	#address-cells = <1>;
17	#size-cells = <1>;
18	chosen { };
19
20	memory@0 {
21		device_type = "memory";
22		reg = <0 0>;
23	};
24
25	aliases {
26		i2c0 = &i2c0;
27		i2c1 = &i2c1;
28		i2c2 = &i2c2;
29		serial0 = &uart0;
30		serial1 = &uart1;
31		serial2 = &uart2;
32		serial3 = &uart3;
33		serial4 = &uart4;
34		serial5 = &uart5;
35		ethernet0 = &cpsw_port1;
36		ethernet1 = &cpsw_port2;
37		spi0 = &qspi;
38	};
39
40	cpus {
41		#address-cells = <1>;
42		#size-cells = <0>;
43		cpu: cpu@0 {
44			compatible = "arm,cortex-a9";
45			enable-method = "ti,am4372";
46			device_type = "cpu";
47			reg = <0>;
48
49			clocks = <&dpll_mpu_ck>;
50			clock-names = "cpu";
51
52			operating-points-v2 = <&cpu0_opp_table>;
53
54			clock-latency = <300000>; /* From omap-cpufreq driver */
55			cpu-idle-states = <&mpu_gate>;
56		};
57
58		idle-states {
59			mpu_gate: mpu_gate {
60				compatible = "arm,idle-state";
61				entry-latency-us = <40>;
62				exit-latency-us = <100>;
63				min-residency-us = <300>;
64				local-timer-stop;
65			};
66		};
67	};
68
69	cpu0_opp_table: opp-table {
70		compatible = "operating-points-v2-ti-cpu";
71		syscon = <&scm_conf>;
72
73		opp-50-300000000 {
74			/* OPP50 */
75			opp-hz = /bits/ 64 <300000000>;
76			opp-microvolt = <950000 931000 969000>;
77			opp-supported-hw = <0xFF 0x01>;
78			opp-suspend;
79		};
80
81		opp-100-600000000 {
82			/* OPP100 */
83			opp-hz = /bits/ 64 <600000000>;
84			opp-microvolt = <1100000 1078000 1122000>;
85			opp-supported-hw = <0xFF 0x04>;
86		};
87
88		opp-120-720000000 {
89			/* OPP120 */
90			opp-hz = /bits/ 64 <720000000>;
91			opp-microvolt = <1200000 1176000 1224000>;
92			opp-supported-hw = <0xFF 0x08>;
93		};
94
95		opp-800000000 {
96			/* OPP Turbo */
97			opp-hz = /bits/ 64 <800000000>;
98			opp-microvolt = <1260000 1234800 1285200>;
99			opp-supported-hw = <0xFF 0x10>;
100		};
101
102		opp-1000000000 {
103			/* OPP Nitro */
104			opp-hz = /bits/ 64 <1000000000>;
105			opp-microvolt = <1325000 1298500 1351500>;
106			opp-supported-hw = <0xFF 0x20>;
107		};
108	};
109
110	soc {
111		compatible = "ti,omap-infra";
112	};
113
114	gic: interrupt-controller@48241000 {
115		compatible = "arm,cortex-a9-gic";
116		interrupt-controller;
117		#interrupt-cells = <3>;
118		reg = <0x48241000 0x1000>,
119		      <0x48240100 0x0100>;
120		interrupt-parent = <&gic>;
121	};
122
123	wakeupgen: interrupt-controller@48281000 {
124		compatible = "ti,omap4-wugen-mpu";
125		interrupt-controller;
126		#interrupt-cells = <3>;
127		reg = <0x48281000 0x1000>;
128		interrupt-parent = <&gic>;
129	};
130
131	scu: scu@48240000 {
132		compatible = "arm,cortex-a9-scu";
133		reg = <0x48240000 0x100>;
134	};
135
136	global_timer: timer@48240200 {
137		compatible = "arm,cortex-a9-global-timer";
138		reg = <0x48240200 0x100>;
139		interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
140		interrupt-parent = <&gic>;
141		clocks = <&mpu_periphclk>;
142	};
143
144	local_timer: timer@48240600 {
145		compatible = "arm,cortex-a9-twd-timer";
146		reg = <0x48240600 0x100>;
147		interrupts = <GIC_PPI 13 IRQ_TYPE_EDGE_RISING>;
148		interrupt-parent = <&gic>;
149		clocks = <&mpu_periphclk>;
150	};
151
152	cache-controller@48242000 {
153		compatible = "arm,pl310-cache";
154		reg = <0x48242000 0x1000>;
155		cache-unified;
156		cache-level = <2>;
157	};
158
159	ocp@44000000 {
160		compatible = "simple-pm-bus";
161		power-domains = <&prm_per>;
162		clocks = <&l3_clkctrl AM4_L3_L3_MAIN_CLKCTRL 0>;
163		clock-names = "fck";
164		#address-cells = <1>;
165		#size-cells = <1>;
166		ranges;
167		ti,no-idle;
168
169		l3-noc@44000000 {
170			compatible = "ti,am4372-l3-noc";
171			reg = <0x44000000 0x400000>,
172			      <0x44800000 0x400000>;
173			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
174				     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
175		};
176
177		l4_wkup: interconnect@44c00000 {
178		};
179		l4_per: interconnect@48000000 {
180		};
181		l4_fast: interconnect@4a000000 {
182		};
183
184		target-module@4c000000 {
185			compatible = "ti,sysc-omap4-simple", "ti,sysc";
186			reg = <0x4c000000 0x4>;
187			reg-names = "rev";
188			clocks = <&emif_clkctrl AM4_EMIF_EMIF_CLKCTRL 0>;
189			clock-names = "fck";
190			ti,no-idle;
191			#address-cells = <1>;
192			#size-cells = <1>;
193			ranges = <0x0 0x4c000000 0x1000000>;
194
195			emif: emif@0 {
196				compatible = "ti,emif-am4372";
197				reg = <0 0x1000000>;
198				interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
199				sram = <&pm_sram_code
200					&pm_sram_data>;
201			};
202		};
203
204		target-module@49000000 {
205			compatible = "ti,sysc-omap4", "ti,sysc";
206			reg = <0x49000000 0x4>;
207			reg-names = "rev";
208			clocks = <&l3_clkctrl AM4_L3_TPCC_CLKCTRL 0>;
209			clock-names = "fck";
210			#address-cells = <1>;
211			#size-cells = <1>;
212			ranges = <0x0 0x49000000 0x10000>;
213
214			edma: dma@0 {
215				compatible = "ti,edma3-tpcc";
216				reg = <0 0x10000>;
217				reg-names = "edma3_cc";
218				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
219					     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
220					     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
221				interrupt-names = "edma3_ccint", "edma3_mperr",
222						  "edma3_ccerrint";
223				dma-requests = <64>;
224				#dma-cells = <2>;
225
226				ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
227					   <&edma_tptc2 0>;
228
229				ti,edma-memcpy-channels = <58 59>;
230			};
231		};
232
233		target-module@49800000 {
234			compatible = "ti,sysc-omap4", "ti,sysc";
235			reg = <0x49800000 0x4>,
236			      <0x49800010 0x4>;
237			reg-names = "rev", "sysc";
238			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
239			ti,sysc-midle = <SYSC_IDLE_FORCE>;
240			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
241					<SYSC_IDLE_SMART>;
242			clocks = <&l3_clkctrl AM4_L3_TPTC0_CLKCTRL 0>;
243			clock-names = "fck";
244			#address-cells = <1>;
245			#size-cells = <1>;
246			ranges = <0x0 0x49800000 0x100000>;
247
248			edma_tptc0: dma@0 {
249				compatible = "ti,edma3-tptc";
250				reg = <0 0x100000>;
251				interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
252				interrupt-names = "edma3_tcerrint";
253			};
254		};
255
256		target-module@49900000 {
257			compatible = "ti,sysc-omap4", "ti,sysc";
258			reg = <0x49900000 0x4>,
259			      <0x49900010 0x4>;
260			reg-names = "rev", "sysc";
261			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
262			ti,sysc-midle = <SYSC_IDLE_FORCE>;
263			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
264					<SYSC_IDLE_SMART>;
265			clocks = <&l3_clkctrl AM4_L3_TPTC1_CLKCTRL 0>;
266			clock-names = "fck";
267			#address-cells = <1>;
268			#size-cells = <1>;
269			ranges = <0x0 0x49900000 0x100000>;
270
271			edma_tptc1: dma@0 {
272				compatible = "ti,edma3-tptc";
273				reg = <0 0x100000>;
274				interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
275				interrupt-names = "edma3_tcerrint";
276			};
277		};
278
279		target-module@49a00000 {
280			compatible = "ti,sysc-omap4", "ti,sysc";
281			reg = <0x49a00000 0x4>,
282			      <0x49a00010 0x4>;
283			reg-names = "rev", "sysc";
284			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
285			ti,sysc-midle = <SYSC_IDLE_FORCE>;
286			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
287					<SYSC_IDLE_SMART>;
288			clocks = <&l3_clkctrl AM4_L3_TPTC2_CLKCTRL 0>;
289			clock-names = "fck";
290			#address-cells = <1>;
291			#size-cells = <1>;
292			ranges = <0x0 0x49a00000 0x100000>;
293
294			edma_tptc2: dma@0 {
295				compatible = "ti,edma3-tptc";
296				reg = <0 0x100000>;
297				interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
298				interrupt-names = "edma3_tcerrint";
299			};
300		};
301
302		target-module@47810000 {
303			compatible = "ti,sysc-omap2", "ti,sysc";
304			reg = <0x478102fc 0x4>,
305			      <0x47810110 0x4>,
306			      <0x47810114 0x4>;
307			reg-names = "rev", "sysc", "syss";
308			ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
309					 SYSC_OMAP2_ENAWAKEUP |
310					 SYSC_OMAP2_SOFTRESET |
311					 SYSC_OMAP2_AUTOIDLE)>;
312			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
313					<SYSC_IDLE_NO>,
314					<SYSC_IDLE_SMART>;
315			ti,syss-mask = <1>;
316			clocks = <&l3s_clkctrl AM4_L3S_MMC3_CLKCTRL 0>;
317			clock-names = "fck";
318			#address-cells = <1>;
319			#size-cells = <1>;
320			ranges = <0x0 0x47810000 0x1000>;
321
322			mmc3: mmc@0 {
323				compatible = "ti,am437-sdhci";
324				ti,needs-special-reset;
325				interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
326				reg = <0x0 0x1000>;
327				status = "disabled";
328			};
329		};
330
331		sham_target: target-module@53100000 {
332			compatible = "ti,sysc-omap3-sham", "ti,sysc";
333			reg = <0x53100100 0x4>,
334			      <0x53100110 0x4>,
335			      <0x53100114 0x4>;
336			reg-names = "rev", "sysc", "syss";
337			ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
338					 SYSC_OMAP2_AUTOIDLE)>;
339			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
340					<SYSC_IDLE_NO>,
341					<SYSC_IDLE_SMART>;
342			ti,syss-mask = <1>;
343			/* Domains (P, C): per_pwrdm, l3_clkdm */
344			clocks = <&l3_clkctrl AM4_L3_SHAM_CLKCTRL 0>;
345			clock-names = "fck";
346			#address-cells = <1>;
347			#size-cells = <1>;
348			ranges = <0x0 0x53100000 0x1000>;
349
350			sham: sham@0 {
351				compatible = "ti,omap5-sham";
352				reg = <0 0x300>;
353				dmas = <&edma 36 0>;
354				dma-names = "rx";
355				interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
356			};
357		};
358
359		aes_target: target-module@53501000 {
360			compatible = "ti,sysc-omap2", "ti,sysc";
361			reg = <0x53501080 0x4>,
362			      <0x53501084 0x4>,
363			      <0x53501088 0x4>;
364			reg-names = "rev", "sysc", "syss";
365			ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
366					 SYSC_OMAP2_AUTOIDLE)>;
367			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
368					<SYSC_IDLE_NO>,
369					<SYSC_IDLE_SMART>,
370					<SYSC_IDLE_SMART_WKUP>;
371			ti,syss-mask = <1>;
372			/* Domains (P, C): per_pwrdm, l3_clkdm */
373			clocks = <&l3_clkctrl AM4_L3_AES_CLKCTRL 0>;
374			clock-names = "fck";
375			#address-cells = <1>;
376			#size-cells = <1>;
377			ranges = <0x0 0x53501000 0x1000>;
378
379			aes: aes@0 {
380				compatible = "ti,omap4-aes";
381				reg = <0 0xa0>;
382				interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
383				dmas = <&edma 6 0>,
384				      <&edma 5 0>;
385				dma-names = "tx", "rx";
386			};
387		};
388
389		des_target: target-module@53701000 {
390			compatible = "ti,sysc-omap2", "ti,sysc";
391			reg = <0x53701030 0x4>,
392			      <0x53701034 0x4>,
393			      <0x53701038 0x4>;
394			reg-names = "rev", "sysc", "syss";
395			ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
396					 SYSC_OMAP2_AUTOIDLE)>;
397			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
398					<SYSC_IDLE_NO>,
399					<SYSC_IDLE_SMART>,
400					<SYSC_IDLE_SMART_WKUP>;
401			ti,syss-mask = <1>;
402			/* Domains (P, C): per_pwrdm, l3_clkdm */
403			clocks = <&l3_clkctrl AM4_L3_DES_CLKCTRL 0>;
404			clock-names = "fck";
405			#address-cells = <1>;
406			#size-cells = <1>;
407			ranges = <0 0x53701000 0x1000>;
408
409			des: des@0 {
410				compatible = "ti,omap4-des";
411				reg = <0 0xa0>;
412				interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
413				dmas = <&edma 34 0>,
414				       <&edma 33 0>;
415				dma-names = "tx", "rx";
416			};
417		};
418
419		pruss_tm: target-module@54400000 {
420			compatible = "ti,sysc-pruss", "ti,sysc";
421			reg = <0x54426000 0x4>,
422			      <0x54426004 0x4>;
423			reg-names = "rev", "sysc";
424			ti,sysc-mask = <(SYSC_PRUSS_STANDBY_INIT |
425					 SYSC_PRUSS_SUB_MWAIT)>;
426			ti,sysc-midle = <SYSC_IDLE_FORCE>,
427					<SYSC_IDLE_NO>,
428					<SYSC_IDLE_SMART>;
429			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
430					<SYSC_IDLE_NO>,
431					<SYSC_IDLE_SMART>;
432			clocks = <&pruss_ocp_clkctrl AM4_PRUSS_OCP_PRUSS_CLKCTRL 0>;
433			clock-names = "fck";
434			resets = <&prm_per 1>;
435			reset-names = "rstctrl";
436			#address-cells = <1>;
437			#size-cells = <1>;
438			ranges = <0x0 0x54400000 0x80000>;
439
440			pruss1: pruss@0 {
441				compatible = "ti,am4376-pruss1";
442				reg = <0x0 0x40000>;
443				#address-cells = <1>;
444				#size-cells = <1>;
445				ranges;
446
447				pruss1_mem: memories@0 {
448					reg = <0x0 0x2000>,
449					      <0x2000 0x2000>,
450					      <0x10000 0x8000>;
451					reg-names = "dram0", "dram1",
452						    "shrdram2";
453				};
454
455				pruss1_cfg: cfg@26000 {
456					compatible = "ti,pruss-cfg", "syscon";
457					reg = <0x26000 0x2000>;
458					#address-cells = <1>;
459					#size-cells = <1>;
460					ranges = <0x0 0x26000 0x2000>;
461
462					clocks {
463						#address-cells = <1>;
464						#size-cells = <0>;
465
466						pruss1_iepclk_mux: iepclk-mux@30 {
467							reg = <0x30>;
468							#clock-cells = <0>;
469							clocks = <&sysclk_div>,     /* icss_iep_gclk */
470								 <&pruss_ocp_gclk>; /* icss_ocp_gclk */
471						};
472					};
473				};
474
475				pruss1_mii_rt: mii-rt@32000 {
476					compatible = "ti,pruss-mii", "syscon";
477					reg = <0x32000 0x58>;
478				};
479
480				pruss1_intc: interrupt-controller@20000 {
481					compatible = "ti,pruss-intc";
482					reg = <0x20000 0x2000>;
483					interrupt-controller;
484					#interrupt-cells = <3>;
485					interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
486						     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
487						     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
488						     <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
489						     <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
490						     <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
491						     <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
492					interrupt-names = "host_intr0", "host_intr1",
493							  "host_intr2", "host_intr3",
494							  "host_intr4",
495							  "host_intr6", "host_intr7";
496					ti,irqs-reserved = /bits/ 8 <0x20>; /* BIT(5) */
497				};
498
499				pru1_0: pru@34000 {
500					compatible = "ti,am4376-pru";
501					reg = <0x34000 0x3000>,
502					      <0x22000 0x400>,
503					      <0x22400 0x100>;
504					reg-names = "iram", "control", "debug";
505					firmware-name = "am437x-pru1_0-fw";
506				};
507
508				pru1_1: pru@38000 {
509					compatible = "ti,am4376-pru";
510					reg = <0x38000 0x3000>,
511					      <0x24000 0x400>,
512					      <0x24400 0x100>;
513					reg-names = "iram", "control", "debug";
514					firmware-name = "am437x-pru1_1-fw";
515				};
516
517				pruss1_mdio: mdio@32400 {
518					compatible = "ti,davinci_mdio";
519					reg = <0x32400 0x90>;
520					clocks = <&dpll_core_m4_ck>;
521					clock-names = "fck";
522					bus_freq = <1000000>;
523					#address-cells = <1>;
524					#size-cells = <0>;
525				};
526			};
527
528			pruss0: pruss@40000 {
529				compatible = "ti,am4376-pruss0";
530				reg = <0x40000 0x40000>;
531				#address-cells = <1>;
532				#size-cells = <1>;
533				ranges;
534
535				pruss0_mem: memories@40000 {
536					reg = <0x40000 0x1000>,
537					      <0x42000 0x1000>;
538					reg-names = "dram0", "dram1";
539				};
540
541				pruss0_cfg: cfg@66000 {
542					compatible = "ti,pruss-cfg", "syscon";
543					reg = <0x66000 0x2000>;
544					#address-cells = <1>;
545					#size-cells = <1>;
546					ranges = <0x0 0x66000 0x2000>;
547
548					clocks {
549						#address-cells = <1>;
550						#size-cells = <0>;
551
552						pruss0_iepclk_mux: iepclk-mux@30 {
553							reg = <0x30>;
554							#clock-cells = <0>;
555							clocks = <&sysclk_div>,     /* icss_iep_gclk */
556								 <&pruss_ocp_gclk>; /* icss_ocp_gclk */
557						};
558					};
559				};
560
561				pruss0_mii_rt: mii-rt@72000 {
562					compatible = "ti,pruss-mii", "syscon";
563					reg = <0x72000 0x58>;
564					status = "disabled";
565				};
566
567				pruss0_intc: interrupt-controller@60000 {
568					compatible = "ti,pruss-intc";
569					reg = <0x60000 0x2000>;
570					interrupt-controller;
571					#interrupt-cells = <3>;
572					interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
573						     <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
574						     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
575						     <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
576						     <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
577						     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
578						     <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
579					interrupt-names = "host_intr0", "host_intr1",
580							  "host_intr2", "host_intr3",
581							  "host_intr4",
582							  "host_intr6", "host_intr7";
583					ti,irqs-reserved = /bits/ 8 <0x20>; /* BIT(5) */
584				};
585
586				pru0_0: pru@74000 {
587					compatible = "ti,am4376-pru";
588					reg = <0x74000 0x1000>,
589					      <0x62000 0x400>,
590					      <0x62400 0x100>;
591					reg-names = "iram", "control", "debug";
592					firmware-name = "am437x-pru0_0-fw";
593				};
594
595				pru0_1: pru@78000 {
596					compatible = "ti,am4376-pru";
597					reg = <0x78000 0x1000>,
598					      <0x64000 0x400>,
599					      <0x64400 0x100>;
600					reg-names = "iram", "control", "debug";
601					firmware-name = "am437x-pru0_1-fw";
602				};
603			};
604		};
605
606		target-module@50000000 {
607			compatible = "ti,sysc-omap2", "ti,sysc";
608			reg = <0x50000000 4>,
609			      <0x50000010 4>,
610			      <0x50000014 4>;
611			reg-names = "rev", "sysc", "syss";
612			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
613					<SYSC_IDLE_NO>,
614					<SYSC_IDLE_SMART>;
615			ti,syss-mask = <1>;
616			clocks = <&l3s_clkctrl AM4_L3S_GPMC_CLKCTRL 0>;
617			clock-names = "fck";
618			#address-cells = <1>;
619			#size-cells = <1>;
620			ranges = <0x50000000 0x50000000 0x00001000>, /* regs */
621				 <0x00000000 0x00000000 0x40000000>; /* data */
622
623			gpmc: gpmc@50000000 {
624				compatible = "ti,am3352-gpmc";
625				dmas = <&edma 52 0>;
626				dma-names = "rxtx";
627				clocks = <&l3s_gclk>;
628				clock-names = "fck";
629				reg = <0x50000000 0x2000>;
630				interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
631				gpmc,num-cs = <7>;
632				gpmc,num-waitpins = <2>;
633				#address-cells = <2>;
634				#size-cells = <1>;
635				interrupt-controller;
636				#interrupt-cells = <2>;
637				gpio-controller;
638				#gpio-cells = <2>;
639				status = "disabled";
640			};
641		};
642
643		target-module@47900000 {
644			compatible = "ti,sysc-omap4", "ti,sysc";
645			reg = <0x47900000 0x4>,
646			      <0x47900010 0x4>;
647			reg-names = "rev", "sysc";
648			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
649					<SYSC_IDLE_NO>,
650					<SYSC_IDLE_SMART>,
651					<SYSC_IDLE_SMART_WKUP>;
652			clocks = <&l3s_clkctrl AM4_L3S_QSPI_CLKCTRL 0>;
653			clock-names = "fck";
654			#address-cells = <1>;
655			#size-cells = <1>;
656			ranges = <0x0 0x47900000 0x1000>,
657				 <0x30000000 0x30000000 0x4000000>;
658
659			qspi: spi@0 {
660				compatible = "ti,am4372-qspi";
661				reg = <0 0x100>,
662				      <0x30000000 0x4000000>;
663				reg-names = "qspi_base", "qspi_mmap";
664				clocks = <&dpll_per_m2_div4_ck>;
665				clock-names = "fck";
666				#address-cells = <1>;
667				#size-cells = <0>;
668				interrupts = <0 138 0x4>;
669				num-cs = <4>;
670			};
671		};
672
673		target-module@40300000 {
674			compatible = "ti,sysc-omap4-simple", "ti,sysc";
675			clocks = <&l3_clkctrl AM4_L3_OCMCRAM_CLKCTRL 0>;
676			clock-names = "fck";
677			ti,no-idle;
678			#address-cells = <1>;
679			#size-cells = <1>;
680			ranges = <0 0x40300000 0x40000>;
681
682			ocmcram: sram@0 {
683				compatible = "mmio-sram";
684				reg = <0 0x40000>; /* 256k */
685				ranges = <0 0 0x40000>;
686				#address-cells = <1>;
687				#size-cells = <1>;
688
689				pm_sram_code: pm-code-sram@0 {
690					compatible = "ti,sram";
691					reg = <0x0 0x1000>;
692					protect-exec;
693				};
694
695				pm_sram_data: pm-data-sram@1000 {
696					compatible = "ti,sram";
697					reg = <0x1000 0x1000>;
698					pool;
699				};
700			};
701		};
702
703		target-module@56000000 {
704			compatible = "ti,sysc-omap4", "ti,sysc";
705			reg = <0x5600fe00 0x4>,
706			      <0x5600fe10 0x4>;
707			reg-names = "rev", "sysc";
708			ti,sysc-midle = <SYSC_IDLE_FORCE>,
709					<SYSC_IDLE_NO>,
710					<SYSC_IDLE_SMART>;
711			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
712					<SYSC_IDLE_NO>,
713					<SYSC_IDLE_SMART>;
714			clocks = <&gfx_l3_clkctrl AM4_GFX_L3_GFX_CLKCTRL 0>;
715			clock-names = "fck";
716			power-domains = <&prm_gfx>;
717			resets = <&prm_gfx 0>;
718			reset-names = "rstctrl";
719			#address-cells = <1>;
720			#size-cells = <1>;
721			ranges = <0 0x56000000 0x1000000>;
722
723			gpu@0 {
724				compatible = "ti,omap3630-gpu", "img,powervr-sgx530";
725				reg = <0x0 0x10000>; /* 64kB */
726				interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
727			};
728		};
729	};
730};
731
732#include "am437x-l4.dtsi"
733#include "am43xx-clocks.dtsi"
734
735&prcm {
736	prm_mpu: prm@300 {
737		compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
738		reg = <0x300 0x100>;
739		#power-domain-cells = <0>;
740	};
741
742	prm_gfx: prm@400 {
743		compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
744		reg = <0x400 0x100>;
745		#power-domain-cells = <0>;
746		#reset-cells = <1>;
747	};
748
749	prm_rtc: prm@500 {
750		compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
751		reg = <0x500 0x100>;
752		#power-domain-cells = <0>;
753	};
754
755	prm_tamper: prm@600 {
756		compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
757		reg = <0x600 0x100>;
758		#power-domain-cells = <0>;
759	};
760
761	prm_cefuse: prm@700 {
762		compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
763		reg = <0x700 0x100>;
764		#power-domain-cells = <0>;
765	};
766
767	prm_per: prm@800 {
768		compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
769		reg = <0x800 0x100>;
770		#reset-cells = <1>;
771		#power-domain-cells = <0>;
772	};
773
774	prm_wkup: prm@2000 {
775		compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
776		reg = <0x2000 0x100>;
777		#reset-cells = <1>;
778		#power-domain-cells = <0>;
779	};
780
781	prm_device: prm@4000 {
782		compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
783		reg = <0x4000 0x100>;
784		#reset-cells = <1>;
785	};
786};
787
788/* Preferred always-on timer for clocksource */
789&timer1_target {
790	ti,no-reset-on-init;
791	ti,no-idle;
792	clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_TIMER1_CLKCTRL 0>,
793		 <&l4_wkup_clkctrl AM4_L4_WKUP_L4_WKUP_CLKCTRL 0>;
794	clock-names = "fck", "ick";
795	timer@0 {
796		assigned-clocks = <&timer1_fck>;
797		assigned-clock-parents = <&sys_clkin_ck>;
798	};
799};
800
801/* Preferred timer for clockevent */
802&timer2_target {
803	ti,no-reset-on-init;
804	ti,no-idle;
805	clocks = <&l4ls_clkctrl AM4_L4LS_TIMER2_CLKCTRL 0>,
806		 <&l4ls_clkctrl AM4_L4LS_L4_LS_CLKCTRL 0>;
807	clock-names = "fck", "ick";
808	timer@0 {
809		assigned-clocks = <&timer2_fck>;
810		assigned-clock-parents = <&sys_clkin_ck>;
811	};
812};
813