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/freebsd/sys/contrib/device-tree/src/arm/arm/
H A Dvexpress-v2p-ca5s.dts16 arm,hbi = <0x225>;
17 arm,vexpress,site = <0xf>;
36 #size-cells = <0>;
38 cpu@0 {
41 reg = <0>;
55 reg = <0x80000000 0x40000000>;
63 /* Chipselect 2 is physically at 0x18000000 */
67 reg = <0x18000000 0x00800000>;
74 reg = <0x2a110000 0x1000>;
75 interrupts = <0 85 4>;
[all …]
/freebsd/sys/dev/bhnd/bcma/
H A Dbcma_dmp.h47 (((_value) & _flag) != 0)
54 #define BCMA_OOB_BUSCONFIG 0x020
55 #define BCMA_OOB_STATUSA 0x100
56 #define BCMA_OOB_STATUSB 0x104
57 #define BCMA_OOB_STATUSC 0x108
58 #define BCMA_OOB_STATUSD 0x10c
59 #define BCMA_OOB_ENABLEA0 0x200
60 #define BCMA_OOB_ENABLEA1 0x204
61 #define BCMA_OOB_ENABLEA2 0x208
62 #define BCMA_OOB_ENABLEA3 0x20c
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimxrt1050-pinfunc.h10 #define IMX_PAD_SION 0x40000000
17 #define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0
18 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0
19 #define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1
20 #define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0
21 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0
22 #define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0
24 #define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0
25 #define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0
26 #define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1
[all …]
H A Dimxrt1170-pinfunc.h10 #define IMX_PAD_SION 0x40000000
17 #define IOMUXC_GPIO_LPSR_00_FLEXCAN3_TX 0x000 0x040 0x0 0x0 0x0
18 #define IOMUXC_GPIO_LPSR_00_MIC_CLK 0x000 0x040 0x0 0x1 0x0
19 #define IOMUXC_GPIO_LPSR_00_MQS_RIGHT 0x000 0x040 0x0 0x2 0x0
20 #define IOMUXC_GPIO_LPSR_00_ARM_CM4_EVENTO 0x000 0x040 0x0 0x3 0x0
21 #define IOMUXC_GPIO_LPSR_00_GPIO_MUX6_IO00 0x000 0x040 0x0 0x5 0x0
22 #define IOMUXC_GPIO_LPSR_00_LPUART12_TXD 0x000 0x040 0x0B0 0x6 0x0
23 #define IOMUXC_GPIO_LPSR_00_SAI4_MCLK 0x000 0x040 0x0C8 0x7 0x0
24 #define IOMUXC_GPIO_LPSR_00_GPIO12_IO00 0x000 0x040 0x0 0xA 0x0
26 #define IOMUXC_GPIO_LPSR_01_FLEXCAN3_RX 0x004 0x044 0x080 0x0 0x0
[all …]
H A Dimx35-pinfunc.h13 #define MX35_PAD_CAPTURE__GPT_CAPIN1 0x004 0x328 0x000 0x0 0x0
14 #define MX35_PAD_CAPTURE__GPT_CMPOUT2 0x004 0x328 0x000 0x1 0x0
15 #define MX35_PAD_CAPTURE__CSPI2_SS1 0x004 0x328 0x7f4 0x2 0x0
16 #define MX35_PAD_CAPTURE__EPIT1_EPITO 0x004 0x328 0x000 0x3 0x0
17 #define MX35_PAD_CAPTURE__CCM_CLK32K 0x004 0x328 0x7d0 0x4 0x0
18 #define MX35_PAD_CAPTURE__GPIO1_4 0x004 0x328 0x850 0x5 0x0
19 #define MX35_PAD_COMPARE__GPT_CMPOUT1 0x008 0x32c 0x000 0x0 0x0
20 #define MX35_PAD_COMPARE__GPT_CAPIN2 0x008 0x32c 0x000 0x1 0x0
21 #define MX35_PAD_COMPARE__GPT_CMPOUT3 0x008 0x32c 0x000 0x2 0x0
22 #define MX35_PAD_COMPARE__EPIT2_EPITO 0x008 0x32c 0x000 0x3 0x0
[all …]
H A Dimx50-pinfunc.h13 #define MX50_PAD_KEY_COL0__KPP_COL_0 0x020 0x2cc 0x000 0x0 0x0
14 #define MX50_PAD_KEY_COL0__GPIO4_0 0x020 0x2cc 0x000 0x1 0x0
15 #define MX50_PAD_KEY_COL0__EIM_NANDF_CLE 0x020 0x2cc 0x000 0x2 0x0
16 #define MX50_PAD_KEY_COL0__CTI_TRIGIN7 0x020 0x2cc 0x000 0x6 0x0
17 #define MX50_PAD_KEY_COL0__USBPHY1_TXREADY 0x020 0x2cc 0x000 0x7 0x0
18 #define MX50_PAD_KEY_ROW0__KPP_ROW_0 0x024 0x2d0 0x000 0x0 0x0
19 #define MX50_PAD_KEY_ROW0__GPIO4_1 0x024 0x2d0 0x000 0x1 0x0
20 #define MX50_PAD_KEY_ROW0__EIM_NANDF_ALE 0x024 0x2d0 0x000 0x2 0x0
21 #define MX50_PAD_KEY_ROW0__CTI_TRIGIN_ACK7 0x024 0x2d0 0x000 0x6 0x0
22 #define MX50_PAD_KEY_ROW0__USBPHY1_RXVALID 0x024 0x2d0 0x000 0x7 0x0
[all …]
H A Dimx53-pinfunc.h13 #define MX53_PAD_GPIO_19__KPP_COL_5 0x020 0x348 0x840 0x0 0x0
14 #define MX53_PAD_GPIO_19__GPIO4_5 0x020 0x348 0x000 0x1 0x0
15 #define MX53_PAD_GPIO_19__CCM_CLKO 0x020 0x348 0x000 0x2 0x0
16 #define MX53_PAD_GPIO_19__SPDIF_OUT1 0x020 0x348 0x000 0x3 0x0
17 #define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 0x020 0x348 0x000 0x4 0x0
18 #define MX53_PAD_GPIO_19__ECSPI1_RDY 0x020 0x348 0x000 0x5 0x0
19 #define MX53_PAD_GPIO_19__FEC_TDATA_3 0x020 0x348 0x000 0x6 0x0
20 #define MX53_PAD_GPIO_19__SRC_INT_BOOT 0x020 0x348 0x000 0x7 0x0
21 #define MX53_PAD_KEY_COL0__KPP_COL_0 0x024 0x34c 0x000 0x0 0x0
22 #define MX53_PAD_KEY_COL0__GPIO4_6 0x024 0x34c 0x000 0x1 0x0
[all …]
H A Dimx6dl-pinfunc.h13 #define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x04c 0x360 0x000 0x0 0x0
14 #define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x04c 0x360 0x000 0x1 0x0
15 #define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x04c 0x360 0x7f8 0x2 0x0
16 #define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x04c 0x360 0x000 0x3 0x0
17 #define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x04c 0x360 0x8fc 0x3 0x0
18 #define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x04c 0x360 0x000 0x5 0x0
19 #define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x04c 0x360 0x000 0x7 0x0
20 #define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x050 0x364 0x000 0x0 0x0
21 #define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 0x050 0x364 0x000 0x1 0x0
22 #define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x050 0x364 0x800 0x2 0x0
[all …]
/freebsd/sys/contrib/device-tree/include/dt-bindings/reset/
H A Dhisi,hi6220-resets.h9 #define PERIPH_RSTDIS0_MMC0 0x000
10 #define PERIPH_RSTDIS0_MMC1 0x001
11 #define PERIPH_RSTDIS0_MMC2 0x002
12 #define PERIPH_RSTDIS0_NANDC 0x003
13 #define PERIPH_RSTDIS0_USBOTG_BUS 0x004
14 #define PERIPH_RSTDIS0_POR_PICOPHY 0x005
15 #define PERIPH_RSTDIS0_USBOTG 0x006
16 #define PERIPH_RSTDIS0_USBOTG_32K 0x007
17 #define PERIPH_RSTDIS1_HIFI 0x100
18 #define PERIPH_RSTDIS1_DIGACODEC 0x105
[all …]
/freebsd/sys/contrib/device-tree/Bindings/arm/ux500/
H A Dboards.txt51 reg = <0x80150000 0x2000>;
59 reg = <0xa0411000 0x1000>,
60 <0xa0410100 0x100>;
65 reg = <0xa0410000 0x100>;
70 reg = <0xa0410600 0x20>;
71 interrupts = <1 13 0x304>; /* IRQ level high per-CPU */
79 #clock-cells = <0>;
/freebsd/sys/contrib/device-tree/src/arm/qcom/
H A Dqcom-msm8960.dtsi20 #size-cells = <0>;
21 interrupts = <GIC_PPI 14 0x304>;
23 cpu@0 {
27 reg = <0>;
52 reg = <0x80000000 0>;
57 interrupts = <GIC_PPI 10 0x304>;
64 #clock-cells = <0>;
71 #clock-cells = <0>;
78 #clock-cells = <0>;
103 reg = <0x02000000 0x1000>,
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8mp-pinfunc.h13 #define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x014 0x274 0x000 0x0 0x0
14 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0
15 #define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0
16 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x014 0x274 0x000 0x6 0x0
17 #define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x018 0x278 0x000 0x0 0x0
18 #define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x0
19 #define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0
20 #define MX8MP_IOMUXC_GPIO1_IO01__CCM_EXT_CLK2 0x018 0x278 0x000 0x6 0x0
21 #define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02 0x01C 0x27C 0x000 0x0 0x0
22 #define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0
[all …]
H A Dimx8mn-pinfunc.h14 …ne MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x020 0x25C 0x000 0x0 0x0
15 …ne MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x020 0x25C 0x55C 0x1 0x3
16 …ne MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x024 0x260 0x000 0x0 0x0
17 …ne MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x024 0x260 0x56C 0x1 0x3
18 …ne MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0
19 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x000 0x1 0x0
20 …ne MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0
21 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0
22 …ne MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0
23 …ne MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0
[all …]
/freebsd/sys/dev/rtwn/rtl8192c/pci/
H A Dr92ce_reg.h31 #define R92C_PCIE_MIO_INTF 0x0e4
32 #define R92C_PCIE_MIO_INTD 0x0e8
34 #define R92C_PCIE_CTRL_REG 0x300
35 #define R92C_INT_MIG 0x304
36 #define R92C_BCNQ_DESA 0x308
37 #define R92C_HQ_DESA 0x310
38 #define R92C_MGQ_DESA 0x318
39 #define R92C_VOQ_DESA 0x320
40 #define R92C_VIQ_DESA 0x328
41 #define R92C_BEQ_DESA 0x330
[all …]
/freebsd/usr.sbin/cxgbetool/
H A Dreg_defs_t4vf.c7 { "SGE_KDOORBELL", 0x000, 0 },
10 { "PIDX", 0, 14 },
11 { "SGE_GTS", 0x004, 0 },
15 { "CIDXInc", 0, 12 },
17 { NULL, 0, 0 }
21 { "SGE_VF_KDOORBELL", 0x000, 0 },
25 { "PIDX", 0, 13 },
26 { "SGE_VF_GTS", 0x004, 0 },
30 { "CIDXInc", 0, 12 },
32 { NULL, 0, 0 }
[all …]
/freebsd/sys/contrib/device-tree/src/arm/vt8500/
H A Dwm8650.dtsi14 #address-cells = <0>;
15 #size-cells = <0>;
25 reg = <0x0 0x0>;
43 reg = <0xd8140000 0x10000>;
52 reg = <0xD8150000 0x10000>;
58 reg = <0xd8110000 0x10000>;
67 reg = <0xd8130000 0x1000>;
71 #size-cells = <0>;
74 #clock-cells = <0>;
80 #clock-cells = <0>;
[all …]
H A Dwm8505.dtsi14 #address-cells = <0>;
15 #size-cells = <0>;
25 reg = <0x0 0x0>;
47 reg = <0xd8140000 0x10000>;
56 reg = <0xD8150000 0x10000>;
62 reg = <0xd8110000 0x10000>;
71 reg = <0xd8130000 0x1000>;
74 #size-cells = <0>;
77 #clock-cells = <0>;
83 #clock-cells = <0>;
[all …]
H A Dwm8850.dtsi15 #size-cells = <0>;
17 cpu@0 {
20 reg = <0x0>;
26 reg = <0x0 0x0>;
46 reg = <0xd8140000 0x10000>;
55 reg = <0xD8150000 0x10000>;
61 reg = <0xd8110000 0x10000>;
70 reg = <0xd8130000 0x1000>;
74 #size-cells = <0>;
77 #clock-cells = <0>;
[all …]
H A Dwm8750.dtsi14 #address-cells = <0>;
15 #size-cells = <0>;
25 reg = <0x0 0x0>;
49 reg = <0xd8140000 0x10000>;
58 reg = <0xD8150000 0x10000>;
64 reg = <0xd8110000 0x10000>;
73 reg = <0xd8130000 0x1000>;
77 #size-cells = <0>;
80 #clock-cells = <0>;
86 #clock-cells = <0>;
[all …]
/freebsd/sys/arm64/coresight/
H A Dcoresight_tmc.h34 #define TMC_RSZ 0x004 /* RAM Size Register */
35 #define TMC_STS 0x00C /* Status Register */
41 #define STS_FULL (1 << 0)
42 #define TMC_RRD 0x010 /* RAM Read Data Register */
43 #define TMC_RRP 0x014 /* RAM Read Pointer Register */
44 #define TMC_RWP 0x018 /* RAM Write Pointer Register */
45 #define TMC_TRG 0x01C /* Trigger Counter Register */
46 #define TMC_CTL 0x020 /* Control Register */
47 #define CTL_TRACECAPTEN (1 << 0) /* Controls trace capture. */
48 #define TMC_RWD 0x024 /* RAM Write Data Register */
[all …]
/freebsd/usr.sbin/bhyve/amd64/
H A Dpci_gvt-d-opregion.h41 /// OpRegion Mailbox 0 Header structure. The OpRegion Header is used to
43 /// Offset 0x0, Size 0x100
46 int8_t sign[0x10]; ///< Offset 0x00 OpRegion Signature
47 uint32_t size; ///< Offset 0x10 OpRegion Size
48 uint32_t over; ///< Offset 0x14 OpRegion Structure Version
49 uint8_t sver[0x20]; ///< Offset 0x18 System BIOS Build Version
50 uint8_t vver[0x10]; ///< Offset 0x38 Video BIOS Build Version
51 uint8_t gver[0x10]; ///< Offset 0x48 Graphic Driver Build Version
52 uint32_t mbox; ///< Offset 0x58 Supported Mailboxes
53 uint32_t dmod; ///< Offset 0x5C Driver Model
[all …]
/freebsd/sys/contrib/device-tree/Bindings/arm/bcm/
H A Dbrcm,brcmstb.txt49 ranges = <0 0x00 0xf0000000 0x1000000>;
53 reg = <0x404000 0x51c>;
58 reg = <0x3e2400 0x5b4>;
64 reg = <0x452000 0x100>;
94 syscon-cpu = <&hif_cpubiuctrl 0x88 0x178>;
117 syscon = <&sun_top_ctrl 0x304 0x308>;
141 reg = <0x410000 0x400>;
170 "brcm,brcmstb-ddr-phy-v72.0"
182 - compatible : should contain "brcm,brcmstb-ddr-shimphy-v1.0"
199 memc@0 {
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/renesas/
H A Dhihope-common.dtsi56 gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
110 states = <3300000 1>, <1800000 0>;
115 #clock-cells = <0>;
119 x304_clk: x304-clock {
121 #clock-cells = <0>;
179 pinctrl-0 = <&hscif0_pins>;
197 reg = <0x6a>;
217 pinctrl-0 = <&scif_clk_pins>;
288 pinctrl-0 = <&scif2_pins>;
299 pinctrl-0 = <&sdhi0_pins>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/broadcom/
H A Dbcm7445.dtsi17 #size-cells = <0>;
19 cpu@0 {
23 reg = <0>;
50 reg = <0x00 0xffd01000 0x00 0x1000>,
51 <0x00 0xffd02000 0x00 0x2000>,
52 <0x00 0xffd04000 0x00 0x2000>,
53 <0x00 0xffd06000 0x00 0x2000>;
70 ranges = <0 0x00 0xf0000000 0x1000000>;
74 reg = <0x40ab00 0x20>;
84 reg = <0x404000 0x51c>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/remoteproc/
H A Dti,omap-remoteproc.yaml235 reg = <0x98000000 0x800000>;
244 ti,bootreg = <&scm_conf 0x304 0>;
250 clocks = <&tesla_clkctrl OMAP4_DSP_CLKCTRL 0>;
251 resets = <&prm_tesla 0>, <&prm_tesla 1>;
268 reg = <0 0x95800000 0
[all...]

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