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/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_4_2_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
H A Duvd_5_0_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
H A Duvd_6_0_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
H A Duvd_3_1_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x8
36 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3
[all …]
H A Dgfx_8_0_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
36 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
[all …]
H A Dgfx_8_1_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
36 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
[all …]
/linux/arch/arm/boot/dts/microchip/
H A Dat91-wb50n.dtsi21 reg = <0x20000000 0x4000000>;
51 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>;
53 slot@0 {
54 reg = <0>;
61 pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>;
63 atheros@0 {
66 reg = <0>;
76 dmas = <0>, <0>; /* Do not use DMA for dbgu */
84 pinctrl-0 = <&pinctrl_usart0 &pinctrl_usart0_rts_cts>;
92 pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts_cts>;
[all …]
/linux/arch/arm/boot/dts/nxp/vf/
H A Dvf610m4-colibri.dts22 reg = <0x8c000000 0x3000000>;
48 pinctrl-0 = <&pinctrl_uart2>;
55 VF610_PAD_PTD0__UART2_TX 0x21a2
56 VF610_PAD_PTD1__UART2_RX 0x21a1
57 VF610_PAD_PTD2__UART2_RTS 0x21a2
58 VF610_PAD_PTD3__UART2_CTS 0x21a1
/linux/drivers/accel/habanalabs/include/goya/asic_reg/
H A Dmme_masks.h23 #define MME_ARCH_STATUS_A_SHIFT 0
24 #define MME_ARCH_STATUS_A_MASK 0x1
26 #define MME_ARCH_STATUS_B_MASK 0x2
28 #define MME_ARCH_STATUS_CIN_MASK 0x4
30 #define MME_ARCH_STATUS_COUT_MASK 0x8
32 #define MME_ARCH_STATUS_TE_MASK 0x10
34 #define MME_ARCH_STATUS_LD_MASK 0x20
36 #define MME_ARCH_STATUS_ST_MASK 0x40
38 #define MME_ARCH_STATUS_SB_A_EMPTY_MASK 0x80
40 #define MME_ARCH_STATUS_SB_B_EMPTY_MASK 0x100
[all …]
/linux/arch/riscv/boot/dts/microchip/
H A Dmpfs-polarberry-fabric.dtsi7 #clock-cells = <0>;
13 #clock-cells = <0>;
19 #address-cells = <0x3>;
20 #interrupt-cells = <0x1>;
21 #size-cells = <0x2>;
23 reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43008000 0x0 0x2000>,
24 <0x0 0x4300a000 0x0 0x2000>;
26 bus-range = <0x0 0x7f>;
29 interrupt-map = <0 0 0 1 &pcie_intc 0>,
30 <0 0 0 2 &pcie_intc 1>,
[all …]
H A Dmpfs-m100pfs-fabric.dtsi7 #clock-cells = <0>;
13 #clock-cells = <0>;
19 #address-cells = <0x3>;
20 #interrupt-cells = <0x1>;
21 #size-cells = <0x2>;
23 reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43008000 0x0 0x2000>,
24 <0x0 0x4300a000 0x0 0x2000>;
26 bus-range = <0x0 0x7f>;
29 interrupt-map = <0 0 0 1 &pcie_intc 0>,
30 <0 0 0 2 &pcie_intc 1>,
[all …]
/linux/arch/arm/boot/dts/xilinx/
H A Dzynq-zc770-xm011.dts25 memory@0 {
27 reg = <0x0 0x40000000>;
32 #phy-cells = <0>;
46 reg = <0x52>;
53 #size-cells = <0>;
54 nand@0 {
55 reg = <0>;
60 partition@0 {
62 reg = <0x0 0x1000000>;
66 reg = <0x1000000 0x2000000>;
[all …]
/linux/drivers/accel/amdxdna/
H A Dnpu2_regs.c16 #define MPNPU_PUB_SEC_INTR 0x3010060
17 #define MPNPU_PUB_PWRMGMT_INTR 0x3010064
18 #define MPNPU_PUB_SCRATCH0 0x301006C
19 #define MPNPU_PUB_SCRATCH1 0x3010070
20 #define MPNPU_PUB_SCRATCH2 0x3010074
21 #define MPNPU_PUB_SCRATCH3 0x3010078
22 #define MPNPU_PUB_SCRATCH4 0x301007C
23 #define MPNPU_PUB_SCRATCH5 0x3010080
24 #define MPNPU_PUB_SCRATCH6 0x3010084
25 #define MPNPU_PUB_SCRATCH7 0x3010088
[all …]
H A Dnpu5_regs.c16 #define MPNPU_PUB_SEC_INTR 0x3010060
17 #define MPNPU_PUB_PWRMGMT_INTR 0x3010064
18 #define MPNPU_PUB_SCRATCH0 0x301006C
19 #define MPNPU_PUB_SCRATCH1 0x3010070
20 #define MPNPU_PUB_SCRATCH2 0x3010074
21 #define MPNPU_PUB_SCRATCH3 0x3010078
22 #define MPNPU_PUB_SCRATCH4 0x301007C
23 #define MPNPU_PUB_SCRATCH5 0x3010080
24 #define MPNPU_PUB_SCRATCH6 0x3010084
25 #define MPNPU_PUB_SCRATCH7 0x3010088
[all …]
H A Dnpu6_regs.c16 #define MPNPU_PUB_SEC_INTR 0x3010060
17 #define MPNPU_PUB_PWRMGMT_INTR 0x3010064
18 #define MPNPU_PUB_SCRATCH0 0x301006C
19 #define MPNPU_PUB_SCRATCH1 0x3010070
20 #define MPNPU_PUB_SCRATCH2 0x3010074
21 #define MPNPU_PUB_SCRATCH3 0x3010078
22 #define MPNPU_PUB_SCRATCH4 0x301007C
23 #define MPNPU_PUB_SCRATCH5 0x3010080
24 #define MPNPU_PUB_SCRATCH6 0x3010084
25 #define MPNPU_PUB_SCRATCH7 0x3010088
[all …]
H A Dnpu1_regs.c16 #define MPNPU_PUB_SEC_INTR 0x3010090
17 #define MPNPU_PUB_PWRMGMT_INTR 0x3010094
18 #define MPNPU_PUB_SCRATCH2 0x30100A0
19 #define MPNPU_PUB_SCRATCH3 0x30100A4
20 #define MPNPU_PUB_SCRATCH4 0x30100A8
21 #define MPNPU_PUB_SCRATCH5 0x30100AC
22 #define MPNPU_PUB_SCRATCH6 0x30100B0
23 #define MPNPU_PUB_SCRATCH7 0x30100B4
24 #define MPNPU_PUB_SCRATCH9 0x30100BC
26 #define MPNPU_SRAM_X2I_MAILBOX_0 0x30A0000
[all …]
H A Dnpu4_regs.c16 #define MPNPU_PUB_SEC_INTR 0x3010060
17 #define MPNPU_PUB_PWRMGMT_INTR 0x3010064
18 #define MPNPU_PUB_SCRATCH0 0x301006C
19 #define MPNPU_PUB_SCRATCH1 0x3010070
20 #define MPNPU_PUB_SCRATCH2 0x3010074
21 #define MPNPU_PUB_SCRATCH3 0x3010078
22 #define MPNPU_PUB_SCRATCH4 0x301007C
23 #define MPNPU_PUB_SCRATCH5 0x3010080
24 #define MPNPU_PUB_SCRATCH6 0x3010084
25 #define MPNPU_PUB_SCRATCH7 0x3010088
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_11_0_sh_mask.h27 #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON_MASK 0x1
28 #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON__SHIFT 0x0
29 #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE_MASK 0x1
30 #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE__SHIFT 0x0
31 #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA_MASK 0xffffff
32 #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA__SHIFT 0x0
33 #define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS_MASK 0x3000000
34 #define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS__SHIFT 0x18
35 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE_MASK 0x10000000
36 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE__SHIFT 0x1c
[all …]
H A Ddce_10_0_sh_mask.h27 #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON_MASK 0x1
28 #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON__SHIFT 0x0
29 #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE_MASK 0x1
30 #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE__SHIFT 0x0
31 #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA_MASK 0xffffff
32 #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA__SHIFT 0x0
33 #define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS_MASK 0x3000000
34 #define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS__SHIFT 0x18
35 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE_MASK 0x10000000
36 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE__SHIFT 0x1c
[all …]
H A Ddce_11_2_sh_mask.h27 #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON_MASK 0x1
28 #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON__SHIFT 0x0
29 #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE_MASK 0x1
30 #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE__SHIFT 0x0
31 #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA_MASK 0xffffff
32 #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA__SHIFT 0x0
33 #define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS_MASK 0x3000000
34 #define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS__SHIFT 0x18
35 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE_MASK 0x10000000
36 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE__SHIFT 0x1c
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/vce/
H A Dvce_3_0_sh_mask.h27 #define VCE_STATUS__JOB_BUSY_MASK 0x1
28 #define VCE_STATUS__JOB_BUSY__SHIFT 0x0
29 #define VCE_STATUS__VCPU_REPORT_MASK 0xfe
30 #define VCE_STATUS__VCPU_REPORT__SHIFT 0x1
31 #define VCE_STATUS__UENC_BUSY_MASK 0x100
32 #define VCE_STATUS__UENC_BUSY__SHIFT 0x8
33 #define VCE_STATUS__VCE_CONFIGURATION_MASK 0xc00000
34 #define VCE_STATUS__VCE_CONFIGURATION__SHIFT 0x16
35 #define VCE_STATUS__VCE_INSTANCE_ID_MASK 0x3000000
36 #define VCE_STATUS__VCE_INSTANCE_ID__SHIFT 0x18
[all …]
/linux/drivers/dma/sf-pdma/
H A Dsf-pdma.h13 * SiFive FU540-C000 v1.0
14 * https://static.dev.sifive.com/FU540-C000-v1.0.pdf
27 #define PDMA_BASE_ADDR 0x3000000
28 #define PDMA_CHAN_OFFSET 0x1000
31 #define PDMA_CTRL 0x000
32 #define PDMA_XFER_TYPE 0x004
33 #define PDMA_XFER_SIZE 0x008
34 #define PDMA_DST_ADDR 0x010
35 #define PDMA_SRC_ADDR 0x018
36 #define PDMA_ACT_TYPE 0x104 /* Read-only */
[all …]
/linux/arch/arm64/boot/dts/marvell/
H A Darmada-ap810-ap0.dtsi45 ranges = <0x0 0x0 0xe8000000 0x4000000>;
57 reg = <0x3000000 0x10000>, /* GICD */
58 <0x3060000 0x100000>, /* GICR */
59 <0x00c0000 0x2000>, /* GICC */
60 <0x00d0000 0x1000>, /* GICH */
61 <0x00e0000 0x2000>; /* GICV */
67 reg = <0x3040000 0x20000>;
73 reg = <0x400000 0x1000>,
74 <0x410000 0x1000>;
75 msi-parent = <&gic_its_ap0 0xa0>;
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/bif/
H A Dbif_5_0_sh_mask.h27 #define MM_INDEX__MM_OFFSET_MASK 0x7fffffff
28 #define MM_INDEX__MM_OFFSET__SHIFT 0x0
29 #define MM_INDEX__MM_APER_MASK 0x80000000
30 #define MM_INDEX__MM_APER__SHIFT 0x1f
31 #define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffff
32 #define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
33 #define MM_DATA__MM_DATA_MASK 0xffffffff
34 #define MM_DATA__MM_DATA__SHIFT 0x0
35 #define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK 0x2
36 #define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE__SHIFT 0x1
[all …]

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