Lines Matching +full:0 +full:x3000000
27 #size-cells = <0>;
29 cpu@0 {
32 reg = <0x0 0x0>;
39 reg = <0x0 0x1>;
46 reg = <0x0 0x2>;
53 reg = <0x0 0x3>;
60 reg = <0x0 0xf1001000 0x0 0x1000>, /* GICD */
61 <0x0 0xf1002000 0x0 0x100>; /* GICC */
62 #address-cells = <0>;
83 ranges = <0x0 0x0 0xf0000000 0x10000000>;
87 reg = <0x8a22000 0x1000>;
95 0xcc 12 0xcc 12 0 0 (ASSERT_CLEAR | DEASSERT_SET | STATUS_NONE)
96 0xcc 13 0xcc 13 0 0 (ASSERT_CLEAR | DEASSERT_SET | STATUS_NONE)
103 reg = <0x8000000 0x1000>;
111 reg = <0x8a20000 0x1000>;
114 ranges = <0x0 0x8a20000 0x1000>;
118 reg = <0x120 0x4>;
120 resets = <&crg 0xbc 4>;
122 #size-cells = <0>;
124 usb2_phy1_port0: phy@0 {
125 reg = <0>;
126 #phy-cells = <0>;
127 resets = <&crg 0xbc 8>;
132 #phy-cells = <0>;
133 resets = <&crg 0xbc 9>;
139 reg = <0x124 0x4>;
141 resets = <&crg 0xbc 6>;
143 #size-cells = <0>;
145 usb2_phy2_port0: phy@0 {
146 reg = <0>;
147 #phy-cells = <0>;
148 resets = <&crg 0xbc 10>;
154 reg = <0x850 0x8>;
157 resets = <&crg 0x188 4>;
165 reg = <0x858 0x8>;
168 resets = <&crg 0x188 12>;
171 hisilicon,mode-select-bits = <0x0008 11 (0x3 << 11)>;
177 reg = <0x8a21000 0x180>;
181 &range 0 8 2 /* GPIO 0 */
182 &range 8 1 0 /* GPIO 1 */
184 &range 13 1 0
186 &range 15 1 0
187 &range 16 5 0 /* GPIO 2 */
192 &range 87 1 0
194 &range 34 3 0
197 &range 41 5 0
201 &range 71 1 0
203 &range 78 1 0
207 &range 88 8 0 /* GPIO 12 */
217 reg = <0x8b00000 0x1000>;
226 reg = <0x8b02000 0x1000>;
235 reg = <0x8b10000 0x1000>;
237 #size-cells = <0>;
246 reg = <0x8b11000 0x1000>;
248 #size-cells = <0>;
257 reg = <0x8b12000 0x1000>;
259 #size-cells = <0>;
268 reg = <0x8b13000 0x1000>;
270 #size-cells = <0>;
279 reg = <0x8b14000 0x1000>;
281 #size-cells = <0>;
290 reg = <0x8b1a000 0x1000>;
293 cs-gpios = <&gpio7 1 0>;
297 #size-cells = <0>;
303 reg = <0x9820000 0x10000>;
308 resets = <&crg 0x9c 4>;
315 reg = <0x9830000 0x10000>;
322 resets = <&crg 0xa0 4>;
329 reg = <0x8b20000 0x1000>;
335 gpio-ranges = <&pmx0 0 0 8>;
343 reg = <0x8b21000 0x1000>;
350 &pmx0 0 8 1
363 reg = <0x8b22000 0x1000>;
369 gpio-ranges = <&pmx0 0 16 5 &pmx0 5 21 3>;
377 reg = <0x8b23000 0x1000>;
384 &pmx0 0 24 4
396 reg = <0x8b24000 0x1000>;
402 gpio-ranges = <&pmx0 0 30 4 &pmx0 4 34 3 &pmx0 7 37 1>;
410 reg = <0x8004000 0x1000>;
423 reg = <0x8b26000 0x1000>;
429 gpio-ranges = <&pmx0 0 38 3 &pmx0 0 41 5>;
437 reg = <0x8b27000 0x1000>;
443 gpio-ranges = <&pmx0 0 46 8>;
451 reg = <0x8b28000 0x1000>;
457 gpio-ranges = <&pmx0 0 54 8>;
465 reg = <0x8b29000 0x1000>;
471 gpio-ranges = <&pmx0 0 64 7 &pmx0 71 1>;
479 reg = <0x8b2a000 0x1000>;
485 gpio-ranges = <&pmx0 0 72 6 &pmx0 6 78 1 &pmx0 7 79 1>;
493 reg = <0x8b2b000 0x1000>;
499 gpio-ranges = <&pmx0 0 80 6 &pmx0 6 70 2>;
507 reg = <0x8b2c000 0x1000>;
513 gpio-ranges = <&pmx0 0 88 8>;
521 reg = <0x9840000 0x1000>,
522 <0x984300c 0x4>;
527 resets = <&crg 0xcc 8>,
528 <&crg 0xcc 10>,
529 <&gmacphyrst 0>;
536 reg = <0x9841000 0x1000>,
537 <0x9843010 0x4>;
542 resets = <&crg 0xcc 9>,
543 <&crg 0xcc 11>,
551 reg = <0x8001000 0x1000>;
559 reg = <0x9860000 0x1000>,
560 <0x0 0x2000>,
561 <0x2000000 0x01000000>;
566 bus-range = <0x00 0xff>;
568 ranges = <0x81000000 0x0 0x00000000 0x4f00000 0x0 0x100000>,
569 <0x82000000 0x0 0x3000000 0x3000000 0x0 0x01f00000>;
573 interrupt-map-mask = <0 0 0 0>;
574 interrupt-map = <0 0 0 0 &gic 0 131 IRQ_TYPE_LEVEL_HIGH>;
580 resets = <&crg 0x18c 6>, <&crg 0x18c 5>, <&crg 0x18c 4>;
589 reg = <0x9880000 0x10000>;
595 resets = <&crg 0xb8 12>;
604 reg = <0x9890000 0x10000>;
610 resets = <&crg 0xb8 12>,
611 <&crg 0xb8 16>,
612 <&crg 0xb8 13>;