Lines Matching +full:0 +full:x3000000
16 #size-cells = <0>;
18 cpu0: cpu@0 {
24 reg = <0>;
146 #clock-cells = <0>;
157 reg = <0x0 0x2010000 0x0 0x1000>;
169 reg = <0x0 0x2000000 0x0 0xC000>;
178 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
179 reg = <0x0 0xc000000 0x0 0x4000000>;
180 #address-cells = <0>;
193 reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>;
200 reg = <0x0 0x20000000 0x0 0x400>;
212 reg = <0x0 0x20100000 0x0 0x400>;
224 reg = <0x0 0x20102000 0x0 0x400>;
236 reg = <0x0 0x20104000 0x0 0x400>;
248 reg = <0x0 0x20106000 0x0 0x400>;
261 reg = <0x0 0x20008000 0x0 0x1000>;
272 #size-cells = <0>;
273 reg = <0x0 0x20108000 0x0 0x1000>;
284 #size-cells = <0>;
285 reg = <0x0 0x20109000 0x0 0x1000>;
296 #size-cells = <0>;
297 reg = <0x0 0x21000000 0x0 0x1000>;
307 reg = <0x0 0x2010a000 0x0 0x1000>;
309 #size-cells = <0>;
319 reg = <0x0 0x2010b000 0x0 0x1000>;
321 #size-cells = <0>;
331 reg = <0x0 0x20110000 0x0 0x2000>;
333 #size-cells = <0>;
344 reg = <0x0 0x20112000 0x0 0x2000>;
346 #size-cells = <0>;
357 reg = <0x0 0x20120000 0x0 0x1000>;
369 reg = <0x0 0x20121000 0x0 0x1000>;
381 reg = <0x0 0x20122000 0x0 0x1000>;
393 reg = <0x0 0x20124000 0x0 0x1000>;
403 reg = <0x0 0x20201000 0x0 0x1000>;
413 #address-cells = <0x3>;
414 #interrupt-cells = <0x1>;
415 #size-cells = <0x2>;
417 reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>;
419 bus-range = <0x0 0x7f>;
422 interrupt-map = <0 0 0 1 &pcie_intc 0>,
423 <0 0 0 2 &pcie_intc 1>,
424 <0 0 0 3 &pcie_intc 2>,
425 <0 0 0 4 &pcie_intc 3>;
426 interrupt-map-mask = <0 0 0 7>;
429 ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>;
432 microchip,axi-m-atr0 = <0x10 0x0>;
435 #address-cells = <0>;
443 reg = <0x0 0x37020000 0x0 0x1000>, <0x0 0x2000318C 0x0 0x40>;
452 mboxes = <&mbox 0>;