Lines Matching +full:0 +full:x3000000
30 pinctrl-0 = <&bl_pwm_default>;
37 pinctrl-0 = <&hall_int_active_state>;
53 #size-cells = <0>;
55 connector@0 {
57 reg = <0>;
63 #size-cells = <0>;
65 port@0 {
66 reg = <0>;
99 #size-cells = <0>;
100 port@0 {
101 reg = <0>;
130 reg = <0x0 0x85500000 0x0 0x200000>;
138 reg = <0x0 0x8bc00000 0x0 0x180000>;
143 reg = <0x0 0x8d800000 0x0 0x3000000>;
148 reg = <0x0 0x90800000 0x0 0x1c00000>;
153 reg = <0x0 0x98715000 0x0 0x2000>;
158 reg = <0x0 0x98900000 0x0 0x1400000>;
190 pinctrl-0 = <&usbprim_sbu_default>;
209 pinctrl-0 = <&usbsec_sbu_default>;
223 regulators-0 {
360 pinctrl-0 = <&i2c1_active>, <&i2c1_hid_active>;
367 reg = <0x10>;
368 hid-descr-addr = <0x1>;
377 pinctrl-0 = <&i2c7_active>, <&i2c7_hid_active>;
384 reg = <0x5>;
385 hid-descr-addr = <0x20>;
392 reg = <0x2c>;
393 hid-descr-addr = <0x20>;
408 data-lanes = <0 1>;
417 data-lanes = <0 1>;
422 data-lanes = <0 1 2 3>;
424 pinctrl-0 = <&edp_hpd_active>;
457 pinctrl-0 = <&pcie3_default_state>;
508 pinctrl-0 = <&uart13_state>;
650 gpio-reserved-ranges = <0 4>, <47 4>, <126 4>;