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12

/linux/arch/powerpc/boot/dts/fsl/
H A Dpq3-esdhc-0.dtsi2 * PQ3 eSDHC device tree stub [ controller @ offset 0x2e000 ]
37 reg = <0x2e000 0x1000>;
38 interrupts = <72 0x2 0 0>;
40 clock-frequency = <0>;
/linux/arch/arm64/boot/dts/realtek/
H A Drtd1619-mjolnir.dts17 reg = <0x2e000 0x7ffd2000>; /* boot ROM to 2 GiB */
/linux/arch/arm/boot/dts/ti/omap/
H A Domap5-l4-abe.dtsi1 &l4_abe { /* 0x40100000 */
3 reg = <0x40100000 0x400>,
4 <0x40100400 0x400>;
10 ranges = <0x00000000 0x40100000 0x100000>, /* segment 0 */
11 <0x49000000 0x49000000 0x100000>;
12 segment@0 { /* 0x40100000 */
18 <0x00000000 0x00000000 0x000400>, /* ap 0 */
19 <0x00000400 0x00000400 0x000400>, /* ap 1 */
20 <0x00022000 0x00022000 0x001000>, /* ap 2 */
21 <0x00023000 0x00023000 0x001000>, /* ap 3 */
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dmsm8953-motorola-potter.dts18 qcom,msm-id = <293 0>;
19 qcom,board-id = <0x46 0x83a0>;
28 reg = <0 0x90001000 0 (2220 * 1920 * 3)>;
51 pinctrl-0 = <&gpio_key_default>;
62 reg = <0x0 0x84300000 0x0 0x2000000>;
67 reg = <0x0 0x90001000 0x0 (1080 * 1920 * 3)>;
72 reg = <0x0 0xaefd2000 0x0 0x2e000>;
77 reg = <0x0 0xeefe4000 0x0 0x1c000>;
83 reg = <0x0 0xef000000 0x0 0x80000>;
84 console-size = <0x40000>;
[all …]
/linux/drivers/gpu/drm/msm/disp/dpu1/catalog/
H A Ddpu_9_1_sar2130p.h12 .max_mixer_blendstages = 0xb,
23 .base = 0, .len = 0x494,
25 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
32 .base = 0x15000, .len = 0x290,
36 .base = 0x16000, .len = 0x290,
40 .base = 0x17000, .len = 0x290,
44 .base = 0x18000, .len = 0x290,
48 .base = 0x19000, .len = 0x290,
52 .base = 0x1a000, .len = 0x290,
60 .base = 0x4000, .len = 0x344,
[all …]
H A Ddpu_9_0_sm8550.h12 .max_mixer_blendstages = 0xb,
23 .base = 0, .len = 0x494,
25 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
32 .base = 0x15000, .len = 0x290,
36 .base = 0x16000, .len = 0x290,
40 .base = 0x17000, .len = 0x290,
44 .base = 0x18000, .len = 0x290,
48 .base = 0x19000, .len = 0x290,
52 .base = 0x1a000, .len = 0x290,
60 .base = 0x4000, .len = 0x344,
[all …]
H A Ddpu_9_2_x1e80100.h11 .max_mixer_blendstages = 0xb,
22 .base = 0, .len = 0x494,
24 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
31 .base = 0x15000, .len = 0x290,
35 .base = 0x16000, .len = 0x290,
39 .base = 0x17000, .len = 0x290,
43 .base = 0x18000, .len = 0x290,
47 .base = 0x19000, .len = 0x290,
51 .base = 0x1a000, .len = 0x290,
59 .base = 0x4000, .len = 0x344,
[all …]
/linux/arch/powerpc/boot/dts/
H A Dmpc8377_wlan.dts28 #size-cells = <0>;
30 PowerPC,8377@0 {
32 reg = <0x0>;
37 timebase-frequency = <0>;
38 bus-frequency = <0>;
39 clock-frequency = <0>;
43 memory@0 {
45 reg = <0x00000000 0x20000000>; // 512MB at 0
52 reg = <0xe0005000 0x1000>;
53 interrupts = <77 0x8>;
[all …]
H A Dmpc8379_rdb.dts25 #size-cells = <0>;
27 PowerPC,8379@0 {
29 reg = <0x0>;
34 timebase-frequency = <0>;
35 bus-frequency = <0>;
36 clock-frequency = <0>;
40 memory@0 {
42 reg = <0x00000000 0x10000000>; // 256MB at 0
49 reg = <0xe0005000 0x1000>;
50 interrupts = <77 0x8>;
[all …]
H A Dmpc8377_rdb.dts27 #size-cells = <0>;
29 PowerPC,8377@0 {
31 reg = <0x0>;
36 timebase-frequency = <0>;
37 bus-frequency = <0>;
38 clock-frequency = <0>;
42 memory@0 {
44 reg = <0x00000000 0x10000000>; // 256MB at 0
51 reg = <0xe0005000 0x1000>;
52 interrupts = <77 0x8>;
[all …]
H A Dmpc8378_rdb.dts27 #size-cells = <0>;
29 PowerPC,8378@0 {
31 reg = <0x0>;
36 timebase-frequency = <0>;
37 bus-frequency = <0>;
38 clock-frequency = <0>;
42 memory@0 {
44 reg = <0x00000000 0x10000000>; // 256MB at 0
51 reg = <0xe0005000 0x1000>;
52 interrupts = <77 0x8>;
[all …]
/linux/drivers/gpu/drm/lima/
H A Dlima_device.c52 LIMA_IP_DESC(pmu, false, false, 0x02000, 0x02000, pmu, "pmu"),
53 LIMA_IP_DESC(l2_cache0, true, true, 0x01000, 0x10000, l2_cache, NULL),
54 LIMA_IP_DESC(l2_cache1, false, true, -1, 0x01000, l2_cache, NULL),
55 LIMA_IP_DESC(l2_cache2, false, false, -1, 0x11000, l2_cache, NULL),
56 LIMA_IP_DESC(gp, true, true, 0x00000, 0x00000, gp, "gp"),
57 LIMA_IP_DESC(pp0, true, true, 0x08000, 0x08000, pp, "pp0"),
58 LIMA_IP_DESC(pp1, false, false, 0x0A000, 0x0A000, pp, "pp1"),
59 LIMA_IP_DESC(pp2, false, false, 0x0C000, 0x0C000, pp, "pp2"),
60 LIMA_IP_DESC(pp3, false, false, 0x0E000, 0x0E000, pp, "pp3"),
61 LIMA_IP_DESC(pp4, false, false, -1, 0x28000, pp, "pp4"),
[all …]
/linux/drivers/interconnect/qcom/
H A Dkaanapali.c458 .port_offsets = { 0x14e000 },
459 .prio = 0,
461 .prio_fwd_disable = 0,
473 .port_offsets = { 0x145000 },
475 .urg_fwd = 0,
516 .port_offsets = { 0x13d000 },
518 .urg_fwd = 0,
531 .port_offsets = { 0x13f000 },
533 .urg_fwd = 0,
555 .port_offsets = { 0x31000, 0xb1000 },
[all …]
H A Dqcs615.c147 .port_offsets = { 0xc000 },
149 .urg_fwd = 0,
161 .port_offsets = { 0x17000 },
163 .urg_fwd = 0,
175 .port_offsets = { 0x10000 },
177 .urg_fwd = 0,
189 .port_offsets = { 0x12000 },
191 .urg_fwd = 0,
203 .port_offsets = { 0x4000 },
217 .port_offsets = { 0x5000 },
[all …]
H A Dsm6350.c155 .port_offsets = { 0xa000 },
157 .urg_fwd = 0,
171 .port_offsets = { 0x7000 },
173 .urg_fwd = 0,
187 .port_offsets = { 0x8000 },
189 .urg_fwd = 0,
211 .port_offsets = { 0xb000 },
213 .urg_fwd = 0,
227 .port_offsets = { 0x9000 },
229 .urg_fwd = 0,
[all …]
H A Dsm8650.c159 .port_offsets = { 0xc000 },
161 .urg_fwd = 0,
162 .prio_fwd_disable = 0,
176 .port_offsets = { 0xd000 },
178 .urg_fwd = 0,
179 .prio_fwd_disable = 0,
201 .port_offsets = { 0xe000 },
203 .urg_fwd = 0,
204 .prio_fwd_disable = 0,
218 .port_offsets = { 0xf000 },
[all …]
H A Dglymur.c652 .port_offsets = { 0x33000 },
653 .prio = 0,
655 .prio_fwd_disable = 0,
694 .port_offsets = { 0x933000 },
696 .urg_fwd = 0,
709 .port_offsets = { 0x51f000 },
711 .urg_fwd = 0,
724 .port_offsets = { 0x51f080 },
726 .urg_fwd = 0,
748 .port_offsets = { 0x934000 },
[all …]
/linux/drivers/clk/qcom/
H A Dgcc-sar2130p.c53 .offset = 0x0,
56 .enable_reg = 0x62018,
57 .enable_mask = BIT(0),
70 { 0x1, 2 },
75 .offset = 0x0,
92 .offset = 0x1000,
95 .enable_reg = 0x62018,
109 .offset = 0x4000,
112 .enable_reg = 0x62018,
126 .offset = 0x5000,
[all …]
H A Dgcc-ipq5424.c55 .offset = 0x20000,
58 .enable_reg = 0xb000,
59 .enable_mask = BIT(0),
83 .offset = 0x20000,
97 .offset = 0x21000,
100 .enable_reg = 0xb000,
112 { 0x1, 2 },
117 .offset = 0x21000,
132 .offset = 0x22000,
135 .enable_reg = 0xb000,
[all …]
H A Dgcc-msm8916.c45 .l_reg = 0x21004,
46 .m_reg = 0x21008,
47 .n_reg = 0x2100c,
48 .config_reg = 0x21010,
49 .mode_reg = 0x21000,
50 .status_reg = 0x2101c,
63 .enable_reg = 0x45000,
64 .enable_mask = BIT(0),
76 .l_reg = 0x20004,
77 .m_reg = 0x20008,
[all …]
H A Dgcc-msm8996.c49 .offset = 0x00000,
52 .enable_reg = 0x52000,
53 .enable_mask = BIT(0),
79 .offset = 0x00000,
94 .enable_reg = 0x5200c,
95 .enable_mask = BIT(0),
111 .enable_reg = 0x5200c,
126 .offset = 0x77000,
129 .enable_reg = 0x52000,
143 .offset = 0x77000,
[all …]
H A Dgcc-ipq5332.c53 .offset = 0x20000,
56 .enable_reg = 0xb000,
57 .enable_mask = BIT(0),
80 .offset = 0x20000,
93 .offset = 0x21000,
96 .enable_reg = 0xb000,
108 .offset = 0x21000,
121 .offset = 0x22000,
124 .enable_reg = 0xb000,
136 .offset = 0x22000,
[all …]
H A Dgcc-msm8998.c27 #define GCC_MMSS_MISC 0x0902C
28 #define GCC_GPU_MISC 0x71028
31 { 250000000, 2000000000, 0 },
36 .offset = 0x0,
41 .enable_reg = 0x52000,
42 .enable_mask = BIT(0),
55 .offset = 0x0,
68 .offset = 0x0,
81 .offset = 0x0,
94 .offset = 0x0,
[all …]
H A Dgcc-msm8939.c53 .l_reg = 0x21004,
54 .m_reg = 0x21008,
55 .n_reg = 0x2100c,
56 .config_reg = 0x21010,
57 .mode_reg = 0x21000,
58 .status_reg = 0x2101c,
71 .enable_reg = 0x45000,
72 .enable_mask = BIT(0),
84 .l_reg = 0x20004,
85 .m_reg = 0x20008,
[all …]
/linux/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_dump.h22 #define DRV_DUMP_XSTORM_WAITP_ADDRESS 0x2b8a80
23 #define DRV_DUMP_TSTORM_WAITP_ADDRESS 0x1b8a80
24 #define DRV_DUMP_USTORM_WAITP_ADDRESS 0x338a80
25 #define DRV_DUMP_CSTORM_WAITP_ADDRESS 0x238a80
45 #define BNX2X_DUMP_VERSION 0x61111111
65 static const u32 page_vals_e2[] = {0, 128};
68 {0x58000, 4608, DUMP_CHIP_E2, 0x30}
74 static const u32 page_vals_e3[] = {0, 128};
77 {0x58000, 4608, DUMP_CHIP_E3A0 | DUMP_CHIP_E3B0, 0x30}
81 { 0x2000, 1, 0x1f, 0xfff},
[all …]

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