Lines Matching +full:0 +full:x2e000
51 .offset = 0x0,
54 .enable_reg = 0x62018,
55 .enable_mask = BIT(0),
77 { 0x1, 2 },
82 .offset = 0x0,
99 .offset = 0x2000,
102 .enable_reg = 0x62018,
116 .offset = 0x3000,
119 .enable_reg = 0x62018,
142 .offset = 0x4000,
145 .enable_reg = 0x62018,
168 .offset = 0x9000,
171 .enable_reg = 0x62018,
185 { P_BI_TCXO, 0 },
197 { P_BI_TCXO, 0 },
211 { P_BI_TCXO, 0 },
221 { P_BI_TCXO, 0 },
229 { P_BI_TCXO, 0 },
245 { P_PCIE_1_PHY_AUX_CLK, 0 },
255 { P_BI_TCXO, 0 },
271 { P_UFS_PHY_RX_SYMBOL_0_CLK, 0 },
281 { P_UFS_PHY_RX_SYMBOL_1_CLK, 0 },
291 { P_UFS_PHY_TX_SYMBOL_0_CLK, 0 },
301 { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
311 .reg = 0x7b060,
325 .reg = 0x9d080,
326 .shift = 0,
340 .reg = 0x9d064,
354 .reg = 0x87060,
355 .shift = 0,
369 .reg = 0x870d0,
370 .shift = 0,
384 .reg = 0x87050,
385 .shift = 0,
399 .reg = 0x49068,
400 .shift = 0,
414 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
415 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
416 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
421 .cmd_rcgr = 0x74004,
437 .cmd_rcgr = 0x75004,
453 .cmd_rcgr = 0x76004,
469 F(19200000, P_BI_TCXO, 1, 0, 0),
474 .cmd_rcgr = 0x7b064,
490 F(19200000, P_BI_TCXO, 1, 0, 0),
491 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
496 .cmd_rcgr = 0x7b048,
497 .mnd_width = 0,
512 .cmd_rcgr = 0x9d068,
528 .cmd_rcgr = 0x9d04c,
529 .mnd_width = 0,
544 F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0),
549 .cmd_rcgr = 0x43010,
550 .mnd_width = 0,
567 F(19200000, P_BI_TCXO, 1, 0, 0),
572 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
575 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
588 .cmd_rcgr = 0x27014,
606 .cmd_rcgr = 0x27148,
624 .cmd_rcgr = 0x2727c,
642 .cmd_rcgr = 0x273b0,
660 .cmd_rcgr = 0x274e4,
672 F(19200000, P_BI_TCXO, 1, 0, 0),
675 F(37500000, P_GCC_GPLL0_OUT_EVEN, 8, 0, 0),
677 F(50000000, P_GCC_GPLL0_OUT_MAIN, 12, 0, 0),
690 .cmd_rcgr = 0x27618,
708 .cmd_rcgr = 0x2774c,
726 .cmd_rcgr = 0x27880,
738 F(19200000, P_BI_TCXO, 1, 0, 0),
743 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
746 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
750 F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
763 .cmd_rcgr = 0x28014,
781 .cmd_rcgr = 0x28148,
799 .cmd_rcgr = 0x2827c,
817 .cmd_rcgr = 0x283b0,
835 .cmd_rcgr = 0x284e4,
853 .cmd_rcgr = 0x28618,
871 .cmd_rcgr = 0x2874c,
889 .cmd_rcgr = 0x2e014,
907 .cmd_rcgr = 0x2e148,
925 .cmd_rcgr = 0x2e27c,
943 .cmd_rcgr = 0x2e3b0,
961 .cmd_rcgr = 0x2e4e4,
979 .cmd_rcgr = 0x2e618,
997 .cmd_rcgr = 0x2e74c,
1008 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
1009 F(37000000, P_GCC_GPLL9_OUT_MAIN, 16, 0, 0),
1010 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
1011 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
1012 F(148000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0),
1018 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
1019 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
1020 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
1021 F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0),
1026 .cmd_rcgr = 0x24014,
1043 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
1044 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
1049 .cmd_rcgr = 0x26014,
1065 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
1066 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1067 F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
1068 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
1069 F(600000000, P_GCC_GPLL0_OUT_MAIN, 1, 0, 0),
1070 F(806400000, P_SM8475_GCC_GPLL2_OUT_EVEN, 1, 0, 0),
1071 F(850000000, P_SM8475_GCC_GPLL2_OUT_EVEN, 1, 0, 0),
1084 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
1085 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1086 F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
1087 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
1092 .cmd_rcgr = 0x8702c,
1108 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1109 F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
1110 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
1111 F(600000000, P_GCC_GPLL0_OUT_MAIN, 1, 0, 0),
1112 F(806400000, P_SM8475_GCC_GPLL2_OUT_EVEN, 1, 0, 0),
1113 F(850000000, P_SM8475_GCC_GPLL2_OUT_EVEN, 1, 0, 0),
1126 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1127 F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
1128 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
1133 .cmd_rcgr = 0x87074,
1134 .mnd_width = 0,
1149 F(9600000, P_BI_TCXO, 2, 0, 0),
1150 F(19200000, P_BI_TCXO, 1, 0, 0),
1155 .cmd_rcgr = 0x870a8,
1156 .mnd_width = 0,
1179 .cmd_rcgr = 0x8708c,
1180 .mnd_width = 0,
1195 F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0),
1196 F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0),
1197 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
1198 F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0),
1203 .cmd_rcgr = 0x49028,
1219 .cmd_rcgr = 0x49040,
1220 .mnd_width = 0,
1235 .cmd_rcgr = 0x4906c,
1236 .mnd_width = 0,
1251 .reg = 0x49058,
1252 .shift = 0,
1266 .halt_reg = 0x7b08c,
1268 .hwcg_reg = 0x7b08c,
1271 .enable_reg = 0x62000,
1281 .halt_reg = 0x9d098,
1283 .hwcg_reg = 0x9d098,
1286 .enable_reg = 0x62000,
1296 .halt_reg = 0x870d4,
1298 .hwcg_reg = 0x870d4,
1301 .enable_reg = 0x870d4,
1302 .enable_mask = BIT(0),
1316 .halt_reg = 0x870d4,
1318 .hwcg_reg = 0x870d4,
1321 .enable_reg = 0x870d4,
1336 .halt_reg = 0x49088,
1338 .hwcg_reg = 0x49088,
1341 .enable_reg = 0x49088,
1342 .enable_mask = BIT(0),
1356 .halt_reg = 0x48004,
1358 .hwcg_reg = 0x48004,
1361 .enable_reg = 0x62000,
1371 .halt_reg = 0x36010,
1373 .hwcg_reg = 0x36010,
1376 .enable_reg = 0x36010,
1377 .enable_mask = BIT(0),
1386 .halt_reg = 0x36018,
1388 .hwcg_reg = 0x36018,
1391 .enable_reg = 0x36018,
1392 .enable_mask = BIT(0),
1401 .halt_reg = 0x20030,
1403 .hwcg_reg = 0x20030,
1406 .enable_reg = 0x62000,
1416 .halt_reg = 0x49084,
1418 .hwcg_reg = 0x49084,
1421 .enable_reg = 0x49084,
1422 .enable_mask = BIT(0),
1436 .halt_reg = 0x81154,
1438 .hwcg_reg = 0x81154,
1441 .enable_reg = 0x81154,
1442 .enable_mask = BIT(0),
1451 .halt_reg = 0x9d094,
1453 .hwcg_reg = 0x9d094,
1456 .enable_reg = 0x62000,
1466 .halt_reg = 0x3700c,
1468 .hwcg_reg = 0x3700c,
1471 .enable_reg = 0x3700c,
1472 .enable_mask = BIT(0),
1481 .halt_reg = 0x37014,
1483 .hwcg_reg = 0x37014,
1486 .enable_reg = 0x37014,
1487 .enable_mask = BIT(0),
1496 .halt_reg = 0x9c00c,
1499 .enable_reg = 0x9c00c,
1500 .enable_mask = BIT(0),
1509 .halt_reg = 0x74000,
1512 .enable_reg = 0x74000,
1513 .enable_mask = BIT(0),
1527 .halt_reg = 0x75000,
1530 .enable_reg = 0x75000,
1531 .enable_mask = BIT(0),
1545 .halt_reg = 0x76000,
1548 .enable_reg = 0x76000,
1549 .enable_mask = BIT(0),
1565 .enable_reg = 0x62000,
1582 .enable_reg = 0x62000,
1597 .halt_reg = 0x81010,
1599 .hwcg_reg = 0x81010,
1602 .enable_reg = 0x81010,
1603 .enable_mask = BIT(0),
1612 .halt_reg = 0x81018,
1615 .enable_reg = 0x81018,
1616 .enable_mask = BIT(0),
1625 .halt_reg = 0x7b034,
1628 .enable_reg = 0x62008,
1643 .halt_reg = 0x7b030,
1645 .hwcg_reg = 0x7b030,
1648 .enable_reg = 0x62008,
1658 .halt_reg = 0x9c004,
1661 .enable_reg = 0x9c004,
1662 .enable_mask = BIT(0),
1671 .halt_reg = 0x7b028,
1674 .enable_reg = 0x62008,
1684 .halt_reg = 0x7b044,
1687 .enable_reg = 0x62000,
1702 .halt_reg = 0x7b03c,
1705 .enable_reg = 0x62008,
1720 .halt_reg = 0x7b020,
1722 .hwcg_reg = 0x7b020,
1725 .enable_reg = 0x62008,
1726 .enable_mask = BIT(0),
1735 .halt_reg = 0x7b01c,
1738 .enable_reg = 0x62008,
1748 .halt_reg = 0x9d030,
1751 .enable_reg = 0x62000,
1766 .halt_reg = 0x9d02c,
1768 .hwcg_reg = 0x9d02c,
1771 .enable_reg = 0x62000,
1781 .halt_reg = 0x9c008,
1784 .enable_reg = 0x9c008,
1785 .enable_mask = BIT(0),
1794 .halt_reg = 0x9d024,
1797 .enable_reg = 0x62000,
1807 .halt_reg = 0x9d038,
1810 .enable_reg = 0x62000,
1825 .halt_reg = 0x9d048,
1828 .enable_reg = 0x62000,
1843 .halt_reg = 0x9d040,
1846 .enable_reg = 0x62000,
1861 .halt_reg = 0x9d01c,
1863 .hwcg_reg = 0x9d01c,
1866 .enable_reg = 0x62000,
1876 .halt_reg = 0x9d018,
1879 .enable_reg = 0x62000,
1889 .halt_reg = 0x4300c,
1892 .enable_reg = 0x4300c,
1893 .enable_mask = BIT(0),
1907 .halt_reg = 0x43004,
1909 .hwcg_reg = 0x43004,
1912 .enable_reg = 0x43004,
1913 .enable_mask = BIT(0),
1922 .halt_reg = 0x43008,
1925 .enable_reg = 0x43008,
1926 .enable_mask = BIT(0),
1935 .halt_reg = 0x36008,
1937 .hwcg_reg = 0x36008,
1940 .enable_reg = 0x36008,
1941 .enable_mask = BIT(0),
1950 .halt_reg = 0x3600c,
1952 .hwcg_reg = 0x3600c,
1955 .enable_reg = 0x3600c,
1956 .enable_mask = BIT(0),
1965 .halt_reg = 0x37008,
1967 .hwcg_reg = 0x37008,
1970 .enable_reg = 0x37008,
1971 .enable_mask = BIT(0),
1980 .halt_reg = 0x81008,
1982 .hwcg_reg = 0x81008,
1985 .enable_reg = 0x81008,
1986 .enable_mask = BIT(0),
1995 .halt_reg = 0x7b018,
1997 .hwcg_reg = 0x7b018,
2000 .enable_reg = 0x7b018,
2001 .enable_mask = BIT(0),
2010 .halt_reg = 0x42014,
2012 .hwcg_reg = 0x42014,
2015 .enable_reg = 0x42014,
2016 .enable_mask = BIT(0),
2025 .halt_reg = 0x42008,
2027 .hwcg_reg = 0x42008,
2030 .enable_reg = 0x42008,
2031 .enable_mask = BIT(0),
2040 .halt_reg = 0x42010,
2042 .hwcg_reg = 0x42010,
2045 .enable_reg = 0x42010,
2046 .enable_mask = BIT(0),
2055 .halt_reg = 0x4200c,
2057 .hwcg_reg = 0x4200c,
2060 .enable_reg = 0x4200c,
2061 .enable_mask = BIT(0),
2070 .halt_reg = 0x3300c,
2073 .enable_reg = 0x62008,
2083 .halt_reg = 0x33000,
2086 .enable_reg = 0x62008,
2096 .halt_reg = 0x2700c,
2099 .enable_reg = 0x62008,
2114 .halt_reg = 0x27140,
2117 .enable_reg = 0x62008,
2132 .halt_reg = 0x27274,
2135 .enable_reg = 0x62008,
2150 .halt_reg = 0x273a8,
2153 .enable_reg = 0x62008,
2168 .halt_reg = 0x274dc,
2171 .enable_reg = 0x62008,
2186 .halt_reg = 0x27610,
2189 .enable_reg = 0x62008,
2204 .halt_reg = 0x27744,
2207 .enable_reg = 0x62008,
2222 .halt_reg = 0x27878,
2225 .enable_reg = 0x62008,
2240 .halt_reg = 0x3314c,
2243 .enable_reg = 0x62008,
2253 .halt_reg = 0x33140,
2256 .enable_reg = 0x62008,
2266 .halt_reg = 0x2800c,
2269 .enable_reg = 0x62008,
2284 .halt_reg = 0x28140,
2287 .enable_reg = 0x62008,
2302 .halt_reg = 0x28274,
2305 .enable_reg = 0x62008,
2320 .halt_reg = 0x283a8,
2323 .enable_reg = 0x62008,
2338 .halt_reg = 0x284dc,
2341 .enable_reg = 0x62008,
2356 .halt_reg = 0x28610,
2359 .enable_reg = 0x62008,
2374 .halt_reg = 0x28744,
2377 .enable_reg = 0x62008,
2392 .halt_reg = 0x3328c,
2395 .enable_reg = 0x62010,
2405 .halt_reg = 0x33280,
2408 .enable_reg = 0x62010,
2409 .enable_mask = BIT(0),
2418 .halt_reg = 0x2e00c,
2421 .enable_reg = 0x62010,
2436 .halt_reg = 0x2e140,
2439 .enable_reg = 0x62010,
2454 .halt_reg = 0x2e274,
2457 .enable_reg = 0x62010,
2472 .halt_reg = 0x2e3a8,
2475 .enable_reg = 0x62010,
2490 .halt_reg = 0x2e4dc,
2493 .enable_reg = 0x62010,
2508 .halt_reg = 0x2e610,
2511 .enable_reg = 0x62010,
2526 .halt_reg = 0x2e744,
2529 .enable_reg = 0x62010,
2544 .halt_reg = 0x27004,
2546 .hwcg_reg = 0x27004,
2549 .enable_reg = 0x62008,
2559 .halt_reg = 0x27008,
2561 .hwcg_reg = 0x27008,
2564 .enable_reg = 0x62008,
2574 .halt_reg = 0x28004,
2576 .hwcg_reg = 0x28004,
2579 .enable_reg = 0x62008,
2589 .halt_reg = 0x28008,
2591 .hwcg_reg = 0x28008,
2594 .enable_reg = 0x62008,
2604 .halt_reg = 0x2e004,
2606 .hwcg_reg = 0x2e004,
2609 .enable_reg = 0x62010,
2619 .halt_reg = 0x2e008,
2621 .hwcg_reg = 0x2e008,
2624 .enable_reg = 0x62010,
2634 .halt_reg = 0x2400c,
2637 .enable_reg = 0x2400c,
2638 .enable_mask = BIT(0),
2647 .halt_reg = 0x24004,
2650 .enable_reg = 0x24004,
2651 .enable_mask = BIT(0),
2665 .halt_reg = 0x24010,
2667 .hwcg_reg = 0x24010,
2670 .enable_reg = 0x24010,
2671 .enable_mask = BIT(0),
2680 .halt_reg = 0x2600c,
2683 .enable_reg = 0x2600c,
2684 .enable_mask = BIT(0),
2693 .halt_reg = 0x26004,
2696 .enable_reg = 0x26004,
2697 .enable_mask = BIT(0),
2711 .halt_reg = 0x26010,
2713 .hwcg_reg = 0x26010,
2716 .enable_reg = 0x26010,
2717 .enable_mask = BIT(0),
2726 .halt_reg = 0x9c000,
2729 .enable_reg = 0x9c000,
2730 .enable_mask = BIT(0),
2739 .halt_reg = 0x87020,
2741 .hwcg_reg = 0x87020,
2744 .enable_reg = 0x87020,
2745 .enable_mask = BIT(0),
2754 .halt_reg = 0x87018,
2756 .hwcg_reg = 0x87018,
2759 .enable_reg = 0x87018,
2760 .enable_mask = BIT(0),
2774 .halt_reg = 0x87018,
2776 .hwcg_reg = 0x87018,
2779 .enable_reg = 0x87018,
2794 .halt_reg = 0x8706c,
2796 .hwcg_reg = 0x8706c,
2799 .enable_reg = 0x8706c,
2800 .enable_mask = BIT(0),
2814 .halt_reg = 0x8706c,
2816 .hwcg_reg = 0x8706c,
2819 .enable_reg = 0x8706c,
2834 .halt_reg = 0x870a4,
2836 .hwcg_reg = 0x870a4,
2839 .enable_reg = 0x870a4,
2840 .enable_mask = BIT(0),
2854 .halt_reg = 0x870a4,
2856 .hwcg_reg = 0x870a4,
2859 .enable_reg = 0x870a4,
2874 .halt_reg = 0x87028,
2877 .enable_reg = 0x87028,
2878 .enable_mask = BIT(0),
2892 .halt_reg = 0x870c0,
2895 .enable_reg = 0x870c0,
2896 .enable_mask = BIT(0),
2910 .halt_reg = 0x87024,
2913 .enable_reg = 0x87024,
2914 .enable_mask = BIT(0),
2928 .halt_reg = 0x87064,
2930 .hwcg_reg = 0x87064,
2933 .enable_reg = 0x87064,
2934 .enable_mask = BIT(0),
2948 .halt_reg = 0x87064,
2950 .hwcg_reg = 0x87064,
2953 .enable_reg = 0x87064,
2968 .halt_reg = 0x49018,
2971 .enable_reg = 0x49018,
2972 .enable_mask = BIT(0),
2986 .halt_reg = 0x49024,
2989 .enable_reg = 0x49024,
2990 .enable_mask = BIT(0),
3004 .halt_reg = 0x49020,
3007 .enable_reg = 0x49020,
3008 .enable_mask = BIT(0),
3017 .halt_reg = 0x9c010,
3020 .enable_reg = 0x9c010,
3021 .enable_mask = BIT(0),
3030 .halt_reg = 0x4905c,
3033 .enable_reg = 0x4905c,
3034 .enable_mask = BIT(0),
3048 .halt_reg = 0x49060,
3051 .enable_reg = 0x49060,
3052 .enable_mask = BIT(0),
3066 .halt_reg = 0x49064,
3068 .hwcg_reg = 0x49064,
3071 .enable_reg = 0x49064,
3072 .enable_mask = BIT(0),
3086 .halt_reg = 0x42018,
3088 .hwcg_reg = 0x42018,
3091 .enable_reg = 0x42018,
3092 .enable_mask = BIT(0),
3101 .halt_reg = 0x42020,
3103 .hwcg_reg = 0x42020,
3106 .enable_reg = 0x42020,
3107 .enable_mask = BIT(0),
3116 .gdscr = 0x7b004,
3124 .gdscr = 0x9d004,
3132 .gdscr = 0x87004,
3140 .gdscr = 0x49004,
3317 [GCC_CAMERA_BCR] = { 0x36000 },
3318 [GCC_DISPLAY_BCR] = { 0x37000 },
3319 [GCC_GPU_BCR] = { 0x81000 },
3320 [GCC_PCIE_0_BCR] = { 0x7b000 },
3321 [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x7c014 },
3322 [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x7c020 },
3323 [GCC_PCIE_0_PHY_BCR] = { 0x7c01c },
3324 [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x7c028 },
3325 [GCC_PCIE_1_BCR] = { 0x9d000 },
3326 [GCC_PCIE_1_LINK_DOWN_BCR] = { 0x9e014 },
3327 [GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x9e020 },
3328 [GCC_PCIE_1_PHY_BCR] = { 0x9e01c },
3329 [GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0x9e000 },
3330 [GCC_PCIE_PHY_BCR] = { 0x7f000 },
3331 [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x7f00c },
3332 [GCC_PCIE_PHY_COM_BCR] = { 0x7f010 },
3333 [GCC_PDM_BCR] = { 0x43000 },
3334 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x27000 },
3335 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x28000 },
3336 [GCC_QUPV3_WRAPPER_2_BCR] = { 0x2e000 },
3337 [GCC_QUSB2PHY_PRIM_BCR] = { 0x22000 },
3338 [GCC_QUSB2PHY_SEC_BCR] = { 0x22004 },
3339 [GCC_SDCC2_BCR] = { 0x24000 },
3340 [GCC_SDCC4_BCR] = { 0x26000 },
3341 [GCC_UFS_PHY_BCR] = { 0x87000 },
3342 [GCC_USB30_PRIM_BCR] = { 0x49000 },
3343 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x60008 },
3344 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x60014 },
3345 [GCC_USB3_PHY_PRIM_BCR] = { 0x60000 },
3346 [GCC_USB3_PHY_SEC_BCR] = { 0x6000c },
3347 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x60004 },
3348 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x60010 },
3349 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x7a000 },
3350 [GCC_VIDEO_AXI0_CLK_ARES] = { .reg = 0x42018, .bit = 2, .udelay = 1000 },
3351 [GCC_VIDEO_AXI1_CLK_ARES] = { .reg = 0x42020, .bit = 2, .udelay = 1000 },
3352 [GCC_VIDEO_BCR] = { 0x42000 },
3391 .max_register = 0x1f1030,
3463 qcom_branch_set_clk_en(regmap, 0x36004); /* GCC_CAMERA_AHB_CLK */ in gcc_sm8450_probe()
3464 qcom_branch_set_clk_en(regmap, 0x36020); /* GCC_CAMERA_XO_CLK */ in gcc_sm8450_probe()
3465 qcom_branch_set_clk_en(regmap, 0x37004); /* GCC_DISP_AHB_CLK */ in gcc_sm8450_probe()
3466 qcom_branch_set_clk_en(regmap, 0x3701c); /* GCC_DISP_XO_CLK */ in gcc_sm8450_probe()
3467 qcom_branch_set_clk_en(regmap, 0x81004); /* GCC_GPU_CFG_AHB_CLK */ in gcc_sm8450_probe()
3468 qcom_branch_set_clk_en(regmap, 0x42004); /* GCC_VIDEO_AHB_CLK */ in gcc_sm8450_probe()
3469 qcom_branch_set_clk_en(regmap, 0x42028); /* GCC_VIDEO_XO_CLK */ in gcc_sm8450_probe()