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/linux/drivers/net/ethernet/apm/xgene-v2/
H A Dmac.h14 #define MAC_CONFIG_1 0xa000
15 #define MAC_CONFIG_2 0xa004
16 #define MII_MGMT_CONFIG 0xa020
17 #define MII_MGMT_COMMAND 0xa024
18 #define MII_MGMT_ADDRESS 0xa028
19 #define MII_MGMT_CONTROL 0xa02c
20 #define MII_MGMT_STATUS 0xa030
21 #define MII_MGMT_INDICATORS 0xa034
22 #define INTERFACE_CONTROL 0xa038
23 #define STATION_ADDR0 0xa040
[all …]
/linux/arch/powerpc/boot/dts/
H A Da3m071.dts26 ranges = <0 0xf0000000 0x0000c000>;
27 reg = <0xf0000000 0x00000100>;
28 bus-frequency = <0>; /* From boot loader */
29 system-frequency = <0>; /* From boot loader */
41 reg = <0x2000 0x100>;
42 interrupts = <2 1 0>;
63 reg = <0x2c00 0x100>;
64 interrupts = <2 4 0>;
73 reg = <0x03>;
94 ranges = <0 0 0xfc000000 0x02000000
[all …]
H A Da4m072.dts27 ranges = <0 0xf0000000 0x0000c000>;
28 reg = <0xf0000000 0x00000100>;
29 bus-frequency = <0>; /* From boot loader */
30 system-frequency = <0>; /* From boot loader */
33 fsl,init-ext-48mhz-en = <0x0>;
34 fsl,init-fd-enable = <0x01>;
35 fsl,init-fd-counters = <0x3333>;
44 reg = <0x2000 0x100>;
45 interrupts = <2 1 0>;
50 reg = <0x2200 0x100>;
[all …]
H A Dlite5200.dts20 #size-cells = <0>;
22 PowerPC,5200@0 {
24 reg = <0>;
27 d-cache-size = <0x4000>; // L1, 16K
28 i-cache-size = <0x4000>; // L1, 16K
29 timebase-frequency = <0>; // from bootloader
30 bus-frequency = <0>; // from bootloader
31 clock-frequency = <0>; // from bootloader
35 memory@0 {
37 reg = <0x00000000 0x04000000>; // 64MB
[all …]
H A Dmpc5200b.dtsi21 #size-cells = <0>;
23 powerpc: PowerPC,5200@0 {
25 reg = <0>;
28 d-cache-size = <0x4000>; // L1, 16K
29 i-cache-size = <0x4000>; // L1, 16K
30 timebase-frequency = <0>; // from bootloader
31 bus-frequency = <0>; // from bootloader
32 clock-frequency = <0>; // from bootloader
36 memory: memory@0 {
38 reg = <0x00000000 0x04000000>; // 64MB
[all …]
/linux/drivers/clk/mediatek/
H A Dclk-mt8196-imp_iic_wrap.c19 .set_ofs = 0xe08,
20 .clr_ofs = 0xe04,
21 .sta_ofs = 0xe00,
35 GATE_IMP(CLK_IMPC_I2C11, "impc_i2c11", "i2c_p", 0),
47 GATE_IMP(CLK_IMPE_I2C5, "impe_i2c5", "i2c_east", 0),
56 .set_ofs = 0x0000,
57 .clr_ofs = 0x0004,
58 .sta_ofs = 0x2c00,
73 GATE_IMP(CLK_IMPN_I2C1, "impn_i2c1", "i2c_north", 0),
87 GATE_IMP(CLK_IMPW_I2C0, "impw_i2c0", "i2c_west", 0),
/linux/drivers/media/radio/si4713/
H A Dsi4713.h25 #define SI4713_PRODUCT_NUMBER 0x0D
41 #define SI4713_PWUP_FUNC_TX 0x02
42 #define SI4713_PWUP_FUNC_PATCH 0x0F
43 #define SI4713_PWUP_OPMOD_ANALOG 0x50
44 #define SI4713_PWUP_OPMOD_DIGITAL 0x0F
47 #define SI4713_CMD_POWER_UP 0x01
50 #define SI4713_CMD_GET_REV 0x10
53 #define SI4713_CMD_POWER_DOWN 0x11
57 #define SI4713_CMD_SET_PROPERTY 0x12
61 #define SI4713_CMD_GET_PROPERTY 0x13
[all …]
/linux/drivers/net/wireless/quantenna/qtnfmac/pcie/
H A Dpearl_pcie_regs.h8 #define PCIE_HDP_CTRL(base) ((base) + 0x2c00)
9 #define PCIE_HDP_AXI_CTRL(base) ((base) + 0x2c04)
10 #define PCIE_HDP_HOST_WR_DESC0(base) ((base) + 0x2c10)
11 #define PCIE_HDP_HOST_WR_DESC0_H(base) ((base) + 0x2c14)
12 #define PCIE_HDP_HOST_WR_DESC1(base) ((base) + 0x2c18)
13 #define PCIE_HDP_HOST_WR_DESC1_H(base) ((base) + 0x2c1c)
14 #define PCIE_HDP_HOST_WR_DESC2(base) ((base) + 0x2c20)
15 #define PCIE_HDP_HOST_WR_DESC2_H(base) ((base) + 0x2c24)
16 #define PCIE_HDP_HOST_WR_DESC3(base) ((base) + 0x2c28)
17 #define PCIE_HDP_HOST_WR_DESC4_H(base) ((base) + 0x2c2c)
[all …]
/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dst,stm32mp25-omm.yaml34 <chip-select> 0 <registers base address> <size>
110 default: 0
116 - 0: OCTOSPI1 chip select send to NCS1 OCTOSPI2 chip select send to NCS1
120 minimum: 0
122 default: 0
128 - 0: direct mode
132 minimum: 0
134 default: 0
137 ^spi@[0-9]:
163 reg = <0x40500000 0x400>, <0x60000000 0x10000000>;
[all …]
/linux/drivers/bus/
H A Domap_l3_smx.h14 #define L3_COMPONENT 0x000
15 #define L3_CORE 0x018
16 #define L3_AGENT_CONTROL 0x020
17 #define L3_AGENT_STATUS 0x028
18 #define L3_ERROR_LOG 0x058
23 #define L3_ERROR_LOG_ADDR 0x060
26 #define L3_SI_CONTROL 0x020
27 #define L3_SI_FLAG_STATUS_0 0x510
31 #define L3_STATUS_0_MPUIA_BRST (shift << 0)
95 #define L3_SI_FLAG_STATUS_1 0x530
[all …]
H A Domap_l3_noc.h16 #define CUSTOM_ERROR 0x2
17 #define STANDARD_ERROR 0x0
18 #define INBAND_ERROR 0x0
19 #define L3_APPLICATION_ERROR 0x0
20 #define L3_DEBUG_ERROR 0x1
23 #define L3_TARG_STDERRLOG_MAIN 0x48
24 #define L3_TARG_STDERRLOG_HDR 0x4c
25 #define L3_TARG_STDERRLOG_MSTADDR 0x50
26 #define L3_TARG_STDERRLOG_INFO 0x58
27 #define L3_TARG_STDERRLOG_SLVOFSLSB 0x5c
[all …]
/linux/drivers/clocksource/
H A Dasm9260_timer.c23 * 0x0 - plain read write mode
24 * 0x4 - set mode, OR logic.
25 * 0x8 - clr mode, XOR logic.
26 * 0xc - togle mode.
31 #define HW_IR 0x0000 /* RW. Interrupt */
36 #define BM_IR_MR0 BIT(0)
38 #define HW_TCR 0x0010 /* RW. Timer controller */
49 * 0 - counters are disabled */
53 #define BM_C0_EN BIT(0)
55 #define HW_DIR 0x0020 /* RW. Direction? */
[all …]
/linux/drivers/platform/x86/intel/telemetry/
H A Dpltdrv.c22 #define DRIVER_VERSION "1.0.0"
24 #define TELEM_TRC_VERBOSITY_MASK 0x3
26 #define TELEM_MIN_PERIOD(x) ((x) & 0x7F0000)
27 #define TELEM_MAX_PERIOD(x) ((x) & 0x7F000000)
29 #define TELEM_CLEAR_SAMPLE_PERIOD(x) ((x) &= ~0x7F)
31 #define TELEM_SAMPLING_DEFAULT_PERIOD 0xD
37 #define IOSS_TELEM 0xeb
38 #define IOSS_TELEM_EVENT_READ 0x0
39 #define IOSS_TELEM_EVENT_WRITE 0x1
40 #define IOSS_TELEM_INFO_READ 0x2
[all …]
/linux/drivers/media/usb/hdpvr/
H A Dhdpvr.h22 #define HD_PVR_VENDOR_ID 0x2040
23 #define HD_PVR_PRODUCT_ID 0x4900
24 #define HD_PVR_PRODUCT_ID1 0x4901
25 #define HD_PVR_PRODUCT_ID2 0x4902
26 #define HD_PVR_PRODUCT_ID4 0x4903
27 #define HD_PVR_PRODUCT_ID3 0x4982
33 #define HDPVR_FIRMWARE_VERSION 0x08
34 #define HDPVR_FIRMWARE_VERSION_AC3 0x0d
35 #define HDPVR_FIRMWARE_VERSION_0X12 0x12
36 #define HDPVR_FIRMWARE_VERSION_0X15 0x15
[all …]
/linux/drivers/cpufreq/
H A Dsun50i-cpufreq-nvmem.c22 #define NVMEM_MASK 0x7
25 #define SUN50I_A100_NVMEM_MASK 0xf
48 return 0; in sun50i_h6_efuse_xlate()
59 case 0b100: in sun50i_a100_efuse_xlate()
61 case 0b010: in sun50i_a100_efuse_xlate()
64 return 0; in sun50i_a100_efuse_xlate()
79 * returned speedbin index is 4 -> 0/2 -> 3 -> 1, from worst to best.
80 * 0 and 2 seem identical from the OPP tables' point of view.
85 u32 value = 0; in sun50i_h616_efuse_xlate()
87 switch (speedbin & 0xffff) { in sun50i_h616_efuse_xlate()
[all …]
/linux/drivers/scsi/fnic/
H A Dfnic_fdls.h65 * bits 0-8: oxid idx - allocated from poool
71 #define FNIC_FRAME_MASK 0xFE00
77 #define FNIC_FDLS_FABRIC_ABORT_ISSUED 0x1
78 #define FNIC_FDLS_FPMA_LEARNT 0x2
81 #define FNIC_FDLS_TPORT_IN_GPN_FT_LIST 0x1
82 #define FNIC_FDLS_TGT_ABORT_ISSUED 0x2
83 #define FNIC_FDLS_TPORT_SEND_ADISC 0x4
84 #define FNIC_FDLS_RETRY_FRAME 0x8
85 #define FNIC_FDLS_TPORT_BUSY 0x10
86 #define FNIC_FDLS_TPORT_TERMINATING 0x20
[all …]
/linux/drivers/net/wireless/broadcom/b43/
H A Dwa.c24 b43_phy_write(dev, B43_PHY_LNAHPFCTL, 0x1FF9); in b43_wa_initgains()
25 b43_phy_mask(dev, B43_PHY_LPFGAINCTL, 0xFF0F); in b43_wa_initgains()
27 b43_ofdmtab_write16(dev, B43_OFDMTAB_LPFGAIN, 0, 0x1FBF); in b43_wa_initgains()
28 b43_radio_write16(dev, 0x0002, 0x1FBF); in b43_wa_initgains()
30 b43_phy_write(dev, 0x0024, 0x4680); in b43_wa_initgains()
31 b43_phy_write(dev, 0x0020, 0x0003); in b43_wa_initgains()
32 b43_phy_write(dev, 0x001D, 0x0F40); in b43_wa_initgains()
33 b43_phy_write(dev, 0x001F, 0x1C00); in b43_wa_initgains()
35 b43_phy_maskset(dev, 0x002A, 0x00FF, 0x0400); in b43_wa_initgains()
37 b43_phy_maskset(dev, 0x002A, 0x00FF, 0x1A00); in b43_wa_initgains()
[all …]
/linux/arch/mips/include/asm/sn/sn0/
H A Dkldir.h28 * 0x2000000 (32M) +-----------------------------------------+
30 * 0x1F80000 (31.5M) +-----------------------------------------+
32 * 0x1C00000 (30M) +-----------------------------------------+
34 * 0x0800000 (28M) +-----------------------------------------+
36 * 0x1B00000 (27M) +-----------------------------------------+
38 * 0x1A00000 (26M) +-----------------------------------------+
40 * 0x1800000 (24M) +-----------------------------------------+
42 * 0x1600000 (22M) +-----------------------------------------+
48 * 0x190000 (2M--) +-----------------------------------------+
51 * 0x34000 (208K) +-----------------------------------------+
[all …]
/linux/drivers/media/usb/pwc/
H A Dpwc.h46 #define PWC_DEBUG_LEVEL_MODULE BIT(0)
74 } while (0)
86 #define PWC_TRACE(fmt, args...) do { } while(0)
87 #define PWC_DEBUG(level, fmt, args...) do { } while(0)
89 #define pwc_trace 0
97 #define FEATURE_MOTOR_PANTILT 0x0001
98 #define FEATURE_CODEC1 0x0002
99 #define FEATURE_CODEC2 0x0004
127 #define SET_LUM_CTL 0x01
128 #define GET_LUM_CTL 0x02
[all …]
/linux/arch/arm/boot/dts/synaptics/
H A Dberlin2.dtsi28 #size-cells = <0>;
31 cpu@0 {
35 reg = <0>;
68 #clock-cells = <0>;
78 ranges = <0 0xf7000000 0x1000000>;
82 reg = <0xab0000 0x200>;
91 reg = <0xab0800 0x200>;
100 reg = <0xab1000 0x200>;
104 pinctrl-0 = <&emmc_pmux>;
111 reg = <0xac0000 0x1000>;
[all …]
H A Dberlin2cd.dtsi27 #size-cells = <0>;
29 cpu: cpu@0 {
33 reg = <0>;
53 #clock-cells = <0>;
63 ranges = <0 0xf7000000 0x1000000>;
67 reg = <0xab0000 0x200>;
76 reg = <0xac0000 0x1000>;
83 reg = <0xad0000 0x100>;
88 reg = <0xad1000 0x1000>, <0xad0100 0x0100>;
95 reg = <0xad0200 0x20>;
[all …]
/linux/drivers/net/wireless/mediatek/mt7601u/
H A Dregs.h12 #define MT_ASIC_VERSION 0x0000
14 #define MT76XX_REV_E3 0x22
15 #define MT76XX_REV_E4 0x33
17 #define MT_CMB_CTRL 0x0020
21 #define MT_EFUSE_CTRL 0x0024
22 #define MT_EFUSE_CTRL_AOUT GENMASK(5, 0)
30 #define MT_EFUSE_DATA_BASE 0x0028
33 #define MT_COEXCFG0 0x0040
34 #define MT_COEXCFG0_COEX_EN BIT(0)
36 #define MT_WLAN_FUN_CTRL 0x0080
[all …]
/linux/drivers/net/ethernet/intel/ice/
H A Dice_ptp_consts.h14 .base_addr = 0x092000,
15 .step = 0x98,
18 .base_addr = 0x093000,
19 .step = 0x200,
22 .base_addr = 0x000000,
23 .step = 0x21000,
26 .base_addr = 0x085000,
27 .step = 0x1000,
30 .base_addr = 0x084000,
31 .step = 0x400,
[all …]
/linux/drivers/net/ethernet/cavium/liquidio/
H A Dcn66xx_regs.h26 #define CN6XXX_XPANSION_BAR 0x30
28 #define CN6XXX_MSI_CAP 0x50
29 #define CN6XXX_MSI_ADDR_LO 0x54
30 #define CN6XXX_MSI_ADDR_HI 0x58
31 #define CN6XXX_MSI_DATA 0x5C
33 #define CN6XXX_PCIE_CAP 0x70
34 #define CN6XXX_PCIE_DEVCAP 0x74
35 #define CN6XXX_PCIE_DEVCTL 0x78
36 #define CN6XXX_PCIE_LINKCAP 0x7C
37 #define CN6XXX_PCIE_LINKCTL 0x80
[all …]
/linux/drivers/gpu/drm/mgag200/
H A Dmgag200_reg.h24 #define MGAREG_DWGCTL 0x1c00
25 #define MGAREG_MACCESS 0x1c04
27 #define MGAREG_MCTLWTST 0x1c08
28 #define MGAREG_ZORG 0x1c0c
30 #define MGAREG_PAT0 0x1c10
31 #define MGAREG_PAT1 0x1c14
32 #define MGAREG_PLNWT 0x1c1c
34 #define MGAREG_BCOL 0x1c20
35 #define MGAREG_FCOL 0x1c24
37 #define MGAREG_SRC0 0x1c30
[all …]

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