Lines Matching +full:0 +full:x2c00
35 #define RT2661_HOST_CMD_CSR 0x0008
36 #define RT2661_MCU_CNTL_CSR 0x000c
37 #define RT2661_SOFT_RESET_CSR 0x0010
38 #define RT2661_MCU_INT_SOURCE_CSR 0x0014
39 #define RT2661_MCU_INT_MASK_CSR 0x0018
40 #define RT2661_PCI_USEC_CSR 0x001c
41 #define RT2661_H2M_MAILBOX_CSR 0x2100
42 #define RT2661_M2H_CMD_DONE_CSR 0x2104
43 #define RT2661_HW_BEACON_BASE0 0x2c00
44 #define RT2661_MAC_CSR0 0x3000
45 #define RT2661_MAC_CSR1 0x3004
46 #define RT2661_MAC_CSR2 0x3008
47 #define RT2661_MAC_CSR3 0x300c
48 #define RT2661_MAC_CSR4 0x3010
49 #define RT2661_MAC_CSR5 0x3014
50 #define RT2661_MAC_CSR6 0x3018
51 #define RT2661_MAC_CSR7 0x301c
52 #define RT2661_MAC_CSR8 0x3020
53 #define RT2661_MAC_CSR9 0x3024
54 #define RT2661_MAC_CSR10 0x3028
55 #define RT2661_MAC_CSR11 0x302c
56 #define RT2661_MAC_CSR12 0x3030
57 #define RT2661_MAC_CSR13 0x3034
58 #define RT2661_MAC_CSR14 0x3038
59 #define RT2661_MAC_CSR15 0x303c
60 #define RT2661_TXRX_CSR0 0x3040
61 #define RT2661_TXRX_CSR1 0x3044
62 #define RT2661_TXRX_CSR2 0x3048
63 #define RT2661_TXRX_CSR3 0x304c
64 #define RT2661_TXRX_CSR4 0x3050
65 #define RT2661_TXRX_CSR5 0x3054
66 #define RT2661_TXRX_CSR6 0x3058
67 #define RT2661_TXRX_CSR7 0x305c
68 #define RT2661_TXRX_CSR8 0x3060
69 #define RT2661_TXRX_CSR9 0x3064
70 #define RT2661_TXRX_CSR10 0x3068
71 #define RT2661_TXRX_CSR11 0x306c
72 #define RT2661_TXRX_CSR12 0x3070
73 #define RT2661_TXRX_CSR13 0x3074
74 #define RT2661_TXRX_CSR14 0x3078
75 #define RT2661_TXRX_CSR15 0x307c
76 #define RT2661_PHY_CSR0 0x3080
77 #define RT2661_PHY_CSR1 0x3084
78 #define RT2661_PHY_CSR2 0x3088
79 #define RT2661_PHY_CSR3 0x308c
80 #define RT2661_PHY_CSR4 0x3090
81 #define RT2661_PHY_CSR5 0x3094
82 #define RT2661_PHY_CSR6 0x3098
83 #define RT2661_PHY_CSR7 0x309c
84 #define RT2661_SEC_CSR0 0x30a0
85 #define RT2661_SEC_CSR1 0x30a4
86 #define RT2661_SEC_CSR2 0x30a8
87 #define RT2661_SEC_CSR3 0x30ac
88 #define RT2661_SEC_CSR4 0x30b0
89 #define RT2661_SEC_CSR5 0x30b4
90 #define RT2661_STA_CSR0 0x30c0
91 #define RT2661_STA_CSR1 0x30c4
92 #define RT2661_STA_CSR2 0x30c8
93 #define RT2661_STA_CSR3 0x30cc
94 #define RT2661_STA_CSR4 0x30d0
95 #define RT2661_AC0_BASE_CSR 0x3400
96 #define RT2661_AC1_BASE_CSR 0x3404
97 #define RT2661_AC2_BASE_CSR 0x3408
98 #define RT2661_AC3_BASE_CSR 0x340c
99 #define RT2661_MGT_BASE_CSR 0x3410
100 #define RT2661_TX_RING_CSR0 0x3418
101 #define RT2661_TX_RING_CSR1 0x341c
102 #define RT2661_AIFSN_CSR 0x3420
103 #define RT2661_CWMIN_CSR 0x3424
104 #define RT2661_CWMAX_CSR 0x3428
105 #define RT2661_TX_DMA_DST_CSR 0x342c
106 #define RT2661_TX_CNTL_CSR 0x3430
107 #define RT2661_LOAD_TX_RING_CSR 0x3434
108 #define RT2661_RX_BASE_CSR 0x3450
109 #define RT2661_RX_RING_CSR 0x3454
110 #define RT2661_RX_CNTL_CSR 0x3458
111 #define RT2661_PCI_CFG_CSR 0x3460
112 #define RT2661_INT_SOURCE_CSR 0x3468
113 #define RT2661_INT_MASK_CSR 0x346c
114 #define RT2661_E2PROM_CSR 0x3470
115 #define RT2661_AC_TXOP_CSR0 0x3474
116 #define RT2661_AC_TXOP_CSR1 0x3478
117 #define RT2661_TEST_MODE_CSR 0x3484
118 #define RT2661_IO_CNTL_CSR 0x3498
119 #define RT2661_MCU_CODE_BASE 0x4000
124 #define RT2661_MCU_CMD_SLEEP 0x30
125 #define RT2661_MCU_CMD_WAKEUP 0x31
126 #define RT2661_MCU_SET_LED 0x50
127 #define RT2661_MCU_SET_RSSI_LED 0x52
130 #define RT2661_MCU_SEL (1 << 0)
135 #define RT2661_MCU_CMD_DONE 0xff
141 #define RT2661_TOKEN_NO_INTR 0xff
168 #define RT2661_TSF_MODE(x) (((x) & 0x3) << 17)
186 #define RT2661_TX_STAT_VALID (1 << 0)
187 #define RT2661_TX_RESULT(v) (((v) >> 1) & 0x7)
188 #define RT2661_TX_RETRYCNT(v) (((v) >> 4) & 0xf)
189 #define RT2661_TX_QID(v) (((v) >> 8) & 0xf)
190 #define RT2661_TX_SUCCESS 0
197 #define RT2661_TX_DONE (1 << 0)
215 #define RT2661_TX_BUSY (1 << 0)
236 #define RT2661_PLCP_LENGEXT 0x80
249 #define RT2661_DEFAULT_TXPOWER 0
262 #define RT2661_RX_BUSY (1 << 0)
267 #define RT2661_RX_CIPHER_MASK 0x00000600
280 #define RAL_RF1 0
294 #define RT2661_SMART_MODE (1 << 0)
301 #define RT2661_EEPROM_MAC01 0x02
302 #define RT2661_EEPROM_MAC23 0x03
303 #define RT2661_EEPROM_MAC45 0x04
304 #define RT2661_EEPROM_ANTENNA 0x10
305 #define RT2661_EEPROM_CONFIG2 0x11
306 #define RT2661_EEPROM_BBP_BASE 0x13
307 #define RT2661_EEPROM_TXPOWER 0x23
308 #define RT2661_EEPROM_FREQ_OFFSET 0x2f
309 #define RT2661_EEPROM_RSSI_2GHZ_OFFSET 0x4d
310 #define RT2661_EEPROM_RSSI_5GHZ_OFFSET 0x4e
337 } while (/* CONSTCOND */0)
343 { RT2661_TXRX_CSR0, 0x0000b032 }, \
344 { RT2661_TXRX_CSR1, 0x9eb39eb3 }, \
345 { RT2661_TXRX_CSR2, 0x8a8b8c8d }, \
346 { RT2661_TXRX_CSR3, 0x00858687 }, \
347 { RT2661_TXRX_CSR7, 0x2e31353b }, \
348 { RT2661_TXRX_CSR8, 0x2a2a2a2c }, \
349 { RT2661_TXRX_CSR15, 0x0000000f }, \
350 { RT2661_MAC_CSR6, 0x00000fff }, \
351 { RT2661_MAC_CSR8, 0x016c030a }, \
352 { RT2661_MAC_CSR10, 0x00000718 }, \
353 { RT2661_MAC_CSR12, 0x00000004 }, \
354 { RT2661_MAC_CSR13, 0x0000e000 }, \
355 { RT2661_SEC_CSR0, 0x00000000 }, \
356 { RT2661_SEC_CSR1, 0x00000000 }, \
357 { RT2661_SEC_CSR5, 0x00000000 }, \
358 { RT2661_PHY_CSR1, 0x000023b0 }, \
359 { RT2661_PHY_CSR5, 0x060a100c }, \
360 { RT2661_PHY_CSR6, 0x00080606 }, \
361 { RT2661_PHY_CSR7, 0x00000a08 }, \
362 { RT2661_PCI_CFG_CSR, 0x3cca4808 }, \
363 { RT2661_AIFSN_CSR, 0x00002273 }, \
364 { RT2661_CWMIN_CSR, 0x00002344 }, \
365 { RT2661_CWMAX_CSR, 0x000034aa }, \
366 { RT2661_TEST_MODE_CSR, 0x00000200 }, \
367 { RT2661_M2H_CMD_DONE_CSR, 0xffffffff }
373 { 3, 0x00 }, \
374 { 15, 0x30 }, \
375 { 17, 0x20 }, \
376 { 21, 0xc8 }, \
377 { 22, 0x38 }, \
378 { 23, 0x06 }, \
379 { 24, 0xfe }, \
380 { 25, 0x0a }, \
381 { 26, 0x0d }, \
382 { 34, 0x12 }, \
383 { 37, 0x07 }, \
384 { 39, 0xf8 }, \
385 { 41, 0x60 }, \
386 { 53, 0x10 }, \
387 { 54, 0x18 }, \
388 { 60, 0x10 }, \
389 { 61, 0x04 }, \
390 { 62, 0x04 }, \
391 { 75, 0xfe }, \
392 { 86, 0xfe }, \
393 { 88, 0xfe }, \
394 { 90, 0x0f }, \
395 { 99, 0x00 }, \
396 { 102, 0x16 }, \
397 { 107, 0x04 }
403 { 1, 0x00b33, 0x011e1, 0x1a014, 0x30282 }, \
404 { 2, 0x00b33, 0x011e1, 0x1a014, 0x30287 }, \
405 { 3, 0x00b33, 0x011e2, 0x1a014, 0x30282 }, \
406 { 4, 0x00b33, 0x011e2, 0x1a014, 0x30287 }, \
407 { 5, 0x00b33, 0x011e3, 0x1a014, 0x30282 }, \
408 { 6, 0x00b33, 0x011e3, 0x1a014, 0x30287 }, \
409 { 7, 0x00b33, 0x011e4, 0x1a014, 0x30282 }, \
410 { 8, 0x00b33, 0x011e4, 0x1a014, 0x30287 }, \
411 { 9, 0x00b33, 0x011e5, 0x1a014, 0x30282 }, \
412 { 10, 0x00b33, 0x011e5, 0x1a014, 0x30287 }, \
413 { 11, 0x00b33, 0x011e6, 0x1a014, 0x30282 }, \
414 { 12, 0x00b33, 0x011e6, 0x1a014, 0x30287 }, \
415 { 13, 0x00b33, 0x011e7, 0x1a014, 0x30282 }, \
416 { 14, 0x00b33, 0x011e8, 0x1a014, 0x30284 }, \
418 { 36, 0x00b33, 0x01266, 0x26014, 0x30288 }, \
419 { 40, 0x00b33, 0x01268, 0x26014, 0x30280 }, \
420 { 44, 0x00b33, 0x01269, 0x26014, 0x30282 }, \
421 { 48, 0x00b33, 0x0126a, 0x26014, 0x30284 }, \
422 { 52, 0x00b33, 0x0126b, 0x26014, 0x30286 }, \
423 { 56, 0x00b33, 0x0126c, 0x26014, 0x30288 }, \
424 { 60, 0x00b33, 0x0126e, 0x26014, 0x30280 }, \
425 { 64, 0x00b33, 0x0126f, 0x26014, 0x30282 }, \
427 { 100, 0x00b33, 0x0128a, 0x2e014, 0x30280 }, \
428 { 104, 0x00b33, 0x0128b, 0x2e014, 0x30282 }, \
429 { 108, 0x00b33, 0x0128c, 0x2e014, 0x30284 }, \
430 { 112, 0x00b33, 0x0128d, 0x2e014, 0x30286 }, \
431 { 116, 0x00b33, 0x0128e, 0x2e014, 0x30288 }, \
432 { 120, 0x00b33, 0x012a0, 0x2e014, 0x30280 }, \
433 { 124, 0x00b33, 0x012a1, 0x2e014, 0x30282 }, \
434 { 128, 0x00b33, 0x012a2, 0x2e014, 0x30284 }, \
435 { 132, 0x00b33, 0x012a3, 0x2e014, 0x30286 }, \
436 { 136, 0x00b33, 0x012a4, 0x2e014, 0x30288 }, \
437 { 140, 0x00b33, 0x012a6, 0x2e014, 0x30280 }, \
439 { 149, 0x00b33, 0x012a8, 0x2e014, 0x30287 }, \
440 { 153, 0x00b33, 0x012a9, 0x2e014, 0x30289 }, \
441 { 157, 0x00b33, 0x012ab, 0x2e014, 0x30281 }, \
442 { 161, 0x00b33, 0x012ac, 0x2e014, 0x30283 }, \
443 { 165, 0x00b33, 0x012ad, 0x2e014, 0x30285 }
446 { 1, 0x00b33, 0x011e1, 0x1a014, 0x30282 }, \
447 { 2, 0x00b33, 0x011e1, 0x1a014, 0x30287 }, \
448 { 3, 0x00b33, 0x011e2, 0x1a014, 0x30282 }, \
449 { 4, 0x00b33, 0x011e2, 0x1a014, 0x30287 }, \
450 { 5, 0x00b33, 0x011e3, 0x1a014, 0x30282 }, \
451 { 6, 0x00b33, 0x011e3, 0x1a014, 0x30287 }, \
452 { 7, 0x00b33, 0x011e4, 0x1a014, 0x30282 }, \
453 { 8, 0x00b33, 0x011e4, 0x1a014, 0x30287 }, \
454 { 9, 0x00b33, 0x011e5, 0x1a014, 0x30282 }, \
455 { 10, 0x00b33, 0x011e5, 0x1a014, 0x30287 }, \
456 { 11, 0x00b33, 0x011e6, 0x1a014, 0x30282 }, \
457 { 12, 0x00b33, 0x011e6, 0x1a014, 0x30287 }, \
458 { 13, 0x00b33, 0x011e7, 0x1a014, 0x30282 }, \
459 { 14, 0x00b33, 0x011e8, 0x1a014, 0x30284 }, \
461 { 36, 0x00b35, 0x11206, 0x26014, 0x30280 }, \
462 { 40, 0x00b34, 0x111a0, 0x26014, 0x30280 }, \
463 { 44, 0x00b34, 0x111a1, 0x26014, 0x30286 }, \
464 { 48, 0x00b34, 0x111a3, 0x26014, 0x30282 }, \
465 { 52, 0x00b34, 0x111a4, 0x26014, 0x30288 }, \
466 { 56, 0x00b34, 0x111a6, 0x26014, 0x30284 }, \
467 { 60, 0x00b34, 0x111a8, 0x26014, 0x30280 }, \
468 { 64, 0x00b34, 0x111a9, 0x26014, 0x30286 }, \
470 { 100, 0x00b35, 0x11226, 0x2e014, 0x30280 }, \
471 { 104, 0x00b35, 0x11228, 0x2e014, 0x30280 }, \
472 { 108, 0x00b35, 0x1122a, 0x2e014, 0x30280 }, \
473 { 112, 0x00b35, 0x1122c, 0x2e014, 0x30280 }, \
474 { 116, 0x00b35, 0x1122e, 0x2e014, 0x30280 }, \
475 { 120, 0x00b34, 0x111c0, 0x2e014, 0x30280 }, \
476 { 124, 0x00b34, 0x111c1, 0x2e014, 0x30286 }, \
477 { 128, 0x00b34, 0x111c3, 0x2e014, 0x30282 }, \
478 { 132, 0x00b34, 0x111c4, 0x2e014, 0x30288 }, \
479 { 136, 0x00b34, 0x111c6, 0x2e014, 0x30284 }, \
480 { 140, 0x00b34, 0x111c8, 0x2e014, 0x30280 }, \
482 { 149, 0x00b34, 0x111cb, 0x2e014, 0x30286 }, \
483 { 153, 0x00b34, 0x111cd, 0x2e014, 0x30282 }, \
484 { 157, 0x00b35, 0x11242, 0x2e014, 0x30285 }, \
485 { 161, 0x00b35, 0x11244, 0x2e014, 0x30285 }, \
486 { 165, 0x00b35, 0x11246, 0x2e014, 0x30285 }