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/freebsd/sys/contrib/device-tree/src/powerpc/
H A Da3m071.dts26 ranges = <0 0xf0000000 0x0000c000>;
27 reg = <0xf0000000 0x00000100>;
28 bus-frequency = <0>; /* From boot loader */
29 system-frequency = <0>; /* From boot loader */
41 reg = <0x2000 0x100>;
42 interrupts = <2 1 0>;
63 reg = <0x2c00 0x100>;
64 interrupts = <2 4 0>;
73 reg = <0x03>;
94 ranges = <0 0 0xfc000000 0x02000000
[all …]
H A Da4m072.dts27 ranges = <0 0xf0000000 0x0000c000>;
28 reg = <0xf0000000 0x00000100>;
29 bus-frequency = <0>; /* From boot loader */
30 system-frequency = <0>; /* From boot loader */
33 fsl,init-ext-48mhz-en = <0x0>;
34 fsl,init-fd-enable = <0x01>;
35 fsl,init-fd-counters = <0x3333>;
44 reg = <0x2000 0x100>;
45 interrupts = <2 1 0>;
50 reg = <0x2200 0x100>;
[all …]
H A Dlite5200.dts20 #size-cells = <0>;
22 PowerPC,5200@0 {
24 reg = <0>;
27 d-cache-size = <0x4000>; // L1, 16K
28 i-cache-size = <0x4000>; // L1, 16K
29 timebase-frequency = <0>; // from bootloader
30 bus-frequency = <0>; // from bootloader
31 clock-frequency = <0>; // from bootloader
35 memory@0 {
37 reg = <0x00000000 0x04000000>; // 64MB
[all …]
H A Dmpc5200b.dtsi21 #size-cells = <0>;
23 powerpc: PowerPC,5200@0 {
25 reg = <0>;
28 d-cache-size = <0x4000>; // L1, 16K
29 i-cache-size = <0x4000>; // L1, 16K
30 timebase-frequency = <0>; // from bootloader
31 bus-frequency = <0>; // from bootloader
32 clock-frequency = <0>; // from bootloader
36 memory: memory@0 {
38 reg = <0x00000000 0x04000000>; // 64MB
[all …]
/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/
H A Dst,stm32mp25-omm.yaml34 <chip-select> 0 <registers base address> <size>
110 default: 0
116 - 0: OCTOSPI1 chip select send to NCS1 OCTOSPI2 chip select send to NCS1
120 minimum: 0
122 default: 0
128 - 0: direct mode
132 minimum: 0
134 default: 0
137 ^spi@[0-9]:
163 reg = <0x40500000 0x400>, <0x60000000 0x10000000>;
[all …]
/freebsd/sys/dev/bnxt/bnxt_re/
H A Dbnxt_re.h70 #define BNXT_RE_ROCE_V1_ETH_TYPE 0x8915
107 __x == 0 ? __y : ((__y == 0) ? __x : min(__x, __y)); })
135 * [0, 100]
139 #define BNXT_RE_UD_QP_HW_STALL 0x400000
154 #define BNXT_RE_CHIP_NUM_57454 0xC454
155 #define BNXT_RE_CHIP_NUM_57452 0xC452
220 #define BNXT_RE_PRE_RECOVERY_REMOVE 0x1
221 #define BNXT_RE_COMPLETE_REMOVE 0x2
222 #define BNXT_RE_POST_RECOVERY_INIT 0x4
223 #define BNXT_RE_COMPLETE_INIT 0x8
[all …]
H A Dqplib_res.h38 #define CHIP_NUM_57508 0x1750
39 #define CHIP_NUM_57504 0x1751
40 #define CHIP_NUM_57502 0x1752
41 #define CHIP_NUM_58818 0xd818
42 #define CHIP_NUM_57608 0x1760
49 #define BNXT_QPLIB_DBR_VALID (0x1UL << 26)
53 #define BNXT_QPLIB_DBR_PF_DB_OFFSET 0x10000
54 #define BNXT_QPLIB_DBR_VF_DB_OFFSET 0x4000
59 #define BNXT_RE_DEFAULT 0xf
62 BNXT_QPLIB_WQE_MODE_STATIC = 0x00,
[all …]
/freebsd/sys/contrib/device-tree/src/arm/synaptics/
H A Dberlin2.dtsi28 #size-cells = <0>;
31 cpu@0 {
35 reg = <0>;
68 #clock-cells = <0>;
78 ranges = <0 0xf7000000 0x1000000>;
82 reg = <0xab0000 0x200>;
91 reg = <0xab0800 0x200>;
100 reg = <0xab1000 0x200>;
104 pinctrl-0 = <&emmc_pmux>;
111 reg = <0xac0000 0x1000>;
[all …]
H A Dberlin2cd.dtsi27 #size-cells = <0>;
29 cpu: cpu@0 {
33 reg = <0>;
53 #clock-cells = <0>;
63 ranges = <0 0xf7000000 0x1000000>;
67 reg = <0xab0000 0x200>;
76 reg = <0xac0000 0x1000>;
83 reg = <0xad0000 0x100>;
88 reg = <0xad1000 0x1000>, <0xad0100 0x0100>;
95 reg = <0xad0200 0x20>;
[all …]
H A Dberlin2q.dtsi22 #size-cells = <0>;
25 cpu0: cpu@0 {
29 reg = <0>;
113 #clock-cells = <0>;
122 ranges = <0 0xf7000000 0x1000000>;
127 reg = <0xab0000 0x200>;
136 reg = <0xab0800 0x200>;
145 reg = <0xab1000 0x200>;
154 reg = <0xac0000 0x1000>;
163 reg = <0xad0000 0x58>;
[all …]
/freebsd/sys/dev/ral/
H A Drt2661reg.h35 #define RT2661_HOST_CMD_CSR 0x0008
36 #define RT2661_MCU_CNTL_CSR 0x000c
37 #define RT2661_SOFT_RESET_CSR 0x0010
38 #define RT2661_MCU_INT_SOURCE_CSR 0x0014
39 #define RT2661_MCU_INT_MASK_CSR 0x0018
40 #define RT2661_PCI_USEC_CSR 0x001c
41 #define RT2661_H2M_MAILBOX_CSR 0x2100
42 #define RT2661_M2H_CMD_DONE_CSR 0x2104
43 #define RT2661_HW_BEACON_BASE0 0x2c00
44 #define RT2661_MAC_CSR0 0x3000
[all …]
/freebsd/sys/contrib/dev/mediatek/mt76/
H A Dmt76x02_regs.h9 #define MT_ASIC_VERSION 0x0000
11 #define MT76XX_REV_E3 0x22
12 #define MT76XX_REV_E4 0x33
14 #define MT_CMB_CTRL 0x0020
18 #define MT_EFUSE_CTRL 0x0024
19 #define MT_EFUSE_CTRL_AOUT GENMASK(5, 0)
27 #define MT_EFUSE_DATA_BASE 0x0028
30 #define MT_COEXCFG0 0x0040
31 #define MT_COEXCFG0_COEX_EN BIT(0)
33 #define MT_WLAN_FUN_CTRL 0x0080
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/amlogic/
H A Dmeson-a1.dtsi23 #size-cells = <0>;
25 cpu0: cpu@0 {
28 reg = <0x0 0x0>;
37 reg = <0x0 0x1>;
72 size = <0x0 0x800000>;
73 alignment = <0x0 0x400000>;
95 reg = <0x0 0xfd000400 0x0 0x290>;
98 #size-cells = <0>;
105 reg = <0x0 0xfe000000 0x0 0x1000000>;
108 ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x1000000>;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Support/
H A DUnicodeCaseFold.cpp5 // http://www.unicode.org/Public/15.1.0/ucd/CaseFolding.txt
9 // "http://www.unicode.org/Public/15.1.0/ucd/CaseFolding.txt" \
17 if (C < 0x0041) in foldCharSimple()
20 if (C <= 0x005a) in foldCharSimple()
23 if (C == 0x00b5) in foldCharSimple()
24 return 0x03bc; in foldCharSimple()
25 if (C < 0x00c0) in foldCharSimple()
28 if (C <= 0x00d6) in foldCharSimple()
30 if (C < 0x00d8) in foldCharSimple()
33 if (C <= 0x00d in foldCharSimple()
[all...]
/freebsd/sys/dev/pms/RefTisa/sat/src/
H A Dsmdefs.h29 #define SM_ROOT_MEM_INDEX 0 /**< the index of dm roo…
41 SM_TIMER_LOCK = 0,
51 #define SATA_ATA_DEVICE 0x01 /**< ATA ATA device ty…
52 #define SATA_ATAPI_DEVICE 0x02 /**< ATA ATAPI device …
53 #define SATA_PM_DEVICE 0x03 /**< ATA PM device typ…
54 #define SATA_SEMB_DEVICE 0x04 /**< ATA SEMB device t…
55 #define SATA_SEMB_WO_SEP_DEVICE 0x05 /**< ATA SEMB without …
56 #define UNKNOWN_DEVICE 0xFF
61 #define PIO_SETUP_DEV_TO_HOST_FIS 0x5F
62 #define REG_DEV_TO_HOST_FIS 0x34
[all …]
/freebsd/sys/dev/bwi/
H A Dbwiphy.c103 #define BWI_PHYTBL_WRSSI 0x1000
104 #define BWI_PHYTBL_NOISE_SCALE 0x1400
105 #define BWI_PHYTBL_NOISE 0x1800
106 #define BWI_PHYTBL_ROTOR 0x2000
107 #define BWI_PHYTBL_DELAY 0x2400
108 #define BWI_PHYTBL_RSSI 0x4000
109 #define BWI_PHYTBL_SIGMA_SQ 0x5000
110 #define BWI_PHYTBL_WRSSI_REV1 0x5400
111 #define BWI_PHYTBL_FREQ 0x5800
187 for (i = 0; i < nitems(bwi_sup_bphy); ++i) { in bwi_phy_attach()
[all …]
/freebsd/sys/dev/bxe/
H A D57710_int_offsets.h31 { 0x40, 0x0, 0x0, 0x0, 0x0}, // COMMON_SB_SIZE
32 { 0x40, 0x0, 0x0, 0x0, 0x0}, // COMMON_SB_DATA_SIZE
33 { 0x28, 0x0, 0x0, 0x0, 0x0}, // COMMON_SP_SB_SIZE
34 { 0x10, 0x0, 0x0, 0x0, 0x0}, // COMMON_SP_SB_DATA_SIZE
35 { 0x40, 0x0, 0x0, 0x0, 0x0}, // COMMON_DYNAMIC_HC_CONFIG_SIZE
36 { 0x10, 0x0, 0x0, 0x0, 0x0}, // COMMON_ASM_ASSERT_MSG_SIZE
37 { 0x8, 0x0, 0x0, 0x0, 0x0}, // COMMON_ASM_ASSERT_INDEX_SIZE
38 { 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_ASM_INVALID_ASSERT_OPCODE
39 { 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_RAM1_TEST_EVENT_ID
40 …{ 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_INBOUND_INTERRUPT_TEST_AGG_INT_EVEN…
[all …]
/freebsd/sys/dev/neta/
H A Dif_mvnetareg.h39 #define MVNETA_SIZE 0x4000
53 #if MVNETA_TX_QNUM_MAX & (MVNETA_TX_QNUM_MAX - 1) != 0
56 #if MVNETA_RX_QNUM_MAX & (MVNETA_RX_QNUM_MAX - 1) != 0
61 #define MVNETA_QUEUE_ALL 0xff
67 * GbE0 BASE 0x00007.0000 SIZE 0x4000
68 * GbE1 BASE 0x00007.4000 SIZE 0x4000
73 #define MVNETA_BASEADDR(n) (0x2200 + ((n) << 3)) /* Base Address */
74 #define MVNETA_S(n) (0x2204 + ((n) << 3)) /* Size */
75 #define MVNETA_HA(n) (0x2280 + ((n) << 2)) /* High Address Remap */
76 #define MVNETA_BARE 0x2290 /* Base Address Enable */
[all …]
/freebsd/sys/contrib/dev/rtw88/
H A Ddebug.c140 return 0; in rtw_debugfs_close()
178 seq_printf(m, "reg 0x%03x: 0x%02x\n", addr, val); in rtw_debugfs_get_read_reg()
182 seq_printf(m, "reg 0x%03x: 0x%04x\n", addr, val); in rtw_debugfs_get_read_reg()
186 seq_printf(m, "reg 0x%03x: 0x%08x\n", addr, val); in rtw_debugfs_get_read_reg()
189 return 0; in rtw_debugfs_get_read_reg()
207 seq_printf(m, "rf_read path:%d addr:0x%08x mask:0x%08x val=0x%08x\n", in rtw_debugfs_get_rf_read()
210 return 0; in rtw_debugfs_get_rf_read()
222 return 0; in rtw_debugfs_get_fix_rate()
226 return 0; in rtw_debugfs_get_fix_rate()
235 memset(tmp, 0, size); in rtw_debugfs_copy_from_user()
[all …]
H A Drtw8821c.c57 efuse->rfe_option = map->rfe_option & 0x1f; in rtw8821c_read_efuse()
62 efuse->lna_type_2g = map->lna_type_2g[0]; in rtw8821c_read_efuse()
63 efuse->lna_type_5g = map->lna_type_5g[0]; in rtw8821c_read_efuse()
65 efuse->country_code[0] = map->country_code[0]; in rtw8821c_read_efuse()
68 efuse->regd = map->rf_board_option & 0x7; in rtw8821c_read_efuse()
69 efuse->thermal_meter[0] = map->thermal_meter; in rtw8821c_read_efuse()
74 hal->pkg_type = map->rfe_option & BIT(5) ? 1 : 0; in rtw8821c_read_efuse()
77 case 0x2: in rtw8821c_read_efuse()
78 case 0x4: in rtw8821c_read_efuse()
79 case 0x7: in rtw8821c_read_efuse()
[all …]
/freebsd/sys/dev/usb/wlan/
H A Dif_mtwreg.h19 #define MTW_ASIC_VER 0x0000
20 #define MTW_CMB_CTRL 0x0020
21 #define MTW_EFUSE_CTRL 0x0024
22 #define MTW_EFUSE_DATA0 0x0028
23 #define MTW_EFUSE_DATA1 0x002c
24 #define MTW_EFUSE_DATA2 0x0030
25 #define MTW_EFUSE_DATA3 0x0034
26 #define MTW_OSC_CTRL 0x0038
27 #define MTW_COEX_CFG0 0x0040
28 #define MTW_PLL_CTRL 0x0050
[all …]
/freebsd/sys/dev/pms/RefTisa/tisa/sassata/common/
H A Dtddefs.h40 #define agFALSE 0
44 #define agNULL ((void *)0)
72 #define OFF 0
87 #define TD_OPERATION_INITIATOR 0x1
88 #define TD_OPERATION_TARGET 0x2
111 #define TD_CARD_ID_FREE 0
140 #define DEFAULT_OUTBOUND_QUEUE_INTERRUPT_DELAY 0
143 #define DEFAULT_INBOUND_QUEUE_PRIORITY 0
144 #define DEFAULT_QUEUE_OPTION 0
150 #define SAS_NO_DEVICE 0
[all …]
/freebsd/contrib/file/magic/Magdir/
H A Danimation11 0 string MOVI Silicon Graphics movie file
51 # https://www.3gpp2.org/Public_html/Specs/C.S0050-B_v1.0_070521.pdf
53 >>11 byte 0x61 \b C.S0050-0 V1.0
54 >>11 byte 0x62 \b C.S0050-0-A V1.0.0
55 >>11 byte 0x63 \b C.S0050-0-B V1.0
178 >8 string J2P0 \b, JPEG2000 Profile 0
315 0 belong 0x00000001
316 >4 byte&0x1F 0x07 JVT NAL sequence, H.264 video
321 0 belong&0xFFFFFF00 0x00000100
322 >3 byte 0xBA MPEG sequence
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/st/
H A Dstm32mp251.dtsi18 #size-cells = <0>;
20 cpu0: cpu@0 {
23 reg = <0>;
39 arm,smc-id = <0xb200005a>;
45 #clock-cells = <0>;
47 clock-frequency = <0>;
51 #clock-cells = <0>;
68 #size-cells = <0>;
69 linaro,optee-channel-id = <0>;
72 reg = <0x14>;
[all …]
/freebsd/sys/dev/bge/
H A Dif_bgereg.h54 * device register space at offset 0x8000 to read any 32K chunk
60 * accessed directly. NIC memory addresses are offset by 0x01000000.
64 #define BGE_PAGE_ZERO 0x00000000
65 #define BGE_PAGE_ZERO_END 0x000000FF
66 #define BGE_SEND_RING_RCB 0x00000100
67 #define BGE_SEND_RING_RCB_END 0x000001FF
68 #define BGE_RX_RETURN_RING_RCB 0x00000200
69 #define BGE_RX_RETURN_RING_RCB_END 0x000002FF
70 #define BGE_STATS_BLOCK 0x00000300
71 #define BGE_STATS_BLOCK_END 0x00000AFF
[all …]

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