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/linux/arch/sh/drivers/pci/
H A Dfixups-sh03.c12 if (dev->bus->number == 0) { in pcibios_map_platform_irq()
14 case 4: return evt2irq(0x2a0); /* eth0 */ in pcibios_map_platform_irq()
15 case 8: return evt2irq(0x2a0); /* eth1 */ in pcibios_map_platform_irq()
16 case 6: return evt2irq(0x240); /* PCI bridge */ in pcibios_map_platform_irq()
20 return evt2irq(0x240); in pcibios_map_platform_irq()
24 case 0: irq = evt2irq(0x240); break; in pcibios_map_platform_irq()
25 case 1: irq = evt2irq(0x240); break; in pcibios_map_platform_irq()
26 case 2: irq = evt2irq(0x240); break; in pcibios_map_platform_irq()
27 case 3: irq = evt2irq(0x240); break; in pcibios_map_platform_irq()
28 case 4: irq = evt2irq(0x240); break; in pcibios_map_platform_irq()
H A Dfixups-snapgear.c26 case 11: irq = evt2irq(0x300); break; /* USB */ in pcibios_map_platform_irq()
27 case 12: irq = evt2irq(0x360); break; /* PCMCIA */ in pcibios_map_platform_irq()
28 case 13: irq = evt2irq(0x2a0); break; /* eth0 */ in pcibios_map_platform_irq()
29 case 14: irq = evt2irq(0x300); break; /* eth1 */ in pcibios_map_platform_irq()
30 case 15: irq = evt2irq(0x360); break; /* safenet (unused) */ in pcibios_map_platform_irq()
H A Dfixups-landisk.c18 #define PCIMCR_MRSET_OFF 0xBFFFFFFF
19 #define PCIMCR_RFSH_OFF 0xFFFFFFFB
29 int irq = ((slot + pin - 1) & 0x3) + evt2irq(0x2a0); in pcibios_map_platform_irq()
31 if ((slot | (pin - 1)) > 0x3) { in pcibios_map_platform_irq()
44 bcr1 |= 0x40080000; /* Enable Bit 19 BREQEN, set PCIC to slave */ in pci_fixup_pcic()
51 pci_write_reg(chan, 0x0c000000, SH7751_PCICONF5); in pci_fixup_pcic()
52 pci_write_reg(chan, 0xd0000000, SH7751_PCICONF6); in pci_fixup_pcic()
53 pci_write_reg(chan, 0x0c000000, SH4_PCILAR0); in pci_fixup_pcic()
54 pci_write_reg(chan, 0x00000000, SH4_PCILAR1); in pci_fixup_pcic()
56 return 0; in pci_fixup_pcic()
/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dti,keystone-irq.yaml58 reg = <0x2a0 0x4>;
59 ti,syscon-dev = <&devctrl 0x2a0>;
/linux/drivers/clk/st/
H A Dclkgen-fsyn.c26 #define PLL_BW_GOODREF (0L)
88 .nrst = { CLKGEN_FIELD(0x2f0, 0x1, 0),
89 CLKGEN_FIELD(0x2f0, 0x1, 1),
90 CLKGEN_FIELD(0x2f0, 0x1, 2),
91 CLKGEN_FIELD(0x2f0, 0x1, 3) },
92 .npda = CLKGEN_FIELD(0x2f0, 0x1, 12),
93 .nsb = { CLKGEN_FIELD(0x2f0, 0x1, 8),
94 CLKGEN_FIELD(0x2f0, 0x1, 9),
95 CLKGEN_FIELD(0x2f0, 0x1, 10),
96 CLKGEN_FIELD(0x2f0, 0x1, 11) },
[all …]
H A Dclkgen-pll.c26 #define C32_NDIV_MASK (0xff)
27 #define C32_IDF_MASK (0x7)
28 #define C32_ODF_MASK (0x3f)
29 #define C32_LDF_MASK (0x7f)
30 #define C32_CP_MASK (0x1f)
37 #define C28_NDIV_MASK (0xff)
38 #define C28_IDF_MASK (0x7)
39 #define C28_ODF_MASK (0x3f)
77 .pdn_status = CLKGEN_FIELD(0x2a0, 0x1, 8),
78 .pdn_ctrl = CLKGEN_FIELD(0x2a0, 0x1, 8),
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/
H A Dvmmgv100.c39 data[0] = nvkm_ro32(inst, 0x200); in gv100_vmm_join()
40 data[1] = nvkm_ro32(inst, 0x204); in gv100_vmm_join()
41 mask = BIT_ULL(0); in gv100_vmm_join()
43 nvkm_wo32(inst, 0x21c, 0x00000000); in gv100_vmm_join()
45 for (i = 0; i < 64; i++) { in gv100_vmm_join()
47 nvkm_wo32(inst, 0x2a4 + (i * 0x10), data[1]); in gv100_vmm_join()
48 nvkm_wo32(inst, 0x2a0 + (i * 0x10), data[0]); in gv100_vmm_join()
50 nvkm_wo32(inst, 0x2a4 + (i * 0x10), 0x00000001); in gv100_vmm_join()
51 nvkm_wo32(inst, 0x2a0 + (i * 0x10), 0x00000001); in gv100_vmm_join()
53 nvkm_wo32(inst, 0x2a8 + (i * 0x10), 0x00000000); in gv100_vmm_join()
[all …]
/linux/arch/sh/boards/
H A Dboard-edosk7760.c24 #define BSC_CS4BCR 0xA4FD0010
25 #define BSC_CS4WCR 0xA4FD0030
27 #define SMC_IOBASE 0xA2000000
28 #define SMC_IO_OFFSET 0x300
35 .offset = 0,
60 [0] = {
62 .start = 0x00000000,
63 .end = 0x00000000 + SZ_32M - 1,
88 .start = evt2irq(0x9e0),
89 .end = evt2irq(0x9e0),
[all …]
/linux/arch/sh/include/mach-common/mach/
H A Dtitan.h14 #define TITAN_IRQ_WAN evt2irq(0x240) /* eth0 (WAN) */
15 #define TITAN_IRQ_LAN evt2irq(0x2a0) /* eth1 (LAN) */
16 #define TITAN_IRQ_MPCIA evt2irq(0x300) /* mPCI A */
17 #define TITAN_IRQ_MPCIB evt2irq(0x360) /* mPCI B */
18 #define TITAN_IRQ_USB evt2irq(0x360) /* USB */
/linux/drivers/tty/serial/8250/
H A D8250_fourport.c16 SERIAL8250_FOURPORT(0x1a0, 9),
17 SERIAL8250_FOURPORT(0x1a8, 9),
18 SERIAL8250_FOURPORT(0x1b0, 9),
19 SERIAL8250_FOURPORT(0x1b8, 9),
20 SERIAL8250_FOURPORT(0x2a0, 5),
21 SERIAL8250_FOURPORT(0x2a8, 5),
22 SERIAL8250_FOURPORT(0x2b0, 5),
23 SERIAL8250_FOURPORT(0x2b8, 5),
/linux/drivers/clk/mediatek/
H A Dclk-mt8186-mcu.c39 MUX(CLK_MCU_ARMPLL_LL_SEL, "mcu_armpll_ll_sel", mcu_armpll_ll_parents, 0x2A0, 9, 2),
41 MUX(CLK_MCU_ARMPLL_BL_SEL, "mcu_armpll_bl_sel", mcu_armpll_bl_parents, 0x2A4, 9, 2),
43 MUX(CLK_MCU_ARMPLL_BUS_SEL, "mcu_armpll_bus_sel", mcu_armpll_bus_parents, 0x2E0, 9, 2),
/linux/arch/sh/include/mach-landisk/mach/
H A Diodata_landisk.h16 #define PA_USB 0xa4000000 /* USB Controller M66590 */
18 #define PA_ATARST 0xb0000000 /* ATA/FATA Access Control Register */
19 #define PA_LED 0xb0000001 /* LED Control Register */
20 #define PA_STATUS 0xb0000002 /* Switch Status Register */
21 #define PA_SHUTDOWN 0xb0000003 /* Shutdown Control Register */
22 #define PA_PCIPME 0xb0000004 /* PCI PME Status Register */
23 #define PA_IMASK 0xb0000005 /* Interrupt Mask Register */
25 #define PA_PWRINT_CLR 0xb0000006 /* Shutdown Interrupt clear Register */
27 #define PA_PIDE_OFFSET 0x40 /* CF IDE Offset */
28 #define PA_SIDE_OFFSET 0x40 /* HDD IDE Offset */
[all …]
/linux/drivers/media/platform/mediatek/mdp3/
H A Dmdp_reg_rdma.h10 #define MDP_RDMA_EN 0x000
11 #define MDP_RDMA_RESET 0x008
12 #define MDP_RDMA_CON 0x020
13 #define MDP_RDMA_GMCIF_CON 0x028
14 #define MDP_RDMA_SRC_CON 0x030
15 #define MDP_RDMA_MF_BKGD_SIZE_IN_BYTE 0x060
16 #define MDP_RDMA_MF_BKGD_SIZE_IN_PXL 0x068
17 #define MDP_RDMA_MF_SRC_SIZE 0x070
18 #define MDP_RDMA_MF_CLIP_SIZE 0x078
19 #define MDP_RDMA_MF_OFFSET_1 0x080
[all …]
/linux/sound/soc/tegra/
H A Dtegra210_mixer.h13 #define TEGRA210_MIXER_RX1_SOFT_RESET 0x04
14 #define TEGRA210_MIXER_RX1_STATUS 0x10
15 #define TEGRA210_MIXER_RX1_CIF_CTRL 0x24
16 #define TEGRA210_MIXER_RX1_CTRL 0x28
17 #define TEGRA210_MIXER_RX1_PEAK_CTRL 0x2c
18 #define TEGRA210_MIXER_RX1_SAMPLE_COUNT 0x30
21 #define TEGRA210_MIXER_TX1_ENABLE 0x280
22 #define TEGRA210_MIXER_TX1_SOFT_RESET 0x284
23 #define TEGRA210_MIXER_TX1_STATUS 0x290
24 #define TEGRA210_MIXER_TX1_INT_STATUS 0x294
[all …]
/linux/include/linux/bcma/
H A Dbcma_driver_gmac_cmn.h7 #define BCMA_GMAC_CMN_STAG0 0x000
8 #define BCMA_GMAC_CMN_STAG1 0x004
9 #define BCMA_GMAC_CMN_STAG2 0x008
10 #define BCMA_GMAC_CMN_STAG3 0x00C
11 #define BCMA_GMAC_CMN_PARSER_CTL 0x020
12 #define BCMA_GMAC_CMN_MIB_MAX_LEN 0x024
13 #define BCMA_GMAC_CMN_PHY_ACCESS 0x100
14 #define BCMA_GMAC_CMN_PA_DATA_MASK 0x0000ffff
15 #define BCMA_GMAC_CMN_PA_ADDR_MASK 0x001f0000
17 #define BCMA_GMAC_CMN_PA_REG_MASK 0x1f000000
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimxrt1050-pinfunc.h10 #define IMX_PAD_SION 0x40000000
17 #define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0
18 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0
19 #define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1
20 #define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0
21 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0
22 #define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0
24 #define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0
25 #define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0
26 #define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1
[all …]
/linux/arch/arm/boot/dts/ti/keystone/
H A Dkeystone.dtsi27 reg = <0x00000000 0x80000000 0x00000000 0x40000000>;
34 reg = <0x0 0x02561000 0x0 0x1000>,
35 <0x0 0x02562000 0x0 0x2000>,
36 <0x0 0x02564000 0x0 0x2000>,
37 <0x0 0x02566000 0x0 0x2000>;
66 cpu_suspend = <0x84000001>;
67 cpu_off = <0x84000002>;
68 cpu_on = <0x84000003>;
71 soc0: soc@0 {
76 ranges = <0x0 0x0 0x0 0xc0000000>;
[all …]
H A Dkeystone-k2g-netcp.dtsi13 power-domains = <&k2g_pds 0x0018>;
14 clocks = <&k2g_clks 0x0018 0>;
17 queue-range = <0 0x80>;
18 linkram0 = <0x4020000 0x7ff>;
26 managed-queues = <0 0x80>;
27 reg = <0x4100000 0x800>,
28 <0x4040000 0x100>,
29 <0x4080000 0x800>,
30 <0x40c0000 0x800>;
38 qpend-0 {
[all …]
/linux/drivers/pinctrl/
H A Dpinctrl-pic32.h12 #define ANSEL_REG 0x00
13 #define TRIS_REG 0x10
14 #define PORT_REG 0x20
15 #define LAT_REG 0x30
16 #define ODCU_REG 0x40
17 #define CNPU_REG 0x50
18 #define CNPD_REG 0x60
19 #define CNCON_REG 0x70
20 #define CNEN_REG 0x80
21 #define CNSTAT_REG 0x90
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mq-pinfunc.h15 #define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0…
16 #define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0…
17 #define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0…
18 #define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0…
19 #define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0…
20 #define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
21 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
22 #define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
23 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
24 #define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
[all …]
/linux/drivers/gpu/drm/bridge/
H A Dnwl-dsi.h12 #define NWL_DSI_CFG_NUM_LANES 0x0
13 #define NWL_DSI_CFG_NONCONTINUOUS_CLK 0x4
14 #define NWL_DSI_CFG_T_PRE 0x8
15 #define NWL_DSI_CFG_T_POST 0xc
16 #define NWL_DSI_CFG_TX_GAP 0x10
17 #define NWL_DSI_CFG_AUTOINSERT_EOTP 0x14
18 #define NWL_DSI_CFG_EXTRA_CMDS_AFTER_EOTP 0x18
19 #define NWL_DSI_CFG_HTX_TO_COUNT 0x1c
20 #define NWL_DSI_CFG_LRX_H_TO_COUNT 0x20
21 #define NWL_DSI_CFG_BTA_H_TO_COUNT 0x24
[all …]
/linux/arch/sh/include/mach-sdk7786/mach/
H A Dfpga.h9 #define SRSTR 0x000
10 #define SRSTR_MAGIC 0x1971 /* Fixed magical read value */
12 #define INTASR 0x010
13 #define INTAMR 0x020
14 #define MODSWR 0x030
15 #define INTTESTR 0x040
16 #define SYSSR 0x050
17 #define NRGPR 0x060
19 #define NMISR 0x070
20 #define NMISR_MAN_NMI BIT(0)
[all …]
/linux/drivers/gpu/drm/rockchip/
H A Drk3066_hdmi.h10 #define GRF_SOC_CON0 0x150
13 #define DDC_SEGMENT_ADDR 0x30
15 #define HDMI_MAXIMUM_INFO_FRAME_SIZE 0x11
17 #define N_32K 0x1000
18 #define N_441K 0x1880
19 #define N_882K 0x3100
20 #define N_1764K 0x6200
21 #define N_48K 0x1800
22 #define N_96K 0x3000
23 #define N_192K 0x6000
[all …]
/linux/drivers/pinctrl/samsung/
H A Dpinctrl-exynos-arm.c27 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
32 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
36 #define S5P_OTHERS 0xE000
43 #define S5P_PIN_PULL_DISABLE 0
86 clk_base = of_iomap(np, 0); in s5pv210_retention_init()
106 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
107 EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpa1", 0x04),
108 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
109 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
110 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
[all …]
/linux/arch/powerpc/kernel/
H A Dexceptions-64e.S39 #define SPECIAL_EXC_SRR0 0
83 lwz r12,0(r11)
119 li r10,0
145 lwz r12,0(r11)
164 PPC_TLBILX_ALL(0,R0)
200 stdcx. r0,0,r1 /* to clear the reservation */
228 REST_GPR(0, r1)
264 cmpdi cr1,r1,0; /* check if SP makes sense */ \
368 SAVE_GPR(0, r1); /* save r0 in stackframe */ \
385 ZEROIZE_GPR(0); \
[all …]

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