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/linux/Documentation/devicetree/bindings/sound/
H A Drenesas,rz-ssi.yaml65 bits[0:9] - Specifies MID/RID value of a SSI channel as below
66 MID/RID value of SSI rx0 = 0x256
67 MID/RID value of SSI tx0 = 0x255
68 MID/RID value of SSI rx1 = 0x25a
69 MID/RID value of SSI tx1 = 0x259
70 MID/RID value of SSI rt2 = 0x25f
71 MID/RID value of SSI rx3 = 0x262
72 MID/RID value of SSI tx3 = 0x261
75 bit[11] - LVL = 0, Detects based on the edge
77 bit[15] - TM = 0, Single transfer mode
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/linux/drivers/net/ethernet/freescale/dpaa2/
H A Ddpni-cmd.h13 #define DPNI_VER_MINOR 0
23 #define DPNI_CMDID_OPEN DPNI_CMD(0x801)
24 #define DPNI_CMDID_CLOSE DPNI_CMD(0x800)
25 #define DPNI_CMDID_CREATE DPNI_CMD(0x901)
26 #define DPNI_CMDID_DESTROY DPNI_CMD(0x900)
27 #define DPNI_CMDID_GET_API_VERSION DPNI_CMD(0xa01)
29 #define DPNI_CMDID_ENABLE DPNI_CMD(0x002)
30 #define DPNI_CMDID_DISABLE DPNI_CMD(0x003)
31 #define DPNI_CMDID_GET_ATTR DPNI_CMD(0x004)
32 #define DPNI_CMDID_RESET DPNI_CMD(0x005)
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/linux/include/linux/mfd/mt6331/
H A Dregisters.h10 #define MT6331_STRUP_CON0 0x0
11 #define MT6331_STRUP_CON2 0x2
12 #define MT6331_STRUP_CON3 0x4
13 #define MT6331_STRUP_CON4 0x6
14 #define MT6331_STRUP_CON5 0x8
15 #define MT6331_STRUP_CON6 0xA
16 #define MT6331_STRUP_CON7 0xC
17 #define MT6331_STRUP_CON8 0xE
18 #define MT6331_STRUP_CON9 0x10
19 #define MT6331_STRUP_CON10 0x12
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/linux/sound/drivers/opl4/
H A Dopl4_synth.c41 #define MIDI_CTL_RELEASE_TIME 0x48
42 #define MIDI_CTL_ATTACK_TIME 0x49
43 #define MIDI_CTL_DECAY_TIME 0x4b
44 #define MIDI_CTL_VIBRATO_RATE 0x4c
45 #define MIDI_CTL_VIBRATO_DEPTH 0x4d
46 #define MIDI_CTL_VIBRATO_DELAY 0x4e
52 static const s16 snd_opl4_pitch_map[0x600] = {
53 0x000,0x000,0x001,0x001,0x002,0x002,0x003,0x003,
54 0x004,0x004,0x005,0x005,0x006,0x006,0x006,0x007,
55 0x007,0x008,0x008,0x009,0x009,0x00a,0x00a,0x00b,
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/linux/drivers/gpu/drm/amd/pm/powerplay/inc/
H A Dsmu7_ppsmc.h30 #define PPSMC_MSG_SetGBDroopSettings ((uint16_t) 0x305)
32 #define PPSMC_SWSTATE_FLAG_DC 0x01
33 #define PPSMC_SWSTATE_FLAG_UVD 0x02
34 #define PPSMC_SWSTATE_FLAG_VCE 0x04
36 #define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL 0x00
37 #define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL 0x01
38 #define PPSMC_THERMAL_PROTECT_TYPE_NONE 0xff
40 #define PPSMC_SYSTEMFLAG_GPIO_DC 0x01
41 #define PPSMC_SYSTEMFLAG_STEPVDDC 0x02
42 #define PPSMC_SYSTEMFLAG_GDDR5 0x04
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H A Dtonga_ppsmc.h29 #define PPSMC_SWSTATE_FLAG_DC 0x01
30 #define PPSMC_SWSTATE_FLAG_UVD 0x02
31 #define PPSMC_SWSTATE_FLAG_VCE 0x04
32 #define PPSMC_SWSTATE_FLAG_PCIE_X1 0x08
34 #define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL 0x00
35 #define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL 0x01
36 #define PPSMC_THERMAL_PROTECT_TYPE_NONE 0xff
38 #define PPSMC_SYSTEMFLAG_GPIO_DC 0x01
39 #define PPSMC_SYSTEMFLAG_STEPVDDC 0x02
40 #define PPSMC_SYSTEMFLAG_GDDR5 0x04
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H A Dfiji_ppsmc.h30 #define PPSMC_SWSTATE_FLAG_DC 0x01
31 #define PPSMC_SWSTATE_FLAG_UVD 0x02
32 #define PPSMC_SWSTATE_FLAG_VCE 0x04
34 #define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL 0x00
35 #define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL 0x01
36 #define PPSMC_THERMAL_PROTECT_TYPE_NONE 0xff
38 #define PPSMC_SYSTEMFLAG_GPIO_DC 0x01
39 #define PPSMC_SYSTEMFLAG_STEPVDDC 0x02
40 #define PPSMC_SYSTEMFLAG_GDDR5 0x04
42 #define PPSMC_SYSTEMFLAG_DISABLE_BABYSTEP 0x08
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/linux/Documentation/mm/
H A Dslub.rst107 If the file contains 1, the option is enabled, 0 means disabled. The debug
117 failslab file is writable, so writing 1 or 0 will enable or disable
154 .. slab_min_order=x (default 0)
174 ``debug_guardpage_minorder=N`` (N > 0), forces setting
175 ``slab_max_order`` to 0, what cause minimum possible order of
196 INFO: 0xc90f6d28-0xc90f6d2b. First byte 0x00 instead of 0xcc
197 INFO: Slab 0xc528c530 flags=0x400000c3 inuse=61 fp=0xc90f6d58
198 INFO: Object 0xc90f6d20 @offset=3360 fp=0xc90f6d58
199 INFO: Allocated in get_modalias+0x61/0xf5 age=53 cpu=1 pid=554
201 Bytes b4 (0xc90f6d10): 00 00 00 00 00 00 00 00 5a 5a 5a 5a 5a 5a 5a 5a ........ZZZZZZZZ
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/linux/include/uapi/linux/
H A Dinput-event-codes.h23 #define INPUT_PROP_POINTER 0x00 /* needs a pointer */
24 #define INPUT_PROP_DIRECT 0x01 /* direct input devices */
25 #define INPUT_PROP_BUTTONPAD 0x02 /* has button(s) under pad */
26 #define INPUT_PROP_SEMI_MT 0x03 /* touch rectangle only */
27 #define INPUT_PROP_TOPBUTTONPAD 0x04 /* softbuttons at top of pad */
28 #define INPUT_PROP_POINTING_STICK 0x05 /* is a pointing stick */
29 #define INPUT_PROP_ACCELEROMETER 0x06 /* has accelerometer */
31 #define INPUT_PROP_MAX 0x1f
38 #define EV_SYN 0x00
39 #define EV_KEY 0x0
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/linux/include/dt-bindings/input/
H A Dlinux-event-codes.h23 #define INPUT_PROP_POINTER 0x00 /* needs a pointer */
24 #define INPUT_PROP_DIRECT 0x01 /* direct input devices */
25 #define INPUT_PROP_BUTTONPAD 0x02 /* has button(s) under pad */
26 #define INPUT_PROP_SEMI_MT 0x03 /* touch rectangle only */
27 #define INPUT_PROP_TOPBUTTONPAD 0x04 /* softbuttons at top of pad */
28 #define INPUT_PROP_POINTING_STICK 0x05 /* is a pointing stick */
29 #define INPUT_PROP_ACCELEROMETER 0x06 /* has accelerometer */
31 #define INPUT_PROP_MAX 0x1f
38 #define EV_SYN 0x00
39 #define EV_KEY 0x0
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/linux/drivers/media/i2c/
H A Dmax96717.c23 #define MAX96717_DEVICE_ID 0xbf
24 #define MAX96717F_DEVICE_ID 0xc8
26 #define MAX96717_PAD_SINK 0
33 #define MAX96717_REG3 CCI_REG8(0x3)
34 #define MAX96717_RCLKSEL GENMASK(1, 0)
35 #define RCLKSEL_REF_PLL CCI_REG8(0x3)
36 #define MAX96717_REG6 CCI_REG8(0x6)
38 #define MAX96717_DEV_ID CCI_REG8(0xd)
39 #define MAX96717_DEV_REV CCI_REG8(0xe)
40 #define MAX96717_DEV_REV_MASK GENMASK(3, 0)
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/linux/drivers/net/ethernet/meta/fbnic/
H A Dfbnic_csr.h16 #define MIN_FW_MAJOR_VERSION 0
23 #define PCI_DEVICE_ID_META_FBNIC_ASIC 0x0013
29 #define FBNIC_TWD_L2_HLEN_MASK DESC_GENMASK(5, 0)
33 FBNIC_TWD_L3_TYPE_OTHER = 0,
43 FBNIC_TWD_L4_TYPE_OTHER = 0,
62 FBNIC_TWD_TYPE_META = 0,
71 #define FBNIC_TWD_TS_MASK DESC_GENMASK(39, 0)
72 #define FBNIC_TWD_ADDR_MASK DESC_GENMASK(45, 0)
76 #define FBNIC_TCD_TYPE0_HEAD0_MASK DESC_GENMASK(15, 0)
79 #define FBNIC_TCD_TYPE1_TS_MASK DESC_GENMASK(39, 0)
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/linux/drivers/net/wireless/broadcom/b43/
H A Dphy_n.h11 #define B43_NPHY_BBCFG B43_PHY_N(0x001) /* BB config */
12 #define B43_NPHY_BBCFG_RSTCCA 0x4000 /* Reset CCA */
13 #define B43_NPHY_BBCFG_RSTRX 0x8000 /* Reset RX */
14 #define B43_NPHY_CHANNEL B43_PHY_N(0x005) /* Channel */
15 #define B43_NPHY_TXERR B43_PHY_N(0x007) /* TX error */
16 #define B43_NPHY_BANDCTL B43_PHY_N(0x009) /* Band control */
17 #define B43_NPHY_BANDCTL_5GHZ 0x0001 /* Use the 5GHz band */
18 #define B43_NPHY_4WI_ADDR B43_PHY_N(0x00B) /* Four-wire bus address */
19 #define B43_NPHY_4WI_DATAHI B43_PHY_N(0x00C) /* Four-wire bus data high */
20 #define B43_NPHY_4WI_DATALO B43_PHY_N(0x00D) /* Four-wire bus data low */
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/linux/drivers/net/wireless/realtek/rtw89/
H A Dcore.h28 #define MASKBYTE0 0xff
29 #define MASKBYTE1 0xff00
30 #define MASKBYTE2 0xff0000
31 #define MASKBYTE3 0xff000000
32 #define MASKBYTE4 0xff00000000ULL
33 #define MASKHWORD 0xffff0000
34 #define MASKLWORD 0x0000ffff
35 #define MASKDWORD 0xffffffff
36 #define RFREG_MASK 0xfffff
37 #define INV_RF_DATA 0xffffffff
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H A Drtw8852bt_rfk.c16 #define RTW8852BT_RXDCK_VER 0x1
17 #define RTW8852BT_IQK_VER 0x2a
20 #define RTW8852BT_DPK_VER 0x06
24 #define DPK_TXAGC_LOWER 0x2e
25 #define DPK_TXAGC_UPPER 0x3f
26 #define DPK_TXAGC_INVAL 0xff
27 #define RFREG_MASKRXBB 0x003e0
28 #define RFREG_MASKMODE 0xf0000
31 RF_SHUT_DOWN = 0x0,
32 RF_STANDBY = 0x1,
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H A Drtw8852b_rfk.c16 #define RTW8852B_RXDCK_VER 0x1
17 #define RTW8852B_IQK_VER 0x2a
22 #define RTW8852B_DPK_VER 0x0d
28 #define DPK_TXAGC_LOWER 0x2e
29 #define DPK_TXAGC_UPPER 0x3f
30 #define DPK_TXAGC_INVAL 0xff
31 #define RFREG_MASKRXBB 0x003e0
32 #define RFREG_MASKMODE 0xf0000
35 LBK_RXIQK = 0x06,
36 SYNC = 0x10,
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