Lines Matching +full:0 +full:x262
16 #define RTW8852BT_RXDCK_VER 0x1
17 #define RTW8852BT_IQK_VER 0x2a
20 #define RTW8852BT_DPK_VER 0x06
24 #define DPK_TXAGC_LOWER 0x2e
25 #define DPK_TXAGC_UPPER 0x3f
26 #define DPK_TXAGC_INVAL 0xff
27 #define RFREG_MASKRXBB 0x003e0
28 #define RFREG_MASKMODE 0xf0000
31 RF_SHUT_DOWN = 0x0,
32 RF_STANDBY = 0x1,
33 RF_TX = 0x2,
34 RF_RX = 0x3,
35 RF_TXIQK = 0x4,
36 RF_DPK = 0x5,
37 RF_RXK1 = 0x6,
38 RF_RXK2 = 0x7,
42 LBK_RXIQK = 0x06,
43 SYNC = 0x10,
44 MDPK_IDL = 0x11,
45 MDPK_MPA = 0x12,
46 GAIN_LOSS = 0x13,
47 GAIN_CAL = 0x14,
48 DPK_RXAGC = 0x15,
49 KIP_PRESET = 0x16,
50 KIP_RESTORE = 0x17,
51 DPK_TXAGC = 0x19,
52 D_KIP_PRESET = 0x28,
53 D_TXAGC = 0x29,
54 D_RXAGC = 0x2a,
55 D_SYNC = 0x2b,
56 D_GAIN_LOSS = 0x2c,
57 D_MDPK_IDL = 0x2d,
58 D_GAIN_NORM = 0x2f,
59 D_KIP_THERMAL = 0x30,
60 D_KIP_RESTORE = 0x31
73 ID_TXAGC = 0x0,
74 ID_FLOK_COARSE = 0x1,
75 ID_FLOK_FINE = 0x2,
76 ID_TXK = 0x3,
77 ID_RXAGC = 0x4,
78 ID_RXK = 0x5,
79 ID_NBTXK = 0x6,
80 ID_NBRXK = 0x7,
81 ID_FLOK_VBUFFER = 0x8,
82 ID_A_FLOK_COARSE = 0x9,
83 ID_G_FLOK_COARSE = 0xa,
84 ID_A_FLOK_FINE = 0xb,
85 ID_G_FLOK_FINE = 0xc,
86 ID_IQK_RESTORE = 0x10,
90 ADC_NA = 0,
97 DAC_40M = 0,
107 static const u32 _tssi_trigger[RTW8852BT_TSSI_PATH_NR] = {0x5820, 0x7820};
108 static const u32 _tssi_cw_rpt_addr[RTW8852BT_TSSI_PATH_NR] = {0x1c18, 0x3c18};
110 {0x5634, 0x5630, 0x5630, 0x5630},
111 {0x7634, 0x7630, 0x7630, 0x7630} };
113 0x000003ff, 0x3ff00000, 0x000ffc00, 0x000003ff};
114 static const u32 _tssi_de_cck_long[RF_PATH_NUM_8852BT] = {0x5858, 0x7858};
115 static const u32 _tssi_de_cck_short[RF_PATH_NUM_8852BT] = {0x5860, 0x7860};
116 static const u32 _tssi_de_mcs_20m[RF_PATH_NUM_8852BT] = {0x5838, 0x7838};
117 static const u32 _tssi_de_mcs_40m[RF_PATH_NUM_8852BT] = {0x5840, 0x7840};
118 static const u32 _tssi_de_mcs_80m[RF_PATH_NUM_8852BT] = {0x5848, 0x7848};
119 static const u32 _tssi_de_mcs_80m_80m[RF_PATH_NUM_8852BT] = {0x5850, 0x7850};
120 static const u32 _tssi_de_mcs_5m[RF_PATH_NUM_8852BT] = {0x5828, 0x7828};
121 static const u32 _tssi_de_mcs_10m[RF_PATH_NUM_8852BT] = {0x5830, 0x7830};
123 static const u32 rtw8852bt_backup_bb_regs[] = {0x2344, 0x5800, 0x7800, 0x0704};
125 0xde, 0xdf, 0x8b, 0x90, 0x97, 0x85, 0x5, 0x10005};
127 0x813c, 0x8124, 0x8120, 0xc0d4, 0xc0d8, 0xc0c4, 0xc0ec,
128 0x823c, 0x8224, 0x8220, 0xc1d4, 0xc1d8, 0xc1c4, 0xc1ec};
138 rtw89_write_rf(rtwdev, path, RR_TM, RR_TM_TRI, 0x1); in _rfk_get_thermal()
139 rtw89_write_rf(rtwdev, path, RR_TM, RR_TM_TRI, 0x0); in _rfk_get_thermal()
140 rtw89_write_rf(rtwdev, path, RR_TM, RR_TM_TRI, 0x1); in _rfk_get_thermal()
146 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] thermal@DPK = 0x%x\n", in _rfk_get_thermal()
154 for (i = 0; i < BACKUP_BB_REGS_NR; i++) { in _rfk_backup_bb_reg()
167 for (i = 0; i < BACKUP_KIP_REGS_NR; i++) { in _rfk_backup_kip_reg()
171 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] Backup 0x%x = %x\n", in _rfk_backup_kip_reg()
181 for (i = 0; i < BACKUP_RF_REGS_NR; i++) { in _rfk_backup_rf_reg()
186 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] Backup RF S%d 0x%x = %x\n", in _rfk_backup_rf_reg()
195 for (i = 0; i < BACKUP_BB_REGS_NR; i++) { in _rfk_reload_bb_reg()
208 for (i = 0; i < BACKUP_KIP_REGS_NR; i++) { in _rfk_reload_kip_reg()
223 for (i = 0; i < BACKUP_RF_REGS_NR; i++) { in _rfk_reload_rf_reg()
255 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK | (path << 13), B_P0_TXCK_ON, 0x0); in _txck_force()
261 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK | (path << 13), B_P0_TXCK_ON, 0x1); in _txck_force()
268 u32 bw = 0; in _rxck_force()
270 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK | (path << 13), B_P0_RXCK_ON, 0x0); in _rxck_force()
276 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK | (path << 13), B_P0_RXCK_ON, 0x1); in _rxck_force()
299 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, MASKHWORD, 0x0303); in _rfk_bb_afe_setting()
300 rtw89_phy_write32_mask(rtwdev, R_P0_ADCFF_EN, B_P0_ADCFF_EN, 0x1); in _rfk_bb_afe_setting()
301 rtw89_phy_write32_mask(rtwdev, R_P1_ADCFF_EN, B_P1_ADCFF_EN, 0x1); in _rfk_bb_afe_setting()
302 rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_CLKG_FORCE, 0x3); in _rfk_bb_afe_setting()
303 rtw89_phy_write32_mask(rtwdev, R_P1_RFCTM, B_P1_CLKG_FORCE, 0x3); in _rfk_bb_afe_setting()
304 rtw89_phy_write32_mask(rtwdev, R_TXCKEN_FORCE, B_TXCKEN_FORCE_ALL, 0x1ffffff); in _rfk_bb_afe_setting()
305 rtw89_phy_write32_mask(rtwdev, R_FAHM, B_RXTD_CKEN, 0x1); in _rfk_bb_afe_setting()
306 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_UPD_GEN_ON, 0x1); in _rfk_bb_afe_setting()
307 rtw89_phy_write32_mask(rtwdev, R_TX_COLLISION_T2R_ST, B_TXRX_FORCE_VAL, 0x3ff); in _rfk_bb_afe_setting()
308 rtw89_phy_write32_mask(rtwdev, R_IOQ_IQK_DPK, B_IOQ_IQK_DPK_CLKEN, 0x3); in _rfk_bb_afe_setting()
309 rtw89_phy_write32_mask(rtwdev, R_IQK_DPK_RST, B_IQK_DPK_RST, 0x1); in _rfk_bb_afe_setting()
310 rtw89_phy_write32_mask(rtwdev, R_P0_PATH_RST, B_P0_PATH_RST, 0x1); in _rfk_bb_afe_setting()
311 rtw89_phy_write32_mask(rtwdev, R_P1_PATH_RST, B_P1_PATH_RST, 0x1); in _rfk_bb_afe_setting()
312 rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x1); in _rfk_bb_afe_setting()
313 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0x1); in _rfk_bb_afe_setting()
314 rtw89_phy_write32_mask(rtwdev, R_DCFO_WEIGHT, B_DAC_CLK_IDX, 0x1); in _rfk_bb_afe_setting()
322 B_UPD_CLK_ADC_VAL | B_UPD_CLK_ADC_ON, 0x5); in _rfk_bb_afe_setting()
323 rtw89_phy_write32_mask(rtwdev, R_P0_NRBW, B_P0_NRBW_DBG, 0x1); in _rfk_bb_afe_setting()
324 rtw89_phy_write32_mask(rtwdev, R_P1_DBGMOD, B_P1_DBGMOD_ON, 0x1); in _rfk_bb_afe_setting()
325 rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, MASKBYTE3, 0x1f); in _rfk_bb_afe_setting()
327 rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, MASKBYTE3, 0x13); in _rfk_bb_afe_setting()
328 rtw89_phy_write32_mask(rtwdev, R_ANAPAR, MASKHWORD, 0x0001); in _rfk_bb_afe_setting()
330 rtw89_phy_write32_mask(rtwdev, R_ANAPAR, MASKHWORD, 0x0041); in _rfk_bb_afe_setting()
331 rtw89_phy_write32_mask(rtwdev, R_P0_NRBW, B_P0_NRBW_RSTB, 0x1); in _rfk_bb_afe_setting()
332 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, MASKHWORD, 0x3333); in _rfk_bb_afe_setting()
334 rtw89_phy_write32_mask(rtwdev, R_TXPWRB_H, B_TXPWRB_RDY, 0x1); in _rfk_bb_afe_setting()
335 rtw89_phy_write32_mask(rtwdev, R_DPD_OFT_EN, MASKLWORD, 0x0000); in _rfk_bb_afe_setting()
336 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_FORCE, B_P1_TXPW_RDY, 0x1); in _rfk_bb_afe_setting()
337 rtw89_phy_write32_mask(rtwdev, R_P1_TXAGC_TH, MASKLWORD, 0x0000); in _rfk_bb_afe_setting()
343 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, MASKHWORD, 0x0303); in _rfk_bb_afe_restore()
344 rtw89_phy_write32_mask(rtwdev, R_P0_NRBW, B_P0_NRBW_DBG, 0x0); in _rfk_bb_afe_restore()
345 rtw89_phy_write32_mask(rtwdev, R_P1_DBGMOD, B_P1_DBGMOD_ON, 0x0); in _rfk_bb_afe_restore()
346 rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_CLKG_FORCE, 0x0); in _rfk_bb_afe_restore()
347 rtw89_phy_write32_mask(rtwdev, R_P1_RFCTM, B_P1_CLKG_FORCE, 0x0); in _rfk_bb_afe_restore()
348 rtw89_phy_write32_mask(rtwdev, R_TXCKEN_FORCE, B_TXCKEN_FORCE_ALL, 0x0); in _rfk_bb_afe_restore()
349 rtw89_phy_write32_mask(rtwdev, R_FAHM, B_RXTD_CKEN, 0x0); in _rfk_bb_afe_restore()
350 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_UPD_GEN_ON, 0x0); in _rfk_bb_afe_restore()
351 rtw89_phy_write32_mask(rtwdev, R_TX_COLLISION_T2R_ST, B_TXRX_FORCE_VAL, 0x63); in _rfk_bb_afe_restore()
352 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK, B_P0_TXCK_ALL, 0x00); in _rfk_bb_afe_restore()
353 rtw89_phy_write32_mask(rtwdev, R_P1_RXCK, B_P1_TXCK_ALL, 0x00); in _rfk_bb_afe_restore()
355 B_UPD_CLK_ADC_VAL | B_UPD_CLK_ADC_ON, 0x0); in _rfk_bb_afe_restore()
356 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, MASKHWORD, 0x0000); in _rfk_bb_afe_restore()
357 rtw89_phy_write32_mask(rtwdev, R_P0_ADCFF_EN, B_P0_ADCFF_EN, 0x0); in _rfk_bb_afe_restore()
358 rtw89_phy_write32_mask(rtwdev, R_P1_ADCFF_EN, B_P1_ADCFF_EN, 0x0); in _rfk_bb_afe_restore()
359 rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x0); in _rfk_bb_afe_restore()
361 rtw89_phy_write32_mask(rtwdev, R_TXPWRB_H, B_TXPWRB_RDY, 0x0); in _rfk_bb_afe_restore()
362 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_MV_AVG, B_P0_TXPW_RSTB, 0x1); in _rfk_bb_afe_restore()
363 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_MV_AVG, B_P0_TXPW_RSTB, 0x2); in _rfk_bb_afe_restore()
364 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_FORCE, B_P1_TXPW_RDY, 0x0); in _rfk_bb_afe_restore()
365 rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_MV_AVG, B_P1_TXPW_RSTB, 0x1); in _rfk_bb_afe_restore()
366 rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_MV_AVG, B_P1_TXPW_RSTB, 0x2); in _rfk_bb_afe_restore()
372 rtw89_write_rf(rtwdev, path, RR_DCK1, RR_DCK1_CLR, 0x0); in _set_rx_dck()
373 rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_LV, 0x0); in _set_rx_dck()
374 rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_LV, 0x1); in _set_rx_dck()
384 "[RX_DCK] ****** RXDCK Start (Ver: 0x%x, CV : 0x%x) ******\n", in _rx_dck()
387 for (path = 0; path < RF_PATH_NUM_8852BT; path++) { in _rx_dck()
394 B_P0_TSSI_TRK_EN, 0x1); in _rx_dck()
396 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0); in _rx_dck()
397 rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_FINE, 0x0); in _rx_dck()
406 B_P0_TSSI_TRK_EN, 0x0); in _rx_dck()
421 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0); in _rck()
424 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RCK] RF0x00 = 0x%05x\n", in _rck()
428 rtw89_write_rf(rtwdev, path, RR_RCKC, RFREG_MASK, 0x00240); in _rck()
435 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RCK] rck_val = 0x%x, ret = %d\n", in _rck()
441 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RCK] RF 0x1b = 0x%x\n", in _rck()
452 rtw89_phy_write32_mask(rtwdev, R_DRCK, B_DRCK_EN, 0x1); in _drck()
460 rtw89_phy_write32_mask(rtwdev, R_DRCK, B_DRCK_EN, 0x0); in _drck()
461 rtw89_phy_write32_mask(rtwdev, R_DRCK_FH, B_DRCK_LAT, 0x1); in _drck()
463 rtw89_phy_write32_mask(rtwdev, R_DRCK_FH, B_DRCK_LAT, 0x0); in _drck()
465 rck_d = rtw89_phy_read32_mask(rtwdev, R_DRCK_RES, 0x7c00); in _drck()
466 rtw89_phy_write32_mask(rtwdev, R_DRCK, B_DRCK_IDLE, 0x0); in _drck()
469 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0xc0c4 = 0x%x\n", in _drck()
478 rtw89_phy_write32_mask(rtwdev, R_P0_NRBW, B_P0_NRBW_DBG, 0x1); in _dack_backup_s0()
480 for (i = 0; i < 0x10; i++) { in _dack_backup_s0()
482 dack->msbk_d[0][0][i] = in _dack_backup_s0()
486 dack->msbk_d[0][1][i] = in _dack_backup_s0()
490 dack->biask_d[0][0] = in _dack_backup_s0()
492 dack->biask_d[0][1] = in _dack_backup_s0()
495 dack->dadck_d[0][0] = in _dack_backup_s0()
497 dack->dadck_d[0][1] = in _dack_backup_s0()
506 rtw89_phy_write32_mask(rtwdev, R_P1_DBGMOD, B_P1_DBGMOD_ON, 0x1); in _dack_backup_s1()
508 for (i = 0; i < 0x10; i++) { in _dack_backup_s1()
510 dack->msbk_d[1][0][i] = in _dack_backup_s1()
518 dack->biask_d[1][0] = in _dack_backup_s1()
523 dack->dadck_d[1][0] = in _dack_backup_s1()
533 rtw89_phy_write32_mask(rtwdev, R_DCOF0, B_DCOF0_RST, 0x0); in _dack_reset()
534 rtw89_phy_write32_mask(rtwdev, R_DCOF0, B_DCOF0_RST, 0x1); in _dack_reset()
536 rtw89_phy_write32_mask(rtwdev, R_DACK10, B_DACK10_RST, 0x0); in _dack_reset()
537 rtw89_phy_write32_mask(rtwdev, R_DACK10, B_DACK10_RST, 0x1); in _dack_reset()
549 if (index == 0) in _dack_reload_by_path()
550 idx_offset = 0; in _dack_reload_by_path()
552 idx_offset = 0x14; in _dack_reload_by_path()
555 path_offset = 0; in _dack_reload_by_path()
557 path_offset = 0x28; in _dack_reload_by_path()
561 rtw89_phy_write32_mask(rtwdev, R_DCOF1, B_DCOF1_RST, 0x1); in _dack_reload_by_path()
562 rtw89_phy_write32_mask(rtwdev, R_DCOF9, B_DCOF9_RST, 0x1); in _dack_reload_by_path()
563 rtw89_phy_write32_mask(rtwdev, R_DACK1_K, B_DACK1_RST, 0x1); in _dack_reload_by_path()
564 rtw89_phy_write32_mask(rtwdev, R_DACK2_K, B_DACK2_RST, 0x1); in _dack_reload_by_path()
567 tmp = 0x0; in _dack_reload_by_path()
568 for (i = 0; i < 4; i++) in _dack_reload_by_path()
570 tmp_reg = 0xc200 + tmp_offset; in _dack_reload_by_path()
572 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x=0x%x\n", tmp_reg, in _dack_reload_by_path()
576 tmp = 0x0; in _dack_reload_by_path()
577 for (i = 0; i < 4; i++) in _dack_reload_by_path()
579 tmp_reg = 0xc204 + tmp_offset; in _dack_reload_by_path()
581 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x=0x%x\n", tmp_reg, in _dack_reload_by_path()
585 tmp = 0x0; in _dack_reload_by_path()
586 for (i = 0; i < 4; i++) in _dack_reload_by_path()
588 tmp_reg = 0xc208 + tmp_offset; in _dack_reload_by_path()
590 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x=0x%x\n", tmp_reg, in _dack_reload_by_path()
593 /* msbk_d: 3/2/1/0 */ in _dack_reload_by_path()
594 tmp = 0x0; in _dack_reload_by_path()
595 for (i = 0; i < 4; i++) in _dack_reload_by_path()
597 tmp_reg = 0xc20c + tmp_offset; in _dack_reload_by_path()
599 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x=0x%x\n", tmp_reg, in _dack_reload_by_path()
605 tmp_reg = 0xc210 + tmp_offset; in _dack_reload_by_path()
607 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x=0x%x\n", tmp_reg, in _dack_reload_by_path()
611 rtw89_phy_write32_mask(rtwdev, R_DACKN0_CTL + tmp_offset, B_DACKN0_EN, 0x1); in _dack_reload_by_path()
619 for (i = 0; i < 2; i++) in _dack_reload()
625 if (rtw89_phy_read32_mask(rtwdev, R_DACK_S0P0, B_DACK_S0P0_OK) == 0 || in _dack_s0_poll()
626 rtw89_phy_read32_mask(rtwdev, R_DACK_S0P1, B_DACK_S0P1_OK) == 0 || in _dack_s0_poll()
627 rtw89_phy_read32_mask(rtwdev, R_DACK_S0P2, B_DACK_S0P2_OK) == 0 || in _dack_s0_poll()
628 rtw89_phy_read32_mask(rtwdev, R_DACK_S0P3, B_DACK_S0P3_OK) == 0) in _dack_s0_poll()
642 rtw89_phy_write32_mask(rtwdev, R_P0_NRBW, B_P0_NRBW_DBG, 0x1); in _dack_s0()
643 rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, BIT(28), 0x1); in _dack_s0()
644 rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_EN1, 0x0); in _dack_s0()
646 rtw89_phy_write32_mask(rtwdev, R_DCOF1, B_DCOF1_VAL, 0x30); in _dack_s0()
647 rtw89_phy_write32_mask(rtwdev, R_DCOF9, B_DCOF9_VAL, 0x30); in _dack_s0()
651 rtw89_phy_write32_mask(rtwdev, R_DCOF1, B_DCOF1_S, 0x1); in _dack_s0()
654 dack->msbk_timeout[0] = false; in _dack_s0()
660 dack->msbk_timeout[0] = true; in _dack_s0()
663 rtw89_phy_write32_mask(rtwdev, R_DCOF1, B_DCOF1_S, 0x0); in _dack_s0()
669 rtw89_phy_write32_mask(rtwdev, R_P0_NRBW, B_P0_NRBW_DBG, 0x0); in _dack_s0()
674 if (rtw89_phy_read32_mask(rtwdev, R_DACK_S1P0, B_DACK_S1P0_OK) == 0 || in _dack_s1_poll()
675 rtw89_phy_read32_mask(rtwdev, R_DACK_S1P1, B_DACK_S1P1_OK) == 0 || in _dack_s1_poll()
676 rtw89_phy_read32_mask(rtwdev, R_DACK_S1P2, B_DACK_S1P2_OK) == 0 || in _dack_s1_poll()
677 rtw89_phy_read32_mask(rtwdev, R_DACK_S1P3, B_DACK_S1P3_OK) == 0) in _dack_s1_poll()
691 rtw89_phy_write32_mask(rtwdev, R_P1_DBGMOD, B_P1_DBGMOD_ON, 0x1); in _dack_s1()
692 rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, BIT(28), 0x1); in _dack_s1()
693 rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_EN1, 0x0); in _dack_s1()
695 rtw89_phy_write32_mask(rtwdev, R_DACK1_K, B_DACK1_VAL, 0x30); in _dack_s1()
696 rtw89_phy_write32_mask(rtwdev, R_DACK2_K, B_DACK2_VAL, 0x30); in _dack_s1()
700 rtw89_phy_write32_mask(rtwdev, R_DACK1_K, B_DACK1_EN, 0x1); in _dack_s1()
712 rtw89_phy_write32_mask(rtwdev, R_DACK1_K, B_DACK1_EN, 0x0); in _dack_s1()
718 rtw89_phy_write32_mask(rtwdev, R_P1_DBGMOD, B_P1_DBGMOD_ON, 0x0); in _dack_s1()
734 "[DACK]S0 ADC_DCK ic = 0x%x, qc = 0x%x\n", in _dack_dump()
735 dack->addck_d[0][0], dack->addck_d[0][1]); in _dack_dump()
737 "[DACK]S1 ADC_DCK ic = 0x%x, qc = 0x%x\n", in _dack_dump()
738 dack->addck_d[1][0], dack->addck_d[1][1]); in _dack_dump()
740 "[DACK]S0 DAC_DCK ic = 0x%x, qc = 0x%x\n", in _dack_dump()
741 dack->dadck_d[0][0], dack->dadck_d[0][1]); in _dack_dump()
743 "[DACK]S1 DAC_DCK ic = 0x%x, qc = 0x%x\n", in _dack_dump()
744 dack->dadck_d[1][0], dack->dadck_d[1][1]); in _dack_dump()
746 "[DACK]S0 biask ic = 0x%x, qc = 0x%x\n", in _dack_dump()
747 dack->biask_d[0][0], dack->biask_d[0][1]); in _dack_dump()
749 "[DACK]S1 biask ic = 0x%x, qc = 0x%x\n", in _dack_dump()
750 dack->biask_d[1][0], dack->biask_d[1][1]); in _dack_dump()
753 for (i = 0; i < 0x10; i++) { in _dack_dump()
754 t = dack->msbk_d[0][0][i]; in _dack_dump()
755 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n", t); in _dack_dump()
759 for (i = 0; i < RTW89_DACK_MSBK_NR; i++) { in _dack_dump()
760 t = dack->msbk_d[0][1][i]; in _dack_dump()
761 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n", t); in _dack_dump()
765 for (i = 0; i < RTW89_DACK_MSBK_NR; i++) { in _dack_dump()
766 t = dack->msbk_d[1][0][i]; in _dack_dump()
767 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n", t); in _dack_dump()
771 for (i = 0; i < RTW89_DACK_MSBK_NR; i++) { in _dack_dump()
773 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n", t); in _dack_dump()
783 rtw89_phy_write32_mask(rtwdev, R_ADDCK0, B_ADDCK0_MAN, 0x0); in _addck_ori()
784 rtw89_phy_write32_mask(rtwdev, R_ADDCK1, B_ADDCK1_MAN, 0x0); in _addck_ori()
785 rtw89_phy_write32_mask(rtwdev, R_P0_NRBW, B_P0_NRBW_DBG, 0x1); in _addck_ori()
786 rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_ADCCLK, 0x0); in _addck_ori()
787 rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_FLTRST, 0x0); in _addck_ori()
788 rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_FLTRST, 0x1); in _addck_ori()
790 rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15_H, 0xf); in _addck_ori()
793 rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_EN, 0x0); in _addck_ori()
794 rtw89_phy_write32_mask(rtwdev, R_PATH0_SAMPL_DLY_T_V1, BIT(4), 0x1); in _addck_ori()
795 rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15_H, 0x3); in _addck_ori()
796 rtw89_phy_write32_mask(rtwdev, R_ADDCK0, B_ADDCK0_TRG, 0x1); in _addck_ori()
797 rtw89_phy_write32_mask(rtwdev, R_ADDCK0, B_ADDCK0_TRG, 0x0); in _addck_ori()
800 rtw89_phy_write32_mask(rtwdev, R_ADDCK0, B_ADDCK0, 0x1); in _addck_ori()
801 dack->addck_timeout[0] = false; in _addck_ori()
805 rtwdev, R_ADDCKR0, BIT(0)); in _addck_ori()
808 dack->addck_timeout[0] = true; in _addck_ori()
811 rtw89_phy_write32_mask(rtwdev, R_PATH0_SAMPL_DLY_T_V1, BIT(4), 0x0); in _addck_ori()
812 rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_EN, 0x1); in _addck_ori()
813 rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15_H, 0xc); in _addck_ori()
814 rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_ADCCLK, 0x1); in _addck_ori()
816 rtw89_phy_write32_mask(rtwdev, R_ADDCK0, B_ADDCK0, 0x0); in _addck_ori()
817 dack->addck_d[0][0] = in _addck_ori()
819 dack->addck_d[0][1] = in _addck_ori()
821 rtw89_phy_write32_mask(rtwdev, R_P0_NRBW, B_P0_NRBW_DBG, 0x0); in _addck_ori()
823 rtw89_phy_write32_mask(rtwdev, R_P1_DBGMOD, B_P1_DBGMOD_ON, 0x1); in _addck_ori()
824 rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_ADCCLK, 0x0); in _addck_ori()
825 rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_FLTRST, 0x0); in _addck_ori()
826 rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_FLTRST, 0x1); in _addck_ori()
828 rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15_H, 0xf); in _addck_ori()
831 rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_EN, 0x0); in _addck_ori()
832 rtw89_phy_write32_mask(rtwdev, R_PATH1_SAMPL_DLY_T_V1, BIT(4), 0x1); in _addck_ori()
833 rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15_H, 0x3); in _addck_ori()
834 rtw89_phy_write32_mask(rtwdev, R_ADDCK1, B_ADDCK1_TRG, 0x1); in _addck_ori()
835 rtw89_phy_write32_mask(rtwdev, R_ADDCK1, B_ADDCK1_TRG, 0x0); in _addck_ori()
838 rtw89_phy_write32_mask(rtwdev, R_ADDCK1, B_ADDCK1, 0x1); in _addck_ori()
843 rtwdev, R_ADDCKR1, BIT(0)); in _addck_ori()
849 rtw89_phy_write32_mask(rtwdev, R_PATH1_SAMPL_DLY_T_V1, BIT(4), 0x0); in _addck_ori()
850 rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_EN, 0x1); in _addck_ori()
851 rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15_H, 0xc); in _addck_ori()
852 rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_ADCCLK, 0x1); in _addck_ori()
854 rtw89_phy_write32_mask(rtwdev, R_ADDCK1, B_ADDCK1, 0x0); in _addck_ori()
855 dack->addck_d[1][0] = in _addck_ori()
860 rtw89_phy_write32_mask(rtwdev, R_P1_DBGMOD, B_P1_DBGMOD_ON, 0x0); in _addck_ori()
867 rtw89_phy_write32_mask(rtwdev, R_ADDCK0_RL, B_ADDCK0_RL1, dack->addck_d[0][0]); in _addck_reload()
868 rtw89_phy_write32_mask(rtwdev, R_ADDCK0_RL, B_ADDCK0_RL0, dack->addck_d[0][1]); in _addck_reload()
870 rtw89_phy_write32_mask(rtwdev, R_ADDCK0_RL, B_ADDCK0_RLS, 0x3); in _addck_reload()
872 rtw89_phy_write32_mask(rtwdev, R_ADDCK1_RL, B_ADDCK1_RL1, dack->addck_d[1][0]); in _addck_reload()
875 rtw89_phy_write32_mask(rtwdev, R_ADDCK1_RL, B_ADDCK1_RLS, 0x3); in _addck_reload()
880 rtw89_phy_write32_mask(rtwdev, R_ADDCK0_RL, B_ADDCK0_RLS, 0x0); in _dack_manual_off()
881 rtw89_phy_write32_mask(rtwdev, R_ADDCK1_RL, B_ADDCK1_RLS, 0x0); in _dack_manual_off()
883 rtw89_phy_write32_mask(rtwdev, R_DACKN0_CTL, B_DACKN0_EN, 0x0); in _dack_manual_off()
884 rtw89_phy_write32_mask(rtwdev, R_DACKN1_CTL, B_DACKN1_ON, 0x0); in _dack_manual_off()
885 rtw89_phy_write32_mask(rtwdev, R_DACKN2_CTL, B_DACKN2_ON, 0x0); in _dack_manual_off()
886 rtw89_phy_write32_mask(rtwdev, R_DACKN3_CTL, B_DACKN3_ON, 0x0); in _dack_manual_off()
898 rtw89_write_rf(rtwdev, RF_PATH_A, RR_RSV1, RFREG_MASK, 0x0); in _dac_cal()
899 rtw89_write_rf(rtwdev, RF_PATH_B, RR_RSV1, RFREG_MASK, 0x0); in _dac_cal()
900 rtw89_write_rf(rtwdev, RF_PATH_A, RR_MOD, RFREG_MASK, 0x337e1); in _dac_cal()
901 rtw89_write_rf(rtwdev, RF_PATH_B, RR_MOD, RFREG_MASK, 0x337e1); in _dac_cal()
910 rtw89_write_rf(rtwdev, RF_PATH_A, RR_MODOPT, RFREG_MASK, 0x0); in _dac_cal()
911 rtw89_write_rf(rtwdev, RF_PATH_B, RR_MODOPT, RFREG_MASK, 0x0); in _dac_cal()
916 rtw89_write_rf(rtwdev, RF_PATH_A, RR_RSV1, RFREG_MASK, 0x1); in _dac_cal()
917 rtw89_write_rf(rtwdev, RF_PATH_B, RR_RSV1, RFREG_MASK, 0x1); in _dac_cal()
929 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val == 0x55, in _iqk_check_cal()
937 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val == 0x8000, in _iqk_check_cal()
946 rtw89_phy_write32_mask(rtwdev, R_NCTL_N1, MASKBYTE0, 0x0); in _iqk_check_cal()
960 iqk_cmd = 0x008 | (1 << (4 + path)) | (path << 1); in _iqk_one_shot()
963 iqk_cmd = 0x108 | (1 << (4 + path)); in _iqk_one_shot()
966 iqk_cmd = 0x208 | (1 << (4 + path)); in _iqk_one_shot()
969 iqk_cmd = 0x308 | (1 << (4 + path)); in _iqk_one_shot()
972 iqk_cmd = 0x008 | (1 << (path + 4)) | in _iqk_one_shot()
973 (((0x8 + iqk_info->iqk_bw[path]) & 0xf) << 8); in _iqk_one_shot()
976 iqk_cmd = 0x508 | (1 << (4 + path)) | (path << 1); in _iqk_one_shot()
979 iqk_cmd = 0x008 | (1 << (path + 4)) | in _iqk_one_shot()
980 (((0xb + iqk_info->iqk_bw[path]) & 0xf) << 8); in _iqk_one_shot()
983 iqk_cmd = 0x408 | (1 << (4 + path)); in _iqk_one_shot()
986 iqk_cmd = 0x608 | (1 << (4 + path)); in _iqk_one_shot()
1007 rtw89_write_rf(rtwdev, path, RR_TXG1, RR_TXG1_ATT2, 0x0); in _iqk_txk_setting()
1008 rtw89_write_rf(rtwdev, path, RR_TXG1, RR_TXG1_ATT1, 0x0); in _iqk_txk_setting()
1009 rtw89_write_rf(rtwdev, path, RR_TXG2, RR_TXG2_ATT0, 0x1); in _iqk_txk_setting()
1010 rtw89_write_rf(rtwdev, path, RR_TXGA, RR_TXGA_LOK_EXT, 0x0); in _iqk_txk_setting()
1011 rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x1); in _iqk_txk_setting()
1012 rtw89_write_rf(rtwdev, path, RR_LUTWA, RR_LUTWA_M1, 0x00); in _iqk_txk_setting()
1013 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_IQK, 0x403e); in _iqk_txk_setting()
1014 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0, 0x0); in _iqk_txk_setting()
1015 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1, 0x5); in _iqk_txk_setting()
1019 rtw89_write_rf(rtwdev, path, RR_BIASA, RR_BIASA_A, 0x1); in _iqk_txk_setting()
1020 rtw89_write_rf(rtwdev, path, RR_TXGA, RR_TXGA_LOK_EXT, 0x0); in _iqk_txk_setting()
1021 rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x1); in _iqk_txk_setting()
1022 rtw89_write_rf(rtwdev, path, RR_LUTWA, RR_LUTWA_M1, 0x80); in _iqk_txk_setting()
1023 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_IQK, 0x403e); in _iqk_txk_setting()
1024 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0, 0x0); in _iqk_txk_setting()
1025 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1, 0x4); in _iqk_txk_setting()
1037 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x0); in _iqk_2g_lok()
1038 rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x1); in _iqk_2g_lok()
1039 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), B_KIP_IQP_IQSW, 0x09); in _iqk_2g_lok()
1040 rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_TXT, 0x021); in _iqk_2g_lok()
1041 rtw89_phy_write32_mask(rtwdev, R_NCTL_CFG, MASKDWORD, 0x00000119 + (path << 4)); in _iqk_2g_lok()
1044 rtw89_phy_write32_mask(rtwdev, R_NCTL_N1, B_NCTL_N1_CIP, 0x00); in _iqk_2g_lok()
1045 rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x0); in _iqk_2g_lok()
1047 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x12); in _iqk_2g_lok()
1048 rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x1); in _iqk_2g_lok()
1049 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), B_KIP_IQP_IQSW, 0x24); in _iqk_2g_lok()
1050 rtw89_phy_write32_mask(rtwdev, R_NCTL_CFG, MASKDWORD, 0x00000319 + (path << 4)); in _iqk_2g_lok()
1053 rtw89_phy_write32_mask(rtwdev, R_NCTL_N1, B_NCTL_N1_CIP, 0x00); in _iqk_2g_lok()
1054 rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x0); in _iqk_2g_lok()
1056 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x0); in _iqk_2g_lok()
1057 rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x1); in _iqk_2g_lok()
1058 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), B_KIP_IQP_IQSW, 0x09); in _iqk_2g_lok()
1059 rtw89_phy_write32_mask(rtwdev, R_NCTL_CFG, MASKDWORD, 0x00000219 + (path << 4)); in _iqk_2g_lok()
1062 rtw89_phy_write32_mask(rtwdev, R_NCTL_N1, B_NCTL_N1_CIP, 0x00); in _iqk_2g_lok()
1063 rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x0); in _iqk_2g_lok()
1065 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x12); in _iqk_2g_lok()
1066 rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x1); in _iqk_2g_lok()
1067 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), B_KIP_IQP_IQSW, 0x24); in _iqk_2g_lok()
1068 rtw89_phy_write32_mask(rtwdev, R_NCTL_CFG, MASKDWORD, 0x00000319 + (path << 4)); in _iqk_2g_lok()
1072 rtw89_phy_write32_mask(rtwdev, R_NCTL_N1, B_NCTL_N1_CIP, 0x00); in _iqk_2g_lok()
1073 rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x0); in _iqk_2g_lok()
1082 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x0); in _iqk_5g_lok()
1083 rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x1); in _iqk_5g_lok()
1084 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), B_KIP_IQP_IQSW, 0x09); in _iqk_5g_lok()
1085 rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_TXT, 0x021); in _iqk_5g_lok()
1086 rtw89_phy_write32_mask(rtwdev, R_NCTL_CFG, MASKDWORD, 0x00000119 + (path << 4)); in _iqk_5g_lok()
1089 rtw89_phy_write32_mask(rtwdev, R_NCTL_N1, B_NCTL_N1_CIP, 0x00); in _iqk_5g_lok()
1090 rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x0); in _iqk_5g_lok()
1092 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x12); in _iqk_5g_lok()
1093 rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x1); in _iqk_5g_lok()
1094 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), B_KIP_IQP_IQSW, 0x24); in _iqk_5g_lok()
1095 rtw89_phy_write32_mask(rtwdev, R_NCTL_CFG, MASKDWORD, 0x00000319 + (path << 4)); in _iqk_5g_lok()
1098 rtw89_phy_write32_mask(rtwdev, R_NCTL_N1, B_NCTL_N1_CIP, 0x00); in _iqk_5g_lok()
1099 rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x0); in _iqk_5g_lok()
1101 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x0); in _iqk_5g_lok()
1102 rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x1); in _iqk_5g_lok()
1103 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), B_KIP_IQP_IQSW, 0x09); in _iqk_5g_lok()
1104 rtw89_phy_write32_mask(rtwdev, R_NCTL_CFG, MASKDWORD, 0x00000219 + (path << 4)); in _iqk_5g_lok()
1107 rtw89_phy_write32_mask(rtwdev, R_NCTL_N1, B_NCTL_N1_CIP, 0x00); in _iqk_5g_lok()
1108 rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x0); in _iqk_5g_lok()
1110 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x12); in _iqk_5g_lok()
1111 rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x1); in _iqk_5g_lok()
1112 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), B_KIP_IQP_IQSW, 0x24); in _iqk_5g_lok()
1113 rtw89_phy_write32_mask(rtwdev, R_NCTL_CFG, MASKDWORD, 0x00000319 + (path << 4)); in _iqk_5g_lok()
1116 rtw89_phy_write32_mask(rtwdev, R_NCTL_N1, B_NCTL_N1_CIP, 0x00); in _iqk_5g_lok()
1117 rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x0); in _iqk_5g_lok()
1124 static const u32 g_power_range[4] = {0x0, 0x0, 0x0, 0x0}; in _iqk_2g_tx()
1125 static const u32 g_track_range[4] = {0x4, 0x4, 0x6, 0x6}; in _iqk_2g_tx()
1126 static const u32 g_gain_bb[4] = {0x08, 0x0e, 0x08, 0x0e}; in _iqk_2g_tx()
1127 static const u32 g_itqt[4] = {0x09, 0x12, 0x1b, 0x24}; in _iqk_2g_tx()
1135 for (gp = 0x0; gp < 0x4; gp++) { in _iqk_2g_tx()
1143 0x00000100, 0x1); in _iqk_2g_tx()
1145 0x00000010, 0x1); in _iqk_2g_tx()
1147 0x00000004, 0x0); in _iqk_2g_tx()
1149 0x00000003, gp); in _iqk_2g_tx()
1151 0x009); in _iqk_2g_tx()
1164 rtw89_phy_write32_mask(rtwdev, R_NCTL_N1, B_NCTL_N1_CIP, 0x00); in _iqk_2g_tx()
1167 "[IQK]S%x, gp = 0x%x, 0x8%x38 = 0x%x\n", in _iqk_2g_tx()
1175 iqk_info->nb_txcfir[path] = 0x40000002; in _iqk_2g_tx()
1177 B_IQK_RES_TXCFIR, 0x0); in _iqk_2g_tx()
1185 static const u32 a_power_range[4] = {0x0, 0x0, 0x0, 0x0}; in _iqk_5g_tx()
1186 static const u32 a_track_range[4] = {0x3, 0x3, 0x6, 0x6}; in _iqk_5g_tx()
1187 static const u32 a_gain_bb[4] = {0x08, 0x10, 0x08, 0x0e}; in _iqk_5g_tx()
1188 static const u32 a_itqt[4] = {0x09, 0x12, 0x1b, 0x24}; in _iqk_5g_tx()
1194 for (gp = 0x0; gp < 0x4; gp++) { in _iqk_5g_tx()
1202 0x00000100, 0x1); in _iqk_5g_tx()
1204 0x00000010, 0x1); in _iqk_5g_tx()
1206 0x00000004, 0x0); in _iqk_5g_tx()
1208 0x00000003, gp); in _iqk_5g_tx()
1210 0x009); in _iqk_5g_tx()
1224 rtw89_phy_write32_mask(rtwdev, R_NCTL_N1, B_NCTL_N1_CIP, 0x00); in _iqk_5g_tx()
1227 "[IQK]S%x, gp = 0x%x, 0x8%x38 = 0x%x\n", in _iqk_5g_tx()
1235 iqk_info->nb_txcfir[path] = 0x40000002; in _iqk_5g_tx()
1237 B_IQK_RES_TXCFIR, 0x0); in _iqk_5g_tx()
1246 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RXK, 0x0303); in _iqk_adc_fifo_rst()
1248 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RXK, 0x3333); in _iqk_adc_fifo_rst()
1256 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RXK, 0x0303); in _iqk_rxclk_setting()
1264 B_UPD_CLK_ADC_ON, 0x1); in _iqk_rxclk_setting()
1266 B_UPD_CLK_ADC_VAL, 0x1); in _iqk_rxclk_setting()
1268 B_PATH0_SAMPL_DLY_T_MSK_V1, 0x2); in _iqk_rxclk_setting()
1270 B_PATH1_SAMPL_DLY_T_MSK_V1, 0x2); in _iqk_rxclk_setting()
1271 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW1, B_P0_CFCH_BW1, 0x8); in _iqk_rxclk_setting()
1273 B_PATH1_BW_SEL_MSK_V1, 0x8); in _iqk_rxclk_setting()
1280 B_UPD_CLK_ADC_ON, 0x1); in _iqk_rxclk_setting()
1282 B_UPD_CLK_ADC_VAL, 0x0); in _iqk_rxclk_setting()
1284 B_PATH0_SAMPL_DLY_T_MSK_V1, 0x3); in _iqk_rxclk_setting()
1286 B_PATH1_SAMPL_DLY_T_MSK_V1, 0x3); in _iqk_rxclk_setting()
1287 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW1, B_P0_CFCH_BW1, 0xf); in _iqk_rxclk_setting()
1289 B_PATH1_BW_SEL_MSK_V1, 0xf); in _iqk_rxclk_setting()
1292 rtw89_phy_write32_mask(rtwdev, R_PATH0_SAMPL_DLY_T_V1, 0x00000780, 0x8); in _iqk_rxclk_setting()
1293 rtw89_phy_write32_mask(rtwdev, R_PATH1_SAMPL_DLY_T_V1, 0x00000780, 0x8); in _iqk_rxclk_setting()
1294 rtw89_phy_write32_mask(rtwdev, R_PATH0_SAMPL_DLY_T_V1, 0x00007800, 0x2); in _iqk_rxclk_setting()
1295 rtw89_phy_write32_mask(rtwdev, R_PATH1_SAMPL_DLY_T_V1, 0x00007800, 0x2); in _iqk_rxclk_setting()
1296 rtw89_phy_write32_mask(rtwdev, R_DRCK, B_DRCK_MUL, 0x0); in _iqk_rxclk_setting()
1297 rtw89_phy_write32_mask(rtwdev, R_P0_NRBW, B_P0_NRBW_DBG, 0x1); in _iqk_rxclk_setting()
1298 rtw89_phy_write32_mask(rtwdev, R_P1_DBGMOD, B_P1_DBGMOD_ON, 0x1); in _iqk_rxclk_setting()
1300 rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15, 0x0f); in _iqk_rxclk_setting()
1302 rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15, 0x03); in _iqk_rxclk_setting()
1303 rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_15, 0xa001); in _iqk_rxclk_setting()
1305 rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_15, 0xa041); in _iqk_rxclk_setting()
1306 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RXK, 0x3333); in _iqk_rxclk_setting()
1311 static const u32 g_idxrxgain[2] = {0x212, 0x310}; in _iqk_2g_rx()
1312 static const u32 g_idxattc2[2] = {0x00, 0x20}; in _iqk_2g_rx()
1313 static const u32 g_idxattc1[2] = {0x3, 0x2}; in _iqk_2g_rx()
1314 static const u32 g_idxrxagc[2] = {0x0, 0x2}; in _iqk_2g_rx()
1315 static const u32 g_idx[2] = {0x0, 0x2}; in _iqk_2g_rx()
1324 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, 0xc); in _iqk_2g_rx()
1325 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL2G, 0x1); in _iqk_2g_rx()
1329 for (gp = 0x0; gp < 0x2; gp++) { in _iqk_2g_rx()
1335 0x00000100, 0x1); in _iqk_2g_rx()
1337 0x00000010, 0x0); in _iqk_2g_rx()
1339 0x00000007, g_idx[gp]); in _iqk_2g_rx()
1340 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RFREG_MASK, 0x80013); in _iqk_2g_rx()
1347 rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x1); in _iqk_2g_rx()
1348 rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_RXT, 0x11); in _iqk_2g_rx()
1351 rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x0); in _iqk_2g_rx()
1353 rtw89_read_rf(rtwdev, path, RR_MOD, 0x003c0)); in _iqk_2g_rx()
1355 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RFREG_MASK, 0x80013); in _iqk_2g_rx()
1358 rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x1); in _iqk_2g_rx()
1359 rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_RXT, 0x011); in _iqk_2g_rx()
1364 MASKDWORD) | 0x2; in _iqk_2g_rx()
1366 "[IQK]S%x, gp = 0x%x, 0x8%x3c = 0x%x\n", path, in _iqk_2g_rx()
1369 rtw89_phy_write32_mask(rtwdev, R_NCTL_N1, B_NCTL_N1_CIP, 0x00); in _iqk_2g_rx()
1370 rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x0); in _iqk_2g_rx()
1375 rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x1); in _iqk_2g_rx()
1377 rtw89_phy_write32_mask(rtwdev, R_NCTL_N1, B_NCTL_N1_CIP, 0x00); in _iqk_2g_rx()
1378 rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x0); in _iqk_2g_rx()
1385 iqk_info->nb_txcfir[path] = 0x40000002; in _iqk_2g_rx()
1387 B_IQK_RES_RXCFIR, 0x0); in _iqk_2g_rx()
1389 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL2G, 0x0); in _iqk_2g_rx()
1396 static const u32 a_idxrxgain[2] = {0x110, 0x290}; in _iqk_5g_rx()
1397 static const u32 a_idxattc2[2] = {0x0f, 0x0f}; in _iqk_5g_rx()
1398 static const u32 a_idxattc1[2] = {0x2, 0x2}; in _iqk_5g_rx()
1399 static const u32 a_idxrxagc[2] = {0x4, 0x6}; in _iqk_5g_rx()
1400 static const u32 a_idx[2] = {0x0, 0x2}; in _iqk_5g_rx()
1409 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, 0xc); in _iqk_5g_rx()
1410 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL5G, 0x1); in _iqk_5g_rx()
1414 for (gp = 0x0; gp < 0x2; gp++) { in _iqk_5g_rx()
1420 0x00000100, 0x1); in _iqk_5g_rx()
1422 0x00000010, 0x0); in _iqk_5g_rx()
1424 0x00000007, a_idx[gp]); in _iqk_5g_rx()
1425 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RFREG_MASK, 0x80013); in _iqk_5g_rx()
1432 rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x1); in _iqk_5g_rx()
1433 rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_RXT, 0x11); in _iqk_5g_rx()
1436 rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x0); in _iqk_5g_rx()
1438 rtw89_read_rf(rtwdev, path, RR_MOD, 0x003c0)); in _iqk_5g_rx()
1440 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RFREG_MASK, 0x80013); in _iqk_5g_rx()
1442 rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x1); in _iqk_5g_rx()
1443 rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_RXT, 0x011); in _iqk_5g_rx()
1447 MASKDWORD) | 0x2; in _iqk_5g_rx()
1449 "[IQK]S%x, gp = 0x%x, 0x8%x3c = 0x%x\n", in _iqk_5g_rx()
1451 rtw89_phy_write32_mask(rtwdev, R_NCTL_N1, B_NCTL_N1_CIP, 0x00); in _iqk_5g_rx()
1452 rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x0); in _iqk_5g_rx()
1457 rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x1); in _iqk_5g_rx()
1459 rtw89_phy_write32_mask(rtwdev, R_NCTL_N1, B_NCTL_N1_CIP, 0x00); in _iqk_5g_rx()
1460 rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x0); in _iqk_5g_rx()
1467 iqk_info->nb_txcfir[path] = 0x40000002; in _iqk_5g_rx()
1469 B_IQK_RES_RXCFIR, 0x0); in _iqk_5g_rx()
1471 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL2G, 0x0); in _iqk_5g_rx()
1484 for (i = 0; i < 3; i++) { in _iqk_by_path()
1498 rtw89_write_rf(rtwdev, path, RR_DTXLOK, RFREG_MASK, 0x80200); in _iqk_by_path()
1499 rtw89_write_rf(rtwdev, path, RR_RSV2, RFREG_MASK, 0x80200); in _iqk_by_path()
1500 rtw89_write_rf(rtwdev, path, RR_LOKVB, RFREG_MASK, 0x80200); in _iqk_by_path()
1503 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]RF_0x08[00:19] = 0x%x\n", in _iqk_by_path()
1505 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]RF_0x09[00:19] = 0x%x\n", in _iqk_by_path()
1507 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]RF_0x0a[00:19] = 0x%x\n", in _iqk_by_path()
1538 for (idx = 0; idx < RTW89_IQK_CHS_NR; idx++) { in _iqk_get_ch_info()
1539 if (iqk_info->iqk_mcc_ch[idx][path] == 0) { in _iqk_get_ch_info()
1549 idx = 0; in _iqk_get_ch_info()
1562 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x18= 0x%x, idx = %x\n", in _iqk_get_ch_info()
1564 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x18= 0x%x\n", in _iqk_get_ch_info()
1566 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x35c= 0x%x\n", in _iqk_get_ch_info()
1568 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]times = 0x%x, ch =%x\n", in _iqk_get_ch_info()
1570 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]iqk_mcc_ch[%x][%x] = 0x%x\n", in _iqk_get_ch_info()
1592 MASKDWORD, 0x40000000); in _iqk_restore()
1594 MASKDWORD, 0x40000000); in _iqk_restore()
1597 0x00000e19 + (path << 4)); in _iqk_restore()
1599 _iqk_check_cal(rtwdev, path, 0x0); in _iqk_restore()
1601 rtw89_phy_write32_mask(rtwdev, R_NCTL_N1, B_NCTL_N1_CIP, 0x00); in _iqk_restore()
1602 rtw89_phy_write32_mask(rtwdev, R_NCTL_RPT, MASKDWORD, 0x00000000); in _iqk_restore()
1603 rtw89_phy_write32_mask(rtwdev, R_KIP_SYSCFG, MASKDWORD, 0x80000000); in _iqk_restore()
1605 rtw89_phy_write32_mask(rtwdev, R_KIP_CLK, MASKDWORD, 0x0); in _iqk_restore()
1606 rtw89_phy_write32_mask(rtwdev, R_IQRSN, B_IQRSN_K2, 0x0); in _iqk_restore()
1607 rtw89_phy_write32_mask(rtwdev, R_CFIR_SYS + (path << 8), BIT(28), 0x0); in _iqk_restore()
1609 rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x0); in _iqk_restore()
1610 rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x0); in _iqk_restore()
1611 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, 0x3); in _iqk_restore()
1612 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x1); in _iqk_restore()
1613 rtw89_write_rf(rtwdev, path, RR_BBDC, RR_BBDC_SEL, 0x1); in _iqk_restore()
1620 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RXK, 0x0303); in _iqk_afebb_restore()
1621 rtw89_phy_write32_mask(rtwdev, R_P0_NRBW, B_P0_NRBW_DBG, 0x0); in _iqk_afebb_restore()
1622 rtw89_phy_write32_mask(rtwdev, R_P1_DBGMOD, B_P1_DBGMOD_ON, 0x0); in _iqk_afebb_restore()
1623 rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_CLKG_FORCE, 0x0); in _iqk_afebb_restore()
1624 rtw89_phy_write32_mask(rtwdev, R_P1_RFCTM, B_P1_CLKG_FORCE, 0x0); in _iqk_afebb_restore()
1625 rtw89_phy_write32_mask(rtwdev, R_TXCKEN_FORCE, B_TXCKEN_FORCE_ALL, 0x0000000); in _iqk_afebb_restore()
1626 rtw89_phy_write32_mask(rtwdev, R_FAHM, B_RXTD_CKEN, 0x0); in _iqk_afebb_restore()
1627 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_UPD_GEN_ON, 0x0); in _iqk_afebb_restore()
1628 rtw89_phy_write32_mask(rtwdev, R_TX_COLLISION_T2R_ST, 0x0000001f, 0x03); in _iqk_afebb_restore()
1629 rtw89_phy_write32_mask(rtwdev, R_TX_COLLISION_T2R_ST, 0x000003e0, 0x03); in _iqk_afebb_restore()
1630 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK, B_P0_TXCK_ALL, 0x00); in _iqk_afebb_restore()
1631 rtw89_phy_write32_mask(rtwdev, R_P1_RXCK, B_P1_TXCK_ALL, 0x00); in _iqk_afebb_restore()
1633 B_UPD_CLK_ADC_VAL | B_UPD_CLK_ADC_ON, 0x0); in _iqk_afebb_restore()
1634 rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x0); in _iqk_afebb_restore()
1635 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0x0); in _iqk_afebb_restore()
1636 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RXK, 0x0000); in _iqk_afebb_restore()
1637 rtw89_phy_write32_mask(rtwdev, R_P0_ADCFF_EN, B_P0_ADCFF_EN, 0x0); in _iqk_afebb_restore()
1638 rtw89_phy_write32_mask(rtwdev, R_P1_ADCFF_EN, B_P1_ADCFF_EN, 0x0); in _iqk_afebb_restore()
1643 u8 idx = 0; in _iqk_preset()
1645 rtw89_phy_write32_mask(rtwdev, R_COEF_SEL + (path << 8), 0x00000001, idx); in _iqk_preset()
1646 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), 0x00000008, idx); in _iqk_preset()
1647 rtw89_phy_write32_mask(rtwdev, R_TXIQC + (path << 8), MASKDWORD, 0x40000000); in _iqk_preset()
1648 rtw89_phy_write32_mask(rtwdev, R_RXIQC + (path << 8), MASKDWORD, 0x40000000); in _iqk_preset()
1650 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0); in _iqk_preset()
1651 rtw89_write_rf(rtwdev, path, RR_BBDC, RR_BBDC_SEL, 0x0); in _iqk_preset()
1652 rtw89_phy_write32_mask(rtwdev, R_NCTL_RPT, MASKDWORD, 0x00000080); in _iqk_preset()
1653 rtw89_phy_write32_mask(rtwdev, R_KIP_SYSCFG, MASKDWORD, 0x81ff010a); in _iqk_preset()
1659 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RXK, 0x0303); in _iqk_macbb_setting()
1660 rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_GOT_TXRX, 0x3); in _iqk_macbb_setting()
1661 rtw89_phy_write32_mask(rtwdev, R_P1_RFCTM, B_P1_GOT_TXRX, 0x3); in _iqk_macbb_setting()
1662 rtw89_phy_write32_mask(rtwdev, R_P0_ADCFF_EN, B_P0_ADCFF_EN, 0x1); in _iqk_macbb_setting()
1663 rtw89_phy_write32_mask(rtwdev, R_P1_ADCFF_EN, B_P1_ADCFF_EN, 0x1); in _iqk_macbb_setting()
1664 rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_CLKG_FORCE, 0x3); in _iqk_macbb_setting()
1665 rtw89_phy_write32_mask(rtwdev, R_P1_RFCTM, B_P0_CLKG_FORCE, 0x3); in _iqk_macbb_setting()
1666 rtw89_phy_write32_mask(rtwdev, R_TXCKEN_FORCE, B_TXCKEN_FORCE_ALL, 0x1ffffff); in _iqk_macbb_setting()
1667 rtw89_phy_write32_mask(rtwdev, R_FAHM, B_RXTD_CKEN, 0x1); in _iqk_macbb_setting()
1668 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_UPD_GEN_ON, 0x1); in _iqk_macbb_setting()
1669 rtw89_phy_write32_mask(rtwdev, R_TX_COLLISION_T2R_ST, B_TXRX_FORCE_VAL, 0x3ff); in _iqk_macbb_setting()
1670 rtw89_phy_write32_mask(rtwdev, R_IOQ_IQK_DPK, B_IOQ_IQK_DPK_CLKEN, 0x3); in _iqk_macbb_setting()
1671 rtw89_phy_write32_mask(rtwdev, R_IQK_DPK_RST, B_IQK_DPK_RST, 0x1); in _iqk_macbb_setting()
1672 rtw89_phy_write32_mask(rtwdev, R_P0_PATH_RST, B_P0_PATH_RST, 0x1); in _iqk_macbb_setting()
1673 rtw89_phy_write32_mask(rtwdev, R_P1_PATH_RST, B_P1_PATH_RST, 0x1); in _iqk_macbb_setting()
1674 rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x1); in _iqk_macbb_setting()
1675 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0x1); in _iqk_macbb_setting()
1676 rtw89_phy_write32_mask(rtwdev, R_DCFO_WEIGHT, B_DAC_CLK_IDX, 0x1); in _iqk_macbb_setting()
1683 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_UPD_CLK_ADC_ON, 0x1); in _iqk_macbb_setting()
1684 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_UPD_CLK_ADC_VAL, 0x2); in _iqk_macbb_setting()
1686 rtw89_phy_write32_mask(rtwdev, R_P0_NRBW, B_P0_NRBW_DBG, 0x1); in _iqk_macbb_setting()
1687 rtw89_phy_write32_mask(rtwdev, R_P1_DBGMOD, B_P1_DBGMOD_ON, 0x1); in _iqk_macbb_setting()
1689 rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15, 0x1f); in _iqk_macbb_setting()
1691 rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15, 0x13); in _iqk_macbb_setting()
1692 rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_15, 0x0001); in _iqk_macbb_setting()
1694 rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_15, 0x0041); in _iqk_macbb_setting()
1695 rtw89_phy_write32_mask(rtwdev, R_P0_NRBW, B_P0_NRBW_RSTB, 0x1); in _iqk_macbb_setting()
1696 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RXK, 0x3333); in _iqk_macbb_setting()
1704 rtw89_phy_write32_mask(rtwdev, R_IQKINF, MASKDWORD, 0x0); in _iqk_init()
1716 iqk_info->iqk_times = 0x0; in _iqk_init()
1718 for (idx = 0; idx < RTW89_IQK_CHS_NR; idx++) { in _iqk_init()
1719 iqk_info->iqk_channel[idx] = 0x0; in _iqk_init()
1720 for (path = 0; path < RTW8852BT_SS; path++) { in _iqk_init()
1725 iqk_info->iqk_mcc_ch[idx][path] = 0x0; in _iqk_init()
1726 iqk_info->iqk_table_idx[path] = 0x0; in _iqk_init()
1737 for (path = 0; path < RF_PATH_MAX; path++) { in _wait_rx_mode()
1774 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]Test Ver 0x%x\n", iqk_info->version); in _doiqk()
1840 dpk_cmd = (id << 8) | (0x19 + (path << 4)); in _dpk_one_shot()
1843 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val == 0x55, in _dpk_one_shot()
1850 rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, MASKDWORD, 0x00030000); in _dpk_one_shot()
1852 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val == 0x8000, in _dpk_one_shot()
1858 rtw89_phy_write32_mask(rtwdev, R_NCTL_N1, MASKBYTE0, 0x0); in _dpk_one_shot()
1860 "[DPK] one-shot for %s = 0x%04x\n", in _dpk_one_shot()
1861 id == 0x06 ? "LBK_RXIQK" : in _dpk_one_shot()
1862 id == 0x10 ? "SYNC" : in _dpk_one_shot()
1863 id == 0x11 ? "MDPK_IDL" : in _dpk_one_shot()
1864 id == 0x12 ? "MDPK_MPA" : in _dpk_one_shot()
1865 id == 0x13 ? "GAIN_LOSS" : in _dpk_one_shot()
1866 id == 0x14 ? "PWR_CAL" : in _dpk_one_shot()
1867 id == 0x15 ? "DPK_RXAGC" : in _dpk_one_shot()
1868 id == 0x16 ? "KIP_PRESET" : in _dpk_one_shot()
1869 id == 0x17 ? "KIP_RESTORE" : in _dpk_one_shot()
1876 rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_LV, 0x0); in _dpk_rx_dck()
1877 rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_LV, 0x1); in _dpk_rx_dck()
1901 dpk->bp[path][kidx].band == 0 ? "2G" : in _dpk_information()
1904 dpk->bp[path][kidx].bw == 0 ? "20M" : in _dpk_information()
1921 rtw89_phy_write32_mask(rtwdev, R_NCTL_RPT, MASKDWORD, 0x00000000); in _dpk_kip_restore()
1922 rtw89_phy_write32_mask(rtwdev, R_KIP_SYSCFG, MASKDWORD, 0x80000000); in _dpk_kip_restore()
1926 B_DPD_COM_OF, 0x1); in _dpk_kip_restore()
1934 rtw89_phy_write32_mask(rtwdev, R_MDPK_RX_DCK, B_MDPK_RX_DCK_EN, 0x1); in _dpk_lbk_rxiqk()
1935 rtw89_phy_write32_mask(rtwdev, R_IQK_RES + (path << 8), B_IQK_RES_RXCFIR, 0x0); in _dpk_lbk_rxiqk()
1938 rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASKMODE, 0xd); in _dpk_lbk_rxiqk()
1939 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_PLLEN, 0x1); in _dpk_lbk_rxiqk()
1941 if (cur_rxbb >= 0x11) in _dpk_lbk_rxiqk()
1942 rtw89_write_rf(rtwdev, path, RR_TXIQK, RR_TXIQK_ATT1, 0x13); in _dpk_lbk_rxiqk()
1943 else if (cur_rxbb <= 0xa) in _dpk_lbk_rxiqk()
1944 rtw89_write_rf(rtwdev, path, RR_TXIQK, RR_TXIQK_ATT1, 0x00); in _dpk_lbk_rxiqk()
1946 rtw89_write_rf(rtwdev, path, RR_TXIQK, RR_TXIQK_ATT1, 0x05); in _dpk_lbk_rxiqk()
1948 rtw89_write_rf(rtwdev, path, RR_XGLNA2, RR_XGLNA2_SW, 0x0); in _dpk_lbk_rxiqk()
1949 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x0); in _dpk_lbk_rxiqk()
1950 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RFREG_MASK, 0x80014); in _dpk_lbk_rxiqk()
1954 rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x1); in _dpk_lbk_rxiqk()
1955 rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_RXT, 0x025); in _dpk_lbk_rxiqk()
1959 rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x0); in _dpk_lbk_rxiqk()
1961 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_PLLEN, 0x0); in _dpk_lbk_rxiqk()
1962 rtw89_phy_write32_mask(rtwdev, R_MDPK_RX_DCK, B_MDPK_RX_DCK_EN, 0x0); in _dpk_lbk_rxiqk()
1963 rtw89_phy_write32_mask(rtwdev, R_KPATH_CFG, B_KPATH_CFG_ED, 0x0); in _dpk_lbk_rxiqk()
1964 rtw89_phy_write32_mask(rtwdev, R_LOAD_COEF + (path << 8), B_LOAD_COEF_DI, 0x1); in _dpk_lbk_rxiqk()
1965 rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASKMODE, 0x5); in _dpk_lbk_rxiqk()
1974 rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASK, 0x50220); in _dpk_rf_setting()
1975 rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_FATT, 0xf2); in _dpk_rf_setting()
1976 rtw89_write_rf(rtwdev, path, RR_LUTDBG, RR_LUTDBG_TIA, 0x1); in _dpk_rf_setting()
1977 rtw89_write_rf(rtwdev, path, RR_TIA, RR_TIA_N6, 0x1); in _dpk_rf_setting()
1979 rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASK, 0x50220); in _dpk_rf_setting()
1980 rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RAA2_SWATT, 0x5); in _dpk_rf_setting()
1981 rtw89_write_rf(rtwdev, path, RR_LUTDBG, RR_LUTDBG_TIA, 0x1); in _dpk_rf_setting()
1982 rtw89_write_rf(rtwdev, path, RR_TIA, RR_TIA_N6, 0x1); in _dpk_rf_setting()
1983 rtw89_write_rf(rtwdev, path, RR_RXA_LNA, RFREG_MASK, 0x920FC); in _dpk_rf_setting()
1984 rtw89_write_rf(rtwdev, path, RR_XALNA2, RFREG_MASK, 0x002C0); in _dpk_rf_setting()
1985 rtw89_write_rf(rtwdev, path, RR_IQGEN, RFREG_MASK, 0x38800); in _dpk_rf_setting()
1988 rtw89_write_rf(rtwdev, path, RR_RCKD, RR_RCKD_BW, 0x1); in _dpk_rf_setting()
1990 rtw89_write_rf(rtwdev, path, RR_BTC, RR_BTC_RXBB, 0x0); in _dpk_rf_setting()
1998 B_RXIQC_BYPASS2, 0x1); in _dpk_bypass_rxcfir()
2000 B_RXIQC_BYPASS, 0x1); in _dpk_bypass_rxcfir()
2003 B_RXIQC_BYPASS2, 0x0); in _dpk_bypass_rxcfir()
2005 B_RXIQC_BYPASS, 0x0); in _dpk_bypass_rxcfir()
2015 rtw89_phy_write32_mask(rtwdev, R_TPG_MOD, B_TPG_MOD_F, 0x0); in _dpk_tpg_sel()
2017 rtw89_phy_write32_mask(rtwdev, R_TPG_MOD, B_TPG_MOD_F, 0x2); in _dpk_tpg_sel()
2019 rtw89_phy_write32_mask(rtwdev, R_TPG_MOD, B_TPG_MOD_F, 0x1); in _dpk_tpg_sel()
2031 val = 0x80 + kidx * 0x20 + gain * 0x10; in _dpk_table_select()
2034 "[DPK] table select for Kidx[%d], Gain[%d] (0x%x)\n", kidx, in _dpk_table_select()
2048 rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, B_KIP_RPT1_SEL, 0x0); in _dpk_sync_check()
2061 rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, B_KIP_RPT1_SEL, 0x9); in _dpk_sync_check()
2093 rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, B_KIP_RPT1_SEL, 0x0); in _dpk_dgain_read()
2097 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] DGain = 0x%x\n", dgain); in _dpk_dgain_read()
2105 0xbf1, 0xaa5, 0x97d, 0x875, 0x789, 0x6b7, 0x5fc, 0x556, in _dpk_dgain_mapping()
2106 0x4c1, 0x43d, 0x3c7, 0x35e, 0x2ac, 0x262, 0x220 in _dpk_dgain_mapping()
2110 if (dgain >= bnd[0]) in _dpk_dgain_mapping()
2111 offset = 0x6; in _dpk_dgain_mapping()
2112 else if (bnd[0] > dgain && dgain >= bnd[1]) in _dpk_dgain_mapping()
2113 offset = 0x6; in _dpk_dgain_mapping()
2115 offset = 0x5; in _dpk_dgain_mapping()
2117 offset = 0x4; in _dpk_dgain_mapping()
2119 offset = 0x3; in _dpk_dgain_mapping()
2121 offset = 0x2; in _dpk_dgain_mapping()
2123 offset = 0x1; in _dpk_dgain_mapping()
2125 offset = 0x0; in _dpk_dgain_mapping()
2127 offset = 0xff; in _dpk_dgain_mapping()
2129 offset = 0xfe; in _dpk_dgain_mapping()
2131 offset = 0xfd; in _dpk_dgain_mapping()
2133 offset = 0xfc; in _dpk_dgain_mapping()
2135 offset = 0xfb; in _dpk_dgain_mapping()
2137 offset = 0xfa; in _dpk_dgain_mapping()
2139 offset = 0xf9; in _dpk_dgain_mapping()
2141 offset = 0xf8; in _dpk_dgain_mapping()
2143 offset = 0x0; in _dpk_dgain_mapping()
2152 rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, B_KIP_RPT1_SEL, 0x6); in _dpk_gainloss_read()
2153 rtw89_phy_write32_mask(rtwdev, R_DPK_CFG2, B_DPK_CFG2_ST, 0x1); in _dpk_gainloss_read()
2163 rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, B_KIP_RPT1_SEL, 0x6); in _dpk_gainloss()
2164 rtw89_phy_write32_mask(rtwdev, R_DPK_CFG2, B_DPK_CFG2_ST, 0x1); in _dpk_gainloss()
2177 rtw89_phy_write32_mask(rtwdev, R_NCTL_RPT, MASKDWORD, 0x00000080); in _dpk_kip_pwr_clk_on()
2178 rtw89_phy_write32_mask(rtwdev, R_KIP_SYSCFG, MASKDWORD, 0x807f030a); in _dpk_kip_pwr_clk_on()
2179 rtw89_phy_write32_mask(rtwdev, R_CFIR_SYS + (path << 8), MASKDWORD, 0xce000a08); in _dpk_kip_pwr_clk_on()
2192 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] Set TxAGC = 0x%x\n", txagc); in _dpk_txagc_check_8852bt()
2204 rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x1); in _dpk_kip_set_txagc()
2206 rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x0); in _dpk_kip_set_txagc()
2208 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] set TXAGC = 0x%x\n", txagc); in _dpk_kip_set_txagc()
2214 rtw89_phy_write32_mask(rtwdev, R_KIP_MOD, B_KIP_MOD, 0x50220); in _dpk_kip_set_rxagc()
2215 rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x1); in _dpk_kip_set_rxagc()
2217 rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x0); in _dpk_kip_set_rxagc()
2234 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] tmp_txagc (GL=%d) = 0x%x\n", in _dpk_set_offset()
2242 u32 val1_i = 0, val1_q = 0, val2_i = 0, val2_q = 0; in _dpk_pas_read()
2245 rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, MASKBYTE2, 0x06); in _dpk_pas_read()
2246 rtw89_phy_write32_mask(rtwdev, R_DPK_CFG2, B_DPK_CFG2_ST, 0x0); in _dpk_pas_read()
2247 rtw89_phy_write32_mask(rtwdev, R_DPK_CFG3, MASKBYTE2, 0x08); in _dpk_pas_read()
2250 rtw89_phy_write32_mask(rtwdev, R_DPK_CFG3, MASKBYTE3, 0x00); in _dpk_pas_read()
2256 rtw89_phy_write32_mask(rtwdev, R_DPK_CFG3, MASKBYTE3, 0x1f); in _dpk_pas_read()
2262 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] PAS_delta = 0x%x\n", in _dpk_pas_read()
2266 for (i = 0; i < 32; i++) { in _dpk_pas_read()
2269 "[DPK] PAS_Read[%02d]= 0x%08x\n", i, in _dpk_pas_read()
2287 u8 goout = 0, agc_cnt = 0, limited_rxbb = 0, gl_cnt = 0; in _dpk_agc()
2288 u8 tmp_txagc, tmp_rxbb, tmp_gl_idx = 0; in _dpk_agc()
2291 s8 offset = 0; in _dpk_agc()
2292 u16 dgain = 0; in _dpk_agc()
2304 if (agc_cnt == 0) { in _dpk_agc()
2313 tmp_txagc = 0xff; in _dpk_agc()
2321 if (loss_only == 1 || limited_rxbb == 1 || offset == 0) in _dpk_agc()
2329 if (tmp_rxbb + offset > 0x1f) { in _dpk_agc()
2330 tmp_rxbb = 0x1f; in _dpk_agc()
2332 } else if (tmp_rxbb + offset < 0) { in _dpk_agc()
2333 tmp_rxbb = 0; in _dpk_agc()
2341 "[DPK] Adjust RXBB (%d) = 0x%x\n", offset, tmp_rxbb); in _dpk_agc()
2357 if ((tmp_gl_idx == 0 && _dpk_pas_read(rtwdev, path, true)) || in _dpk_agc()
2360 else if (tmp_gl_idx == 0) in _dpk_agc()
2368 if (tmp_txagc == 0x2e || in _dpk_agc()
2375 tmp_txagc, 0x3); in _dpk_agc()
2382 if (tmp_txagc == 0x3f || tmp_txagc == dpk->max_dpk_txagc[path]) { in _dpk_agc()
2388 tmp_txagc, 0xfe); in _dpk_agc()
2405 } while (!goout && agc_cnt < 6 && limit-- > 0); in _dpk_agc()
2411 "[DPK] Txagc / RXBB for DPK = 0x%x / 0x%x\n", tmp_txagc, tmp_rxbb); in _dpk_agc()
2422 case 0: /* (5,3,1) */ in _dpk_set_mdpd_para()
2424 rtw89_phy_write32_mask(rtwdev, R_LDL_NORM, B_LDL_NORM_PN, 0x3); in _dpk_set_mdpd_para()
2425 rtw89_phy_write32_mask(rtwdev, R_MDPK_SYNC, B_MDPK_SYNC_MAN, 0x1); in _dpk_set_mdpd_para()
2426 dpk->dpk_order[path] = 0x3; in _dpk_set_mdpd_para()
2428 case 1: /* (5,3,0) */ in _dpk_set_mdpd_para()
2430 rtw89_phy_write32_mask(rtwdev, R_LDL_NORM, B_LDL_NORM_PN, 0x0); in _dpk_set_mdpd_para()
2431 rtw89_phy_write32_mask(rtwdev, R_MDPK_SYNC, B_MDPK_SYNC_MAN, 0x0); in _dpk_set_mdpd_para()
2432 dpk->dpk_order[path] = 0x1; in _dpk_set_mdpd_para()
2434 case 2: /* (5,0,0) */ in _dpk_set_mdpd_para()
2436 rtw89_phy_write32_mask(rtwdev, R_LDL_NORM, B_LDL_NORM_PN, 0x0); in _dpk_set_mdpd_para()
2437 rtw89_phy_write32_mask(rtwdev, R_MDPK_SYNC, B_MDPK_SYNC_MAN, 0x0); in _dpk_set_mdpd_para()
2438 dpk->dpk_order[path] = 0x0; in _dpk_set_mdpd_para()
2442 "[DPK] Wrong MDPD order!!(0x%x)\n", order); in _dpk_set_mdpd_para()
2447 order == 0x0 ? "(5,3,1)" : in _dpk_set_mdpd_para()
2448 order == 0x1 ? "(5,3,0)" : "(5,0,0)"); in _dpk_set_mdpd_para()
2451 "[DPK] Set MDPD order to 0x%x for IDL\n", order); in _dpk_set_mdpd_para()
2461 _dpk_set_mdpd_para(rtwdev, path, 0x2); in _dpk_idl_mpa()
2463 _dpk_set_mdpd_para(rtwdev, path, 0x0); in _dpk_idl_mpa()
2473 u16 pwsf = 0x78; in _dpk_fill_result()
2478 "[DPK] Fill txagc/ pwsf/ gs = 0x%x/ 0x%x/ 0x%x\n", in _dpk_fill_result()
2483 0x3F << ((gain << 3) + (kidx << 4)), txagc); in _dpk_fill_result()
2487 0x1FF << (gain << 4), pwsf); in _dpk_fill_result()
2489 rtw89_phy_write32_mask(rtwdev, R_LOAD_COEF + (path << 8), B_LOAD_COEF_MDPD, 0x1); in _dpk_fill_result()
2490 rtw89_phy_write32_mask(rtwdev, R_LOAD_COEF + (path << 8), B_LOAD_COEF_MDPD, 0x0); in _dpk_fill_result()
2493 if (dpk->dpk_gs[phy] == 0x7f) in _dpk_fill_result()
2496 MASKDWORD, 0x007f7f7f); in _dpk_fill_result()
2500 MASKDWORD, 0x005b5b5b); in _dpk_fill_result()
2505 rtw89_phy_write32_mask(rtwdev, R_DPD_V1 + (path << 8), MASKDWORD, 0x0); in _dpk_fill_result()
2506 rtw89_phy_write32_mask(rtwdev, R_MDPK_SYNC, B_MDPK_SYNC_SEL, 0x0); in _dpk_fill_result()
2520 for (idx = 0; idx < RTW89_DPK_BKUP_NUM; idx++) { in _dpk_reload_check()
2540 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x1); in _rf_direct_cntrl()
2542 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0); in _rf_direct_cntrl()
2549 rtw89_write_rf(rtwdev, path, RR_BBDC, RR_BBDC_SEL, 0x1); in _drf_direct_cntrl()
2551 rtw89_write_rf(rtwdev, path, RR_BBDC, RR_BBDC_SEL, 0x0); in _drf_direct_cntrl()
2559 u8 txagc = 0x38, kidx = dpk->cur_idx[path]; in _dpk_main()
2580 if (txagc == 0xff) { in _dpk_main()
2594 dpk->bp[path][kidx].path_ok = 0; in _dpk_main()
2618 for (path = 0; path < DPK_RF_PATH_MAX_8852BT; path++) { in _dpk_cal_select()
2620 if (!reloaded[path] && dpk->bp[path][0].ch != 0) in _dpk_cal_select()
2629 for (path = 0; path < DPK_RF_PATH_MAX_8852BT; path++) { in _dpk_cal_select()
2638 for (path = 0; path < DPK_RF_PATH_MAX_8852BT; path++) in _dpk_cal_select()
2647 for (path = 0; path < DPK_RF_PATH_MAX_8852BT; path++) { in _dpk_cal_select()
2683 for (path = 0; path < RTW8852BT_SS; path++) { in _dpk_force_bypass()
2692 s8 txagc_bb, txagc_bb_tp, ini_diff = 0, txagc_ofst; in _dpk_track()
2700 for (path = 0; path < RF_PATH_NUM_8852BT; path++) { in _dpk_track()
2727 "[DPK_TRK] txagc_RF / track_idx = 0x%x / %d\n", in _dpk_track()
2738 "[DPK_TRK] txagc_bb_tp / txagc_bb = 0x%x / 0x%x\n", in _dpk_track()
2750 if (tmp == 0x1) { in _dpk_track()
2751 txagc_ofst = 0; in _dpk_track()
2762 if (tmp == 0x0) { in _dpk_track()
2763 pwsf[0] = dpk->bp[path][kidx].pwsf + in _dpk_track()
2768 pwsf[0] = dpk->bp[path][kidx].pwsf + ini_diff; in _dpk_track()
2772 pwsf[0] = (dpk->bp[path][kidx].pwsf + delta_ther[path]) & 0x1ff; in _dpk_track()
2773 pwsf[1] = (dpk->bp[path][kidx].pwsf + delta_ther[path]) & 0x1ff; in _dpk_track()
2779 "[DPK_TRK] New pwsf[0] / pwsf[1] = 0x%x / 0x%x\n", in _dpk_track()
2780 pwsf[0], pwsf[1]); in _dpk_track()
2784 B_DPD_BND_0, pwsf[0]); in _dpk_track()
2803 /* move dpd backoff to bb, and set dpd backoff to 0 */ in _set_dpd_backoff()
2804 dpk->dpk_gs[phy] = 0x7f; in _set_dpd_backoff()
2805 for (path = 0; path < RF_PATH_NUM_8852BT; path++) { in _set_dpd_backoff()
2810 B_DPD_CFG, 0x7f7f7f); in _set_dpd_backoff()
2812 "[RFK] Set S%d DPD backoff to 0dB\n", path); in _set_dpd_backoff()
2815 dpk->dpk_gs[phy] = 0x5b; in _set_dpd_backoff()
2821 rtw89_phy_write32_mask(rtwdev, R_DPD_CH0A, BIT(24), 0x0); in _tssi_dpk_off()
2822 rtw89_phy_write32_mask(rtwdev, R_DPD_CH0B, BIT(24), 0x0); in _tssi_dpk_off()
2831 rtw89_write_rf(rtwdev, path, RR_TXPOW, RR_TXPOW_TXG, 0x1); in _tssi_rf_setting()
2833 rtw89_write_rf(rtwdev, path, RR_TXPOW, RR_TXPOW_TXA, 0x1); in _tssi_rf_setting()
2844 rtw89_phy_write32_mask(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_BW80, 0x1); in _tssi_set_sys()
2846 rtw89_phy_write32_mask(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_BW80, 0x0); in _tssi_set_sys()
2891 u32 __val = 0; \ in _tssi_set_tmeter_tbl()
2892 for (__i = 0; __i < 4; __i++) { \ in _tssi_set_tmeter_tbl()
2906 u8 thermal = 0xff; in _tssi_set_tmeter_tbl()
2907 s8 thm_ofst[64] = {0}; in _tssi_set_tmeter_tbl()
2908 u32 tmp = 0; in _tssi_set_tmeter_tbl()
2914 thm_up_a = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_2GA_P][0]; in _tssi_set_tmeter_tbl()
2915 thm_down_a = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_2GA_N][0]; in _tssi_set_tmeter_tbl()
2916 thm_up_b = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_2GB_P][0]; in _tssi_set_tmeter_tbl()
2917 thm_down_b = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_2GB_N][0]; in _tssi_set_tmeter_tbl()
2920 thm_up_a = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_P][0]; in _tssi_set_tmeter_tbl()
2921 thm_down_a = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_N][0]; in _tssi_set_tmeter_tbl()
2922 thm_up_b = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_P][0]; in _tssi_set_tmeter_tbl()
2923 thm_down_b = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_N][0]; in _tssi_set_tmeter_tbl()
2943 "[TSSI] ch=%d thermal_pathA=0x%x\n", ch, thermal); in _tssi_set_tmeter_tbl()
2945 rtw89_phy_write32_mask(rtwdev, R_P0_TMETER, B_P0_TMETER_DIS, 0x0); in _tssi_set_tmeter_tbl()
2946 rtw89_phy_write32_mask(rtwdev, R_P0_TMETER, B_P0_TMETER_TRK, 0x1); in _tssi_set_tmeter_tbl()
2948 if (thermal == 0xff) { in _tssi_set_tmeter_tbl()
2952 for (i = 0; i < 64; i += 4) { in _tssi_set_tmeter_tbl()
2953 rtw89_phy_write32(rtwdev, R_P0_TSSI_BASE + i, 0x0); in _tssi_set_tmeter_tbl()
2956 "[TSSI] write 0x%x val=0x%08x\n", in _tssi_set_tmeter_tbl()
2957 R_P0_TSSI_BASE + i, 0x0); in _tssi_set_tmeter_tbl()
2966 i = 0; in _tssi_set_tmeter_tbl()
2967 for (j = 0; j < 32; j++) in _tssi_set_tmeter_tbl()
2978 for (i = 0; i < 64; i += 4) { in _tssi_set_tmeter_tbl()
2983 "[TSSI] write 0x%x val=0x%08x\n", in _tssi_set_tmeter_tbl()
2984 0x5c00 + i, tmp); in _tssi_set_tmeter_tbl()
2987 rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, R_P0_RFCTM_RDY, 0x1); in _tssi_set_tmeter_tbl()
2988 rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, R_P0_RFCTM_RDY, 0x0); in _tssi_set_tmeter_tbl()
2994 "[TSSI] ch=%d thermal_pathB=0x%x\n", ch, thermal); in _tssi_set_tmeter_tbl()
2996 rtw89_phy_write32_mask(rtwdev, R_P1_TMETER, B_P1_TMETER_DIS, 0x0); in _tssi_set_tmeter_tbl()
2997 rtw89_phy_write32_mask(rtwdev, R_P1_TMETER, B_P1_TMETER_TRK, 0x1); in _tssi_set_tmeter_tbl()
2999 if (thermal == 0xff) { in _tssi_set_tmeter_tbl()
3003 for (i = 0; i < 64; i += 4) { in _tssi_set_tmeter_tbl()
3004 rtw89_phy_write32(rtwdev, R_TSSI_THOF + i, 0x0); in _tssi_set_tmeter_tbl()
3007 "[TSSI] write 0x%x val=0x%08x\n", in _tssi_set_tmeter_tbl()
3008 0x7c00 + i, 0x0); in _tssi_set_tmeter_tbl()
3017 i = 0; in _tssi_set_tmeter_tbl()
3018 for (j = 0; j < 32; j++) in _tssi_set_tmeter_tbl()
3029 for (i = 0; i < 64; i += 4) { in _tssi_set_tmeter_tbl()
3034 "[TSSI] write 0x%x val=0x%08x\n", in _tssi_set_tmeter_tbl()
3035 0x7c00 + i, tmp); in _tssi_set_tmeter_tbl()
3038 rtw89_phy_write32_mask(rtwdev, R_P1_RFCTM, R_P1_RFCTM_RDY, 0x1); in _tssi_set_tmeter_tbl()
3039 rtw89_phy_write32_mask(rtwdev, R_P1_RFCTM, R_P1_RFCTM_RDY, 0x0); in _tssi_set_tmeter_tbl()
3111 rtw89_phy_write32_mask(rtwdev, R_P0_TSSIC, B_P0_TSSIC_BYPASS, 0x0); in _tssi_set_tssi_track()
3113 rtw89_phy_write32_mask(rtwdev, R_P1_TSSIC, B_P1_TSSIC_BYPASS, 0x0); in _tssi_set_tssi_track()
3125 B_P0_TSSI_MV_MIX, 0x010); in _tssi_set_txagc_offset_mv_avg()
3128 B_P1_RFCTM_DEL, 0x010); in _tssi_set_txagc_offset_mv_avg()
3135 for (i = 0; i < RF_PATH_NUM_8852BT; i++) { in _tssi_enable()
3141 B_P0_TSSI_MV_CLR, 0x0); in _tssi_enable()
3143 B_P0_TSSI_EN, 0x0); in _tssi_enable()
3145 B_P0_TSSI_EN, 0x1); in _tssi_enable()
3147 RR_TXGA_V1_TRK_EN, 0x1); in _tssi_enable()
3149 B_P0_TSSI_RFC, 0x3); in _tssi_enable()
3152 B_P0_TSSI_OFT, 0xc0); in _tssi_enable()
3154 B_P0_TSSI_OFT_EN, 0x0); in _tssi_enable()
3156 B_P0_TSSI_OFT_EN, 0x1); in _tssi_enable()
3161 B_P1_TSSI_MV_CLR, 0x0); in _tssi_enable()
3163 B_P1_TSSI_EN, 0x0); in _tssi_enable()
3165 B_P1_TSSI_EN, 0x1); in _tssi_enable()
3167 RR_TXGA_V1_TRK_EN, 0x1); in _tssi_enable()
3169 B_P1_TSSI_RFC, 0x3); in _tssi_enable()
3172 B_P1_TSSI_OFT, 0xc0); in _tssi_enable()
3174 B_P1_TSSI_OFT_EN, 0x0); in _tssi_enable()
3176 B_P1_TSSI_OFT_EN, 0x1); in _tssi_enable()
3185 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_AVG, B_P0_TSSI_EN, 0x0); in _tssi_disable()
3186 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_RFC, 0x1); in _tssi_disable()
3187 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_MV_AVG, B_P0_TSSI_MV_CLR, 0x1); in _tssi_disable()
3188 rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_AVG, B_P1_TSSI_EN, 0x0); in _tssi_disable()
3189 rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_RFC, 0x1); in _tssi_disable()
3190 rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_MV_AVG, B_P1_TSSI_MV_CLR, 0x1); in _tssi_disable()
3200 return 0; in _tssi_get_cck_group()
3213 return 0; in _tssi_get_cck_group()
3226 return 0; in _tssi_get_ofdm_group()
3287 return 0; in _tssi_get_ofdm_group()
3294 return 0; in _tssi_get_trim_group()
3311 return 0; in _tssi_get_trim_group()
3327 "[TSSI][TRIM]: path=%d mcs group_idx=0x%x\n", path, gidx); in _tssi_get_ofdm_de()
3362 "[TSSI][TRIM]: path=%d mcs trim_group_idx=0x%x\n", in _tssi_get_ofdm_trim_de()
3406 "[TSSI][TRIM]: path=%d cck[%d]=0x%x trim=0x%x\n", in _tssi_set_efuse_to_de()
3413 "[TSSI] Set TSSI CCK DE 0x%x[21:12]=0x%x\n", in _tssi_set_efuse_to_de()
3423 "[TSSI][TRIM]: path=%d mcs=0x%x trim=0x%x\n", in _tssi_set_efuse_to_de()
3435 "[TSSI] Set TSSI MCS DE 0x%x[21:12]=0x%x\n", in _tssi_set_efuse_to_de()
3445 "[TSSI PA K]\n0x%x = 0x%08x\n0x%x = 0x%08x\n0x%x = 0x%08x\n0x%x = 0x%08x\n" in _tssi_alimentk_dump_result()
3446 "0x%x = 0x%08x\n0x%x = 0x%08x\n0x%x = 0x%08x\n0x%x = 0x%08x\n", in _tssi_alimentk_dump_result()
3489 tssi_info->alignment_value[path][band][0]); in _tssi_alimentk_done()
3532 for (i = 0; i < reg_num; i++) { in _tssi_backup_bb_registers()
3536 "[TSSI] Backup BB 0x%x = 0x%x\n", reg[i], in _tssi_backup_bb_registers()
3548 for (i = 0; i < reg_num; i++) { in _tssi_reload_bb_registers()
3552 "[TSSI] Reload BB 0x%x = 0x%x\n", reg[i], in _tssi_reload_bb_registers()
3570 channel_index = 0; in _tssi_ch_to_idx()
3584 for (j = 0; j < RTW8852BT_TSSI_PATH_NR; j++) { in _tssi_get_cw_report()
3585 rtw89_phy_write32_mask(rtwdev, _tssi_trigger[path], B_P0_TSSI_EN, 0x0); in _tssi_get_cw_report()
3586 rtw89_phy_write32_mask(rtwdev, _tssi_trigger[path], B_P0_TSSI_EN, 0x1); in _tssi_get_cw_report()
3592 "[TSSI PA K] 0x%x = 0x%08x path=%d\n", in _tssi_get_cw_report()
3595 if (j == 0) in _tssi_get_cw_report()
3609 for (k = 0; k < retry; k++) { in _tssi_get_cw_report()
3655 static const u32 bb_reg[8] = {0x5820, 0x7820, 0x4978, 0x58e4, in _tssi_alimentk()
3656 0x78e4, 0x49c0, 0x0d18, 0x0d80}; in _tssi_alimentk()
3700 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_AVG, B_P0_TSSI_AVG, 0x8); in _tssi_alimentk()
3701 rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_AVG, B_P1_TSSI_AVG, 0x8); in _tssi_alimentk()
3702 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_MV_AVG, B_P0_TSSI_MV_AVG, 0x2); in _tssi_alimentk()
3703 rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_MV_AVG, B_P1_TSSI_MV_AVG, 0x2); in _tssi_alimentk()
3709 for (j = 0; j < RTW8852BT_TSSI_PATH_NR; j++) { in _tssi_alimentk()
3718 tssi_alim_offset_1 = tssi_cw_rpt[0] - ((power[0] - power[1]) * 2) - in _tssi_alimentk()
3741 "[TSSI PA K] tssi_alim_offset = 0x%x 0x%x 0x%x 0x%x\n", in _tssi_alimentk()
3755 "[TSSI PA K] tssi_alim_offset = 0x%x 0x%x 0x%x 0x%x\n", in _tssi_alimentk()
3763 tssi_info->alignment_value[path][band][0] = in _tssi_alimentk()
3773 tssi_info->alignment_backup_by_ch[path][ch_idx][0] = in _tssi_alimentk()
3783 "[TSSI PA K] tssi_info->alignment_value[path=%d][band=%d][0], 0x%x = 0x%08x\n", in _tssi_alimentk()
3785 tssi_info->alignment_value[path][band][0]); in _tssi_alimentk()
3787 "[TSSI PA K] tssi_info->alignment_value[path=%d][band=%d][1], 0x%x = 0x%08x\n", in _tssi_alimentk()
3791 "[TSSI PA K] tssi_info->alignment_value[path=%d][band=%d][2], 0x%x = 0x%08x\n", in _tssi_alimentk()
3795 "[TSSI PA K] tssi_info->alignment_value[path=%d][band=%d][3], 0x%x = 0x%08x\n", in _tssi_alimentk()
3803 rtw8852bx_bb_tx_mode_switch(rtwdev, phy, 0); in _tssi_alimentk()
3819 for (path = 0; path < 2; path++) { in rtw8852bt_dpk_init()
3820 dpk->cur_idx[path] = 0; in rtw8852bt_dpk_init()
3821 dpk->max_dpk_txagc[path] = 0x3F; in rtw8852bt_dpk_init()
3833 for (path = 0; path < RF_PATH_NUM_8852BT; path++) in rtw8852bt_rck()
3839 u8 phy_map = rtw89_btc_phymap(rtwdev, RTW89_PHY_0, 0, chanctx_idx); in rtw8852bt_dack()
3849 u8 phy_map = rtw89_btc_phymap(rtwdev, phy_idx, 0, chanctx_idx); in rtw8852bt_iqk()
3866 u8 phy_map = rtw89_btc_phymap(rtwdev, phy_idx, 0, chanctx_idx); in rtw8852bt_rx_dck()
3883 "[DPK] ****** DPK Start (Ver: 0x%x) ******\n", RTW8852BT_DPK_VER); in rtw8852bt_dpk()
3994 "======>%s 1 SCAN_END Set 0x5818[7:0]=0x%x 0x7818[7:0]=0x%x\n", in rtw8852bt_tssi_default_txagc()
3999 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_OFT, 0xc0); in rtw8852bt_tssi_default_txagc()
4000 rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_OFT, 0xc0); in rtw8852bt_tssi_default_txagc()
4001 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_OFT_EN, 0x0); in rtw8852bt_tssi_default_txagc()
4002 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_OFT_EN, 0x1); in rtw8852bt_tssi_default_txagc()
4003 rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_OFT_EN, 0x0); in rtw8852bt_tssi_default_txagc()
4004 rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_OFT_EN, 0x1); in rtw8852bt_tssi_default_txagc()
4010 "======>%s 2 SCAN_END Set 0x5818[7:0]=0x%x 0x7818[7:0]=0x%x\n", in rtw8852bt_tssi_default_txagc()
4066 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RFK] set %x at path%d, %x =0x%x\n", in _bw_setting()
4085 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LCK_TRG, RR_LCK_TRGSEL, 0x1); in _set_s0_arfc18()
4088 ret = read_poll_timeout_atomic(rtw89_read_rf, tmp, tmp == 0, 1, 1000, in _set_s0_arfc18()
4093 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LCK_TRG, RR_LCK_TRGSEL, 0x0); in _set_s0_arfc18()
4101 if (rtw89_read_rf(rtwdev, RF_PATH_A, RR_SYNFB, RR_SYNFB_LK) == 0) { in _lck_check()
4104 rtw89_write_rf(rtwdev, RF_PATH_A, RR_MMD, RR_MMD_RST_EN, 0x1); in _lck_check()
4105 rtw89_write_rf(rtwdev, RF_PATH_A, RR_MMD, RR_MMD_RST_SYN, 0x0); in _lck_check()
4106 rtw89_write_rf(rtwdev, RF_PATH_A, RR_MMD, RR_MMD_RST_SYN, 0x1); in _lck_check()
4107 rtw89_write_rf(rtwdev, RF_PATH_A, RR_MMD, RR_MMD_RST_EN, 0x0); in _lck_check()
4112 if (rtw89_read_rf(rtwdev, RF_PATH_A, RR_SYNFB, RR_SYNFB_LK) == 0) { in _lck_check()
4113 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[LCK]re-set RF 0x18\n"); in _lck_check()
4115 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LCK_TRG, RR_LCK_TRGSEL, 0x1); in _lck_check()
4118 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LCK_TRG, RR_LCK_TRGSEL, 0x0); in _lck_check()
4121 if (rtw89_read_rf(rtwdev, RF_PATH_A, RR_SYNFB, RR_SYNFB_LK) == 0) { in _lck_check()
4129 rtw89_write_rf(rtwdev, RF_PATH_A, RR_SYNLUT, RR_SYNLUT_MOD, 0x1); in _lck_check()
4130 rtw89_write_rf(rtwdev, RF_PATH_A, RR_POW, RR_POW_SYN, 0x0); in _lck_check()
4131 rtw89_write_rf(rtwdev, RF_PATH_A, RR_POW, RR_POW_SYN, 0x3); in _lck_check()
4132 rtw89_write_rf(rtwdev, RF_PATH_A, RR_SYNLUT, RR_SYNLUT_MOD, 0x0); in _lck_check()
4134 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LCK_TRG, RR_LCK_TRGSEL, 0x1); in _lck_check()
4137 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LCK_TRG, RR_LCK_TRGSEL, 0x0); in _lck_check()
4139 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[LCK]0xb2=%x, 0xc5=%x\n", in _lck_check()
4151 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LDO, RR_LDO_SEL, 0x1); in _set_ch()
4185 rtw89_write_rf(rtwdev, path, RR_LCKST, RR_LCKST_BIN, 0); in _ch_setting()
4189 "[RFK]CH: %d for Path-%d, reg0x%x = 0x%x\n", in _ch_setting()
4205 rtw89_write_rf(rtwdev, path, RR_LUTWE2, RR_LUTWE2_RTXBW, 0x1); in _set_rxbb_bw()
4206 rtw89_write_rf(rtwdev, path, RR_LUTWA, RR_LUTWA_M2, 0x12); in _set_rxbb_bw()
4209 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RR_LUTWD0_LB, 0x1b); in _set_rxbb_bw()
4211 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RR_LUTWD0_LB, 0x13); in _set_rxbb_bw()
4213 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RR_LUTWD0_LB, 0xb); in _set_rxbb_bw()
4215 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RR_LUTWD0_LB, 0x3); in _set_rxbb_bw()
4217 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RFK] set S%d RXBB BW 0x3F = 0x%x\n", in _set_rxbb_bw()
4220 rtw89_write_rf(rtwdev, path, RR_LUTWE2, RR_LUTWE2_RTXBW, 0x0); in _set_rxbb_bw()
4230 for (path = 0; path < RF_PATH_NUM_8852BT; path++) { in _rxbb_bw()