Lines Matching +full:0 +full:x262
16 #define MIN_FW_MAJOR_VERSION 0
23 #define PCI_DEVICE_ID_META_FBNIC_ASIC 0x0013
29 #define FBNIC_TWD_L2_HLEN_MASK DESC_GENMASK(5, 0)
33 FBNIC_TWD_L3_TYPE_OTHER = 0,
43 FBNIC_TWD_L4_TYPE_OTHER = 0,
62 FBNIC_TWD_TYPE_META = 0,
71 #define FBNIC_TWD_TS_MASK DESC_GENMASK(39, 0)
72 #define FBNIC_TWD_ADDR_MASK DESC_GENMASK(45, 0)
76 #define FBNIC_TCD_TYPE0_HEAD0_MASK DESC_GENMASK(15, 0)
79 #define FBNIC_TCD_TYPE1_TS_MASK DESC_GENMASK(39, 0)
87 FBNIC_TCD_TYPE_0 = 0,
99 * address with the lowest 12 bits being reserved 0 due to the fact that
127 FBNIC_RCD_TYPE_HDR_AL = 0,
136 #define FBNIC_RCD_AL_BUFF_ID_MASK DESC_GENMASK(15, 0)
148 FBNIC_RCD_HDR_AL_DMA_HINT_NONE = 0,
155 #define FBNIC_RCD_OPT_META_TS_MASK DESC_GENMASK(39, 0)
162 #define FBNIC_RCD_META_RSS_HASH_MASK DESC_GENMASK(31, 0)
166 FBNIC_RCD_META_L3_TYPE_OTHER = 0,
174 FBNIC_RCD_META_L4_TYPE_OTHER = 0,
196 #define FBNIC_CSR_START_INTR 0x00000 /* CSR section delimiter */
197 #define FBNIC_INTR_STATUS(n) (0x00000 + (n)) /* 0x00000 + 4*n */
199 #define FBNIC_INTR_MASK(n) (0x00008 + (n)) /* 0x00020 + 4*n */
201 #define FBNIC_INTR_SET(n) (0x00010 + (n)) /* 0x00040 + 4*n */
203 #define FBNIC_INTR_CLEAR(n) (0x00018 + (n)) /* 0x00060 + 4*n */
205 #define FBNIC_INTR_SW_STATUS(n) (0x00020 + (n)) /* 0x00080 + 4*n */
207 #define FBNIC_INTR_SW_AC_MODE(n) (0x00028 + (n)) /* 0x000a0 + 4*n */
209 #define FBNIC_INTR_MASK_SET(n) (0x00030 + (n)) /* 0x000c0 + 4*n */
211 #define FBNIC_INTR_MASK_CLEAR(n) (0x00038 + (n)) /* 0x000e0 + 4*n */
214 #define FBNIC_INTR_MSIX_CTRL(n) (0x00040 + (n)) /* 0x00100 + 4*n */
215 #define FBNIC_INTR_MSIX_CTRL_VECTOR_MASK CSR_GENMASK(7, 0)
221 #define FBNIC_CSR_END_INTR 0x0005f /* CSR section delimiter */
224 #define FBNIC_CSR_START_INTR_CQ 0x00400 /* CSR section delimiter */
226 (0x00400 + 4 * (n)) /* 0x01000 + 16*n */
228 #define FBNIC_INTR_CQ_REARM_RCQ_TIMEOUT CSR_GENMASK(13, 0)
236 (0x00401 + 4 * (n)) /* 0x01004 + 16*n */
239 (0x00402 + 4 * (n)) /* 0x01008 + 16*n */
241 #define FBNIC_CSR_END_INTR_CQ 0x007fe /* CSR section delimiter */
244 #define FBNIC_CSR_START_QM_TX 0x00800 /* CSR section delimiter */
245 #define FBNIC_QM_TWQ_IDLE(n) (0x00800 + (n)) /* 0x02000 + 4*n */
247 #define FBNIC_QM_TWQ_DEFAULT_META_L 0x00818 /* 0x02060 */
248 #define FBNIC_QM_TWQ_DEFAULT_META_H 0x00819 /* 0x02064 */
250 #define FBNIC_QM_TQS_CTL0 0x0081b /* 0x0206c */
251 #define FBNIC_QM_TQS_CTL0_LSO_TS_MASK CSR_BIT(0)
253 FBNIC_QM_TQS_CTL0_LSO_TS_FIRST = 0,
262 #define FBNIC_QM_TQS_CTL1 0x0081c /* 0x02070 */
263 #define FBNIC_QM_TQS_CTL1_MC_MAX_CREDITS CSR_GENMASK(7, 0)
265 #define FBNIC_QM_TQS_MTU_CTL0 0x0081d /* 0x02074 */
266 #define FBNIC_QM_TQS_MTU_CTL1 0x0081e /* 0x02078 */
267 #define FBNIC_QM_TQS_MTU_CTL1_BULK CSR_GENMASK(13, 0)
268 #define FBNIC_QM_TCQ_IDLE(n) (0x00821 + (n)) /* 0x02084 + 4*n */
270 #define FBNIC_QM_TCQ_CTL0 0x0082d /* 0x020b4 */
271 #define FBNIC_QM_TCQ_CTL0_COAL_WAIT CSR_GENMASK(15, 0)
273 #define FBNIC_QM_TQS_IDLE(n) (0x00830 + (n)) /* 0x020c0 + 4*n */
275 #define FBNIC_QM_TQS_EDT_TS_RANGE 0x00849 /* 0x2124 */
276 #define FBNIC_QM_TDE_IDLE(n) (0x00853 + (n)) /* 0x0214c + 4*n */
278 #define FBNIC_QM_TNI_TDF_CTL 0x0086c /* 0x021b0 */
279 #define FBNIC_QM_TNI_TDF_CTL_MRRS CSR_GENMASK(1, 0)
283 #define FBNIC_QM_TNI_TDE_CTL 0x0086d /* 0x021b4 */
284 #define FBNIC_QM_TNI_TDE_CTL_MRRS CSR_GENMASK(1, 0)
289 #define FBNIC_QM_TNI_TCM_CTL 0x0086e /* 0x021b8 */
290 #define FBNIC_QM_TNI_TCM_CTL_MPS CSR_GENMASK(1, 0)
294 #define FBNIC_CSR_END_QM_TX 0x00873 /* CSR section delimiter */
297 #define FBNIC_CSR_START_QM_RX 0x00c00 /* CSR section delimiter */
298 #define FBNIC_QM_RCQ_IDLE(n) (0x00c00 + (n)) /* 0x03000 + 4*n */
300 #define FBNIC_QM_RCQ_CTL0 0x00c0c /* 0x03030 */
301 #define FBNIC_QM_RCQ_CTL0_COAL_WAIT CSR_GENMASK(15, 0)
303 #define FBNIC_QM_HPQ_IDLE(n) (0x00c0f + (n)) /* 0x0303c + 4*n */
305 #define FBNIC_QM_PPQ_IDLE(n) (0x00c13 + (n)) /* 0x0304c + 4*n */
307 #define FBNIC_QM_RNI_RBP_CTL 0x00c2d /* 0x030b4 */
308 #define FBNIC_QM_RNI_RBP_CTL_MRRS CSR_GENMASK(1, 0)
312 #define FBNIC_QM_RNI_RDE_CTL 0x00c2e /* 0x030b8 */
313 #define FBNIC_QM_RNI_RDE_CTL_MPS CSR_GENMASK(1, 0)
317 #define FBNIC_QM_RNI_RCM_CTL 0x00c2f /* 0x030bc */
318 #define FBNIC_QM_RNI_RCM_CTL_MPS CSR_GENMASK(1, 0)
322 #define FBNIC_CSR_END_QM_RX 0x00c34 /* CSR section delimiter */
325 #define FBNIC_CSR_START_TCE 0x04000 /* CSR section delimiter */
326 #define FBNIC_TCE_REG_BASE 0x04000 /* 0x10000 */
328 #define FBNIC_TCE_LSO_CTRL 0x04000 /* 0x10000 */
329 #define FBNIC_TCE_LSO_CTRL_TCPF_CLR_1ST CSR_GENMASK(8, 0)
334 #define FBNIC_TCE_CSO_CTRL 0x04001 /* 0x10004 */
335 #define FBNIC_TCE_CSO_CTRL_TCP_ZERO_CSUM CSR_BIT(0)
337 #define FBNIC_TCE_TXB_CTRL 0x04002 /* 0x10008 */
338 #define FBNIC_TCE_TXB_CTRL_LOAD CSR_BIT(0)
342 #define FBNIC_TCE_TXB_ENQ_WRR_CTRL 0x04003 /* 0x1000c */
343 #define FBNIC_TCE_TXB_ENQ_WRR_CTRL_WEIGHT0 CSR_GENMASK(7, 0)
347 #define FBNIC_TCE_TXB_TEI_Q0_CTRL 0x04004 /* 0x10010 */
348 #define FBNIC_TCE_TXB_TEI_Q1_CTRL 0x04005 /* 0x10014 */
349 #define FBNIC_TCE_TXB_MC_Q_CTRL 0x04006 /* 0x10018 */
350 #define FBNIC_TCE_TXB_RX_TEI_Q_CTRL 0x04007 /* 0x1001c */
351 #define FBNIC_TCE_TXB_RX_BMC_Q_CTRL 0x04008 /* 0x10020 */
352 #define FBNIC_TCE_TXB_Q_CTRL_START CSR_GENMASK(10, 0)
355 #define FBNIC_TCE_TXB_TEI_DWRR_CTRL 0x04009 /* 0x10024 */
356 #define FBNIC_TCE_TXB_TEI_DWRR_CTRL_QUANTUM0 CSR_GENMASK(7, 0)
358 #define FBNIC_TCE_TXB_NTWRK_DWRR_CTRL 0x0400a /* 0x10028 */
359 #define FBNIC_TCE_TXB_NTWRK_DWRR_CTRL_QUANTUM0 CSR_GENMASK(7, 0)
363 #define FBNIC_TCE_TXB_CLDR_CFG 0x0400b /* 0x1002c */
364 #define FBNIC_TCE_TXB_CLDR_CFG_NUM_SLOT CSR_GENMASK(5, 0)
365 #define FBNIC_TCE_TXB_CLDR_SLOT_CFG(n) (0x0400c + (n)) /* 0x10030 + 4*n */
367 #define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_0_0 CSR_GENMASK(1, 0)
384 #define FBNIC_TCE_BMC_MAX_PKTSZ 0x0403a /* 0x100e8 */
385 #define FBNIC_TCE_BMC_MAX_PKTSZ_TX CSR_GENMASK(13, 0)
387 #define FBNIC_TCE_MC_MAX_PKTSZ 0x0403b /* 0x100ec */
388 #define FBNIC_TCE_MC_MAX_PKTSZ_TMI CSR_GENMASK(13, 0)
390 #define FBNIC_TCE_SOP_PROT_CTRL 0x0403c /* 0x100f0 */
391 #define FBNIC_TCE_SOP_PROT_CTRL_TBI CSR_GENMASK(7, 0)
395 #define FBNIC_TCE_DROP_CTRL 0x0403d /* 0x100f4 */
396 #define FBNIC_TCE_DROP_CTRL_TTI_CM_DROP_EN CSR_BIT(0)
400 #define FBNIC_TCE_TCAM_IDX2DEST_MAP 0x0404A /* 0x10128 */
401 #define FBNIC_TCE_TCAM_IDX2DEST_MAP_DEST_ID_0 CSR_GENMASK(3, 0)
408 #define FBNIC_TCE_TXB_TX_BMC_Q_CTRL 0x0404B /* 0x1012c */
409 #define FBNIC_TCE_TXB_BMC_DWRR_CTRL 0x0404C /* 0x10130 */
410 #define FBNIC_TCE_TXB_BMC_DWRR_CTRL_QUANTUM0 CSR_GENMASK(7, 0)
412 #define FBNIC_TCE_TXB_TEI_DWRR_CTRL_EXT 0x0404D /* 0x10134 */
414 0x0404E /* 0x10138 */
415 #define FBNIC_TCE_TXB_BMC_DWRR_CTRL_EXT 0x0404F /* 0x1013c */
416 #define FBNIC_CSR_END_TCE 0x04050 /* CSR section delimiter */
419 #define FBNIC_CSR_START_TCE_RAM 0x04200 /* CSR section delimiter */
421 (0x04200 + 0x8 * (n) + (m)) /* 0x10800 + 32*n + 4*m */
422 #define FBNIC_TCE_RAM_TCAM_MASK CSR_GENMASK(15, 0)
424 #define FBNIC_TCE_RAM_TCAM3(n) (0x04218 + (n)) /* 0x010860 + 4*n */
428 #define FBNIC_CSR_END_TCE_RAM 0x0421F /* CSR section delimiter */
431 #define FBNIC_CSR_START_TMI 0x04400 /* CSR section delimiter */
432 #define FBNIC_TMI_SOP_PROT_CTRL 0x04400 /* 0x11000 */
433 #define FBNIC_TMI_DROP_CTRL 0x04401 /* 0x11004 */
434 #define FBNIC_TMI_DROP_CTRL_EN CSR_BIT(0)
435 #define FBNIC_CSR_END_TMI 0x0443f /* CSR section delimiter */
438 #define FBNIC_CSR_START_PTP 0x04800 /* CSR section delimiter */
439 #define FBNIC_PTP_REG_BASE 0x04800 /* 0x12000 */
441 #define FBNIC_PTP_CTRL 0x04800 /* 0x12000 */
442 #define FBNIC_PTP_CTRL_EN CSR_BIT(0)
448 #define FBNIC_PTP_ADJUST 0x04801 /* 0x12004 */
449 #define FBNIC_PTP_ADJUST_INIT CSR_BIT(0)
454 #define FBNIC_PTP_INIT_HI 0x04802 /* 0x12008 */
455 #define FBNIC_PTP_INIT_LO 0x04803 /* 0x1200c */
457 #define FBNIC_PTP_NUDGE_NS 0x04804 /* 0x12010 */
458 #define FBNIC_PTP_NUDGE_SUBNS 0x04805 /* 0x12014 */
460 #define FBNIC_PTP_ADD_VAL_NS 0x04806 /* 0x12018 */
461 #define FBNIC_PTP_ADD_VAL_NS_MASK CSR_GENMASK(15, 0)
462 #define FBNIC_PTP_ADD_VAL_SUBNS 0x04807 /* 0x1201c */
464 #define FBNIC_PTP_CTR_VAL_HI 0x04808 /* 0x12020 */
465 #define FBNIC_PTP_CTR_VAL_LO 0x04809 /* 0x12024 */
467 #define FBNIC_PTP_MONO_PTP_CTR_HI 0x0480a /* 0x12028 */
468 #define FBNIC_PTP_MONO_PTP_CTR_LO 0x0480b /* 0x1202c */
470 #define FBNIC_PTP_CDC_FIFO_STATUS 0x0480c /* 0x12030 */
471 #define FBNIC_PTP_SPARE 0x0480d /* 0x12034 */
472 #define FBNIC_CSR_END_PTP 0x0480d /* CSR section delimiter */
475 #define FBNIC_CSR_START_RXB 0x08000 /* CSR section delimiter */
477 FBNIC_RXB_FIFO_MC = 0,
488 #define FBNIC_RXB_CT_SIZE(n) (0x08000 + (n)) /* 0x20000 + 4*n */
490 #define FBNIC_RXB_CT_SIZE_HEADER CSR_GENMASK(5, 0)
493 #define FBNIC_RXB_PAUSE_DROP_CTRL 0x08008 /* 0x20020 */
494 #define FBNIC_RXB_PAUSE_DROP_CTRL_DROP_ENABLE CSR_GENMASK(7, 0)
498 #define FBNIC_RXB_PAUSE_THLD(n) (0x08009 + (n)) /* 0x20024 + 4*n */
500 #define FBNIC_RXB_PAUSE_THLD_ON CSR_GENMASK(12, 0)
502 #define FBNIC_RXB_DROP_THLD(n) (0x08011 + (n)) /* 0x20044 + 4*n */
504 #define FBNIC_RXB_DROP_THLD_ON CSR_GENMASK(12, 0)
506 #define FBNIC_RXB_ECN_THLD(n) (0x0801e + (n)) /* 0x20078 + 4*n */
508 #define FBNIC_RXB_ECN_THLD_ON CSR_GENMASK(12, 0)
510 #define FBNIC_RXB_PBUF_CFG(n) (0x08027 + (n)) /* 0x2009c + 4*n */
512 #define FBNIC_RXB_PBUF_BASE_ADDR CSR_GENMASK(12, 0)
514 #define FBNIC_RXB_DWRR_RDE_WEIGHT0 0x0802f /* 0x200bc */
515 #define FBNIC_RXB_DWRR_RDE_WEIGHT0_QUANTUM0 CSR_GENMASK(7, 0)
519 #define FBNIC_RXB_DWRR_RDE_WEIGHT1 0x08030 /* 0x200c0 */
520 #define FBNIC_RXB_DWRR_RDE_WEIGHT1_QUANTUM4 CSR_GENMASK(7, 0)
521 #define FBNIC_RXB_DWRR_BMC_WEIGHT 0x08031 /* 0x200c4 */
522 #define FBNIC_RXB_CLDR_PRIO_CFG(n) (0x8034 + (n)) /* 0x200d0 + 4*n */
524 #define FBNIC_RXB_ENDIAN_FCS 0x08044 /* 0x20110 */
533 #define FBNIC_RXB_PBUF_CREDIT(n) (0x08047 + (n)) /* 0x2011C + 4*n */
535 #define FBNIC_RXB_PBUF_CREDIT_MASK CSR_GENMASK(13, 0)
536 #define FBNIC_RXB_INTF_CREDIT 0x0804f /* 0x2013C */
537 #define FBNIC_RXB_INTF_CREDIT_MASK0 CSR_GENMASK(3, 0)
542 #define FBNIC_RXB_PAUSE_EVENT_CNT(n) (0x08053 + (n)) /* 0x2014c + 4*n */
543 #define FBNIC_RXB_DROP_FRMS_STS(n) (0x08057 + (n)) /* 0x2015c + 4*n */
545 (0x08080 + 2 * (n)) /* 0x20200 + 8*n */
547 (0x08081 + 2 * (n)) /* 0x20204 + 8*n */
548 #define FBNIC_RXB_TRUN_FRMS_STS(n) (0x08091 + (n)) /* 0x20244 + 4*n */
550 (0x080c0 + 2 * (n)) /* 0x20300 + 8*n */
552 (0x080c1 + 2 * (n)) /* 0x20304 + 8*n */
553 #define FBNIC_RXB_TRANS_PAUSE_STS(n) (0x080d1 + (n)) /* 0x20344 + 4*n */
554 #define FBNIC_RXB_TRANS_DROP_STS(n) (0x080d9 + (n)) /* 0x20364 + 4*n */
555 #define FBNIC_RXB_TRANS_ECN_STS(n) (0x080e1 + (n)) /* 0x20384 + 4*n */
557 FBNIC_RXB_ENQUEUE_NET = 0,
564 #define FBNIC_RXB_DRBO_FRM_CNT_SRC(n) (0x080f9 + (n)) /* 0x203e4 + 4*n */
566 (0x080fd + (n)) /* 0x203f4 + 4*n */
568 (0x08101 + (n)) /* 0x20404 + 4*n */
569 #define FBNIC_RXB_INTF_FRM_CNT_DST(n) (0x08105 + (n)) /* 0x20414 + 4*n */
571 (0x08109 + (n)) /* 0x20424 + 4*n */
573 (0x0810d + (n)) /* 0x20434 + 4*n */
574 #define FBNIC_RXB_PBUF_FRM_CNT_DST(n) (0x08111 + (n)) /* 0x20444 + 4*n */
576 (0x08115 + (n)) /* 0x20454 + 4*n */
578 (0x08119 + (n)) /* 0x20464 + 4*n */
580 #define FBNIC_RXB_PBUF_FIFO_LEVEL(n) (0x0811d + (n)) /* 0x20474 + 4*n */
582 #define FBNIC_RXB_INTEGRITY_ERR(n) (0x0812f + (n)) /* 0x204bc + 4*n */
583 #define FBNIC_RXB_MAC_ERR(n) (0x08133 + (n)) /* 0x204cc + 4*n */
584 #define FBNIC_RXB_PARSER_ERR(n) (0x08137 + (n)) /* 0x204dc + 4*n */
585 #define FBNIC_RXB_FRM_ERR(n) (0x0813b + (n)) /* 0x204ec + 4*n */
587 #define FBNIC_RXB_DWRR_RDE_WEIGHT0_EXT 0x08143 /* 0x2050c */
588 #define FBNIC_RXB_DWRR_RDE_WEIGHT1_EXT 0x08144 /* 0x20510 */
589 #define FBNIC_CSR_END_RXB 0x081b1 /* CSR section delimiter */
592 #define FBNIC_CSR_START_RPC 0x08400 /* CSR section delimiter */
593 #define FBNIC_RPC_RMI_CONFIG 0x08400 /* 0x21000 */
594 #define FBNIC_RPC_RMI_CONFIG_OH_BYTES CSR_GENMASK(4, 0)
599 #define FBNIC_RPC_ACT_TBL0_DEFAULT 0x0840a /* 0x21028 */
600 #define FBNIC_RPC_ACT_TBL0_DROP CSR_BIT(0)
612 #define FBNIC_RPC_ACT_TBL1_DEFAULT 0x0840b /* 0x2102c */
613 #define FBNIC_RPC_ACT_TBL1_RSS_ENA_MASK CSR_GENMASK(15, 0)
628 #define FBNIC_RPC_RSS_KEY(n) (0x0840c + (n)) /* 0x21030 + 4*n */
641 #define FBNIC_RPC_CNTR_TCP_OPT_ERR 0x0849e /* 0x21278 */
642 #define FBNIC_RPC_CNTR_UNKN_ETYPE 0x0849f /* 0x2127c */
643 #define FBNIC_RPC_CNTR_IPV4_FRAG 0x084a0 /* 0x21280 */
644 #define FBNIC_RPC_CNTR_IPV6_FRAG 0x084a1 /* 0x21284 */
645 #define FBNIC_RPC_CNTR_IPV4_ESP 0x084a2 /* 0x21288 */
646 #define FBNIC_RPC_CNTR_IPV6_ESP 0x084a3 /* 0x2128c */
647 #define FBNIC_RPC_CNTR_UNKN_EXT_HDR 0x084a4 /* 0x21290 */
648 #define FBNIC_RPC_CNTR_OUT_OF_HDR_ERR 0x084a5 /* 0x21294 */
649 #define FBNIC_RPC_CNTR_OVR_SIZE_ERR 0x084a6 /* 0x21298 */
651 #define FBNIC_RPC_TCAM_MACDA_VALIDATE 0x0852d /* 0x214b4 */
652 #define FBNIC_CSR_END_RPC 0x0856b /* CSR section delimiter */
656 #define FBNIC_CSR_START_RPC_RAM 0x08800 /* CSR section delimiter */
657 #define FBNIC_RPC_ACT_TBL0(n) (0x08800 + (n)) /* 0x22000 + 4*n */
658 #define FBNIC_RPC_ACT_TBL1(n) (0x08840 + (n)) /* 0x22100 + 4*n */
668 (0x08880 + 0x40 * (n) + (m)) /* 0x22200 + 256*n + 4*m */
670 #define FBNIC_RPC_TCAM_ACT_VALUE CSR_GENMASK(15, 0)
674 (0x08b80 + 0x20 * (n) + (m)) /* 0x022e00 + 128*n + 4*m */
675 #define FBNIC_RPC_TCAM_MACDA_VALUE CSR_GENMASK(15, 0)
679 (0x08c00 + 0x08 * (n) + (m)) /* 0x023000 + 32*n + 4*m */
681 (0x08c48 + 0x08 * (n) + (m)) /* 0x023120 + 32*n + 4*m */
683 (0x08c90 + 0x08 * (n) + (m)) /* 0x023240 + 32*n + 4*m */
685 (0x08cd8 + 0x08 * (n) + (m)) /* 0x023360 + 32*n + 4*m */
688 (0x08d20 + 0x100 * (n) + (m)) /* 0x023480 + 1024*n + 4*m */
691 #define FBNIC_CSR_END_RPC_RAM 0x08f1f /* CSR section delimiter */
694 #define FBNIC_CSR_START_FAB 0x0C000 /* CSR section delimiter */
695 #define FBNIC_FAB_AXI4_AR_SPACER_2_CFG 0x0C005 /* 0x30014 */
697 #define FBNIC_FAB_AXI4_AR_SPACER_THREADSHOLD CSR_GENMASK(15, 0)
698 #define FBNIC_CSR_END_FAB 0x0C020 /* CSR section delimiter */
701 #define FBNIC_CSR_START_MASTER 0x0C400 /* CSR section delimiter */
702 #define FBNIC_MASTER_SPARE_0 0x0C41B /* 0x3106c */
703 #define FBNIC_CSR_END_MASTER 0x0C452 /* CSR section delimiter */
706 #define FBNIC_CSR_START_PCS 0x10000 /* CSR section delimiter */
707 #define FBNIC_CSR_END_PCS 0x10668 /* CSR section delimiter */
709 #define FBNIC_CSR_START_RSFEC 0x10800 /* CSR section delimiter */
710 #define FBNIC_CSR_END_RSFEC 0x108c8 /* CSR section delimiter */
713 #define FBNIC_CSR_START_MAC_MAC 0x11000 /* CSR section delimiter */
714 #define FBNIC_MAC_COMMAND_CONFIG 0x11002 /* 0x44008 */
722 #define FBNIC_MAC_COMMAND_CONFIG_TX_ENA CSR_BIT(0)
723 #define FBNIC_MAC_CL01_PAUSE_QUANTA 0x11015 /* 0x44054 */
724 #define FBNIC_MAC_CL01_QUANTA_THRESH 0x11019 /* 0x44064 */
725 #define FBNIC_CSR_END_MAC_MAC 0x11028 /* CSR section delimiter */
728 #define FBNIC_CSR_START_SIG 0x11800 /* CSR section delimiter */
729 #define FBNIC_SIG_MAC_IN0 0x11800 /* 0x46000 */
736 #define FBNIC_SIG_PCS_OUT0 0x11808 /* 0x46020 */
740 #define FBNIC_SIG_PCS_OUT1 0x11809 /* 0x46024 */
742 #define FBNIC_SIG_PCS_INTR_STS 0x11814 /* 0x46050 */
744 #define FBNIC_SIG_PCS_INTR_LINK_UP CSR_BIT(0)
745 #define FBNIC_SIG_PCS_INTR_MASK 0x11816 /* 0x46058 */
746 #define FBNIC_CSR_END_SIG 0x1184e /* CSR section delimiter */
748 #define FBNIC_CSR_START_MAC_STAT 0x11a00
749 #define FBNIC_MAC_STAT_RX_BYTE_COUNT_L 0x11a08 /* 0x46820 */
750 #define FBNIC_MAC_STAT_RX_BYTE_COUNT_H 0x11a09 /* 0x46824 */
752 0x11a0a /* 0x46828 */
754 0x11a0b /* 0x4682c */
755 #define FBNIC_MAC_STAT_RX_TOOLONG_L 0x11a0e /* 0x46838 */
756 #define FBNIC_MAC_STAT_RX_TOOLONG_H 0x11a0f /* 0x4683c */
758 0x11a12 /* 0x46848 */
760 0x11a13 /* 0x4684c */
762 0x11a14 /* 0x46850 */
764 0x11a15 /* 0x46854 */
765 #define FBNIC_MAC_STAT_RX_IFINERRORS_L 0x11a18 /* 0x46860 */
766 #define FBNIC_MAC_STAT_RX_IFINERRORS_H 0x11a19 /* 0x46864 */
767 #define FBNIC_MAC_STAT_RX_MULTICAST_L 0x11a1c /* 0x46870 */
768 #define FBNIC_MAC_STAT_RX_MULTICAST_H 0x11a1d /* 0x46874 */
769 #define FBNIC_MAC_STAT_RX_BROADCAST_L 0x11a1e /* 0x46878 */
770 #define FBNIC_MAC_STAT_RX_BROADCAST_H 0x11a1f /* 0x4687c */
771 #define FBNIC_MAC_STAT_TX_BYTE_COUNT_L 0x11a3e /* 0x468f8 */
772 #define FBNIC_MAC_STAT_TX_BYTE_COUNT_H 0x11a3f /* 0x468fc */
774 0x11a42 /* 0x46908 */
776 0x11a43 /* 0x4690c */
778 0x11a46 /* 0x46918 */
780 0x11a47 /* 0x4691c */
781 #define FBNIC_MAC_STAT_TX_MULTICAST_L 0x11a4a /* 0x46928 */
782 #define FBNIC_MAC_STAT_TX_MULTICAST_H 0x11a4b /* 0x4692c */
783 #define FBNIC_MAC_STAT_TX_BROADCAST_L 0x11a4c /* 0x46930 */
784 #define FBNIC_MAC_STAT_TX_BROADCAST_H 0x11a4d /* 0x46934 */
786 #define FBNIC_CSR_START_PUL_USER 0x31000 /* CSR section delimiter */
787 #define FBNIC_PUL_OB_TLP_HDR_AW_CFG 0x3103d /* 0xc40f4 */
789 #define FBNIC_PUL_OB_TLP_HDR_AR_CFG 0x3103e /* 0xc40f8 */
791 #define FBNIC_CSR_END_PUL_USER 0x31080 /* CSR section delimiter */
800 #define FBNIC_CSR_START_QUEUE 0x40000 /* CSR section delimiter */
801 #define FBNIC_QUEUE_STRIDE 0x400 /* 0x1000 */
803 (0x40000 + FBNIC_QUEUE_STRIDE * (n)) /* 0x100000 + 4096*n */
805 #define FBNIC_QUEUE_TWQ0_CTL 0x000 /* 0x000 */
806 #define FBNIC_QUEUE_TWQ1_CTL 0x001 /* 0x004 */
807 #define FBNIC_QUEUE_TWQ_CTL_RESET CSR_BIT(0)
809 #define FBNIC_QUEUE_TWQ0_TAIL 0x002 /* 0x008 */
810 #define FBNIC_QUEUE_TWQ1_TAIL 0x003 /* 0x00c */
812 #define FBNIC_QUEUE_TWQ0_SIZE 0x00a /* 0x028 */
813 #define FBNIC_QUEUE_TWQ1_SIZE 0x00b /* 0x02c */
814 #define FBNIC_QUEUE_TWQ_SIZE_MASK CSR_GENMASK(3, 0)
816 #define FBNIC_QUEUE_TWQ0_BAL 0x020 /* 0x080 */
818 #define FBNIC_QUEUE_TWQ0_BAH 0x021 /* 0x084 */
819 #define FBNIC_QUEUE_TWQ1_BAL 0x022 /* 0x088 */
820 #define FBNIC_QUEUE_TWQ1_BAH 0x023 /* 0x08c */
823 #define FBNIC_QUEUE_TCQ_CTL 0x080 /* 0x200 */
824 #define FBNIC_QUEUE_TCQ_CTL_RESET CSR_BIT(0)
827 #define FBNIC_QUEUE_TCQ_HEAD 0x081 /* 0x204 */
829 #define FBNIC_QUEUE_TCQ_SIZE 0x084 /* 0x210 */
830 #define FBNIC_QUEUE_TCQ_SIZE_MASK CSR_GENMASK(3, 0)
832 #define FBNIC_QUEUE_TCQ_BAL 0x0a0 /* 0x280 */
833 #define FBNIC_QUEUE_TCQ_BAH 0x0a1 /* 0x284 */
836 #define FBNIC_QUEUE_TIM_CTL 0x0c0 /* 0x300 */
837 #define FBNIC_QUEUE_TIM_CTL_MSIX_MASK CSR_GENMASK(7, 0)
839 #define FBNIC_QUEUE_TIM_THRESHOLD 0x0c1 /* 0x304 */
840 #define FBNIC_QUEUE_TIM_THRESHOLD_TWD_MASK CSR_GENMASK(14, 0)
842 #define FBNIC_QUEUE_TIM_CLEAR 0x0c2 /* 0x308 */
843 #define FBNIC_QUEUE_TIM_CLEAR_MASK CSR_BIT(0)
844 #define FBNIC_QUEUE_TIM_SET 0x0c3 /* 0x30c */
845 #define FBNIC_QUEUE_TIM_SET_MASK CSR_BIT(0)
846 #define FBNIC_QUEUE_TIM_MASK 0x0c4 /* 0x310 */
847 #define FBNIC_QUEUE_TIM_MASK_MASK CSR_BIT(0)
849 #define FBNIC_QUEUE_TIM_TIMER 0x0c5 /* 0x314 */
851 #define FBNIC_QUEUE_TIM_COUNTS 0x0c6 /* 0x318 */
853 #define FBNIC_QUEUE_TIM_COUNTS_CNT0_MASK CSR_GENMASK(14, 0)
856 #define FBNIC_QUEUE_RCQ_CTL 0x200 /* 0x800 */
857 #define FBNIC_QUEUE_RCQ_CTL_RESET CSR_BIT(0)
860 #define FBNIC_QUEUE_RCQ_HEAD 0x201 /* 0x804 */
862 #define FBNIC_QUEUE_RCQ_SIZE 0x204 /* 0x810 */
863 #define FBNIC_QUEUE_RCQ_SIZE_MASK CSR_GENMASK(3, 0)
865 #define FBNIC_QUEUE_RCQ_BAL 0x220 /* 0x880 */
866 #define FBNIC_QUEUE_RCQ_BAH 0x221 /* 0x884 */
869 #define FBNIC_QUEUE_BDQ_CTL 0x240 /* 0x900 */
870 #define FBNIC_QUEUE_BDQ_CTL_RESET CSR_BIT(0)
874 #define FBNIC_QUEUE_BDQ_HPQ_TAIL 0x241 /* 0x904 */
875 #define FBNIC_QUEUE_BDQ_PPQ_TAIL 0x242 /* 0x908 */
877 #define FBNIC_QUEUE_BDQ_HPQ_SIZE 0x247 /* 0x91c */
878 #define FBNIC_QUEUE_BDQ_PPQ_SIZE 0x248 /* 0x920 */
879 #define FBNIC_QUEUE_BDQ_SIZE_MASK CSR_GENMASK(3, 0)
881 #define FBNIC_QUEUE_BDQ_HPQ_BAL 0x260 /* 0x980 */
882 #define FBNIC_QUEUE_BDQ_HPQ_BAH 0x261 /* 0x984 */
883 #define FBNIC_QUEUE_BDQ_PPQ_BAL 0x262 /* 0x988 */
884 #define FBNIC_QUEUE_BDQ_PPQ_BAH 0x263 /* 0x98c */
887 #define FBNIC_QUEUE_RDE_CTL0 0x2a0 /* 0xa80 */
891 FBNIC_QUEUE_RDE_CTL0_DROP_IMMEDIATE = 0,
899 #define FBNIC_QUEUE_RDE_CTL1 0x2a1 /* 0xa84 */
904 #define FBNIC_QUEUE_RDE_CTL1_PAYLD_PACK_MASK CSR_GENMASK(1, 0)
906 FBNIC_QUEUE_RDE_CTL1_PAYLD_PACK_NONE = 0,
912 #define FBNIC_QUEUE_RIM_CTL 0x2c0 /* 0xb00 */
913 #define FBNIC_QUEUE_RIM_CTL_MSIX_MASK CSR_GENMASK(7, 0)
915 #define FBNIC_QUEUE_RIM_THRESHOLD 0x2c1 /* 0xb04 */
916 #define FBNIC_QUEUE_RIM_THRESHOLD_RCD_MASK CSR_GENMASK(14, 0)
918 #define FBNIC_QUEUE_RIM_CLEAR 0x2c2 /* 0xb08 */
919 #define FBNIC_QUEUE_RIM_CLEAR_MASK CSR_BIT(0)
920 #define FBNIC_QUEUE_RIM_SET 0x2c3 /* 0xb0c */
921 #define FBNIC_QUEUE_RIM_SET_MASK CSR_BIT(0)
922 #define FBNIC_QUEUE_RIM_MASK 0x2c4 /* 0xb10 */
923 #define FBNIC_QUEUE_RIM_MASK_MASK CSR_BIT(0)
925 #define FBNIC_QUEUE_RIM_COAL_STATUS 0x2c5 /* 0xb14 */
927 #define FBNIC_QUEUE_RIM_TIMER_MASK CSR_GENMASK(13, 0)
929 #define FBNIC_CSR_END_QUEUE (0x40000 + 0x400 * FBNIC_MAX_QUEUES - 1)
933 0x3106e /* 0xc41b8 */
935 0x31070 /* 0xc41c0 */
937 0x31071 /* 0xc41c4 */
939 0x31072 /* 0xc41c8 */
941 0x31073 /* 0xc41cc */
943 0x31074 /* 0xc41d0 */
945 0x31075 /* 0xc41d4 */
947 0x31076 /* 0xc41d8 */
949 0x31077 /* 0xc41dc */
951 0x31078 /* 0xc41e0 */
953 0x31079 /* 0xc41e4 */
955 0x3107a /* 0xc41e8 */
957 0x3107b /* 0xc41ec */
959 0x3107c /* 0xc41f0 */
961 0x3107d /* 0xc41f4 */
963 0x3107e /* 0xc41f8 */
965 0x3107f /* 0xc41fc */
966 #define FBNIC_CSR_END_PUL_USER 0x31080 /* CSR section delimiter */
974 * Currently we use an offset of 0x6000 on BAR4 for the mailbox so we just
980 ((((mbx_idx) * FBNIC_IPC_MBX_DESC_LEN + (desc_idx)) * 2) + 0x6000)
983 #define FBNIC_FW_ZERO_REG FBNIC_IPC_MBX(0, 0)
995 #define FBNIC_IPC_MBX_DESC_HOST_CMPL DESC_BIT(0)