Lines Matching +full:0 +full:x262
16 #define RTW8852B_RXDCK_VER 0x1
17 #define RTW8852B_IQK_VER 0x2a
22 #define RTW8852B_DPK_VER 0x0d
28 #define DPK_TXAGC_LOWER 0x2e
29 #define DPK_TXAGC_UPPER 0x3f
30 #define DPK_TXAGC_INVAL 0xff
31 #define RFREG_MASKRXBB 0x003e0
32 #define RFREG_MASKMODE 0xf0000
35 LBK_RXIQK = 0x06,
36 SYNC = 0x10,
37 MDPK_IDL = 0x11,
38 MDPK_MPA = 0x12,
39 GAIN_LOSS = 0x13,
40 GAIN_CAL = 0x14,
41 DPK_RXAGC = 0x15,
42 KIP_PRESET = 0x16,
43 KIP_RESTORE = 0x17,
44 DPK_TXAGC = 0x19,
45 D_KIP_PRESET = 0x28,
46 D_TXAGC = 0x29,
47 D_RXAGC = 0x2a,
48 D_SYNC = 0x2b,
49 D_GAIN_LOSS = 0x2c,
50 D_MDPK_IDL = 0x2d,
51 D_GAIN_NORM = 0x2f,
52 D_KIP_THERMAL = 0x30,
53 D_KIP_RESTORE = 0x31
66 ID_TXAGC = 0x0,
67 ID_FLOK_COARSE = 0x1,
68 ID_FLOK_FINE = 0x2,
69 ID_TXK = 0x3,
70 ID_RXAGC = 0x4,
71 ID_RXK = 0x5,
72 ID_NBTXK = 0x6,
73 ID_NBRXK = 0x7,
74 ID_FLOK_VBUFFER = 0x8,
75 ID_A_FLOK_COARSE = 0x9,
76 ID_G_FLOK_COARSE = 0xa,
77 ID_A_FLOK_FINE = 0xb,
78 ID_G_FLOK_FINE = 0xc,
79 ID_IQK_RESTORE = 0x10,
82 static const u32 _tssi_trigger[RTW8852B_TSSI_PATH_NR] = {0x5820, 0x7820};
83 static const u32 _tssi_cw_rpt_addr[RTW8852B_TSSI_PATH_NR] = {0x1c18, 0x3c18};
85 {0x5634, 0x5630, 0x5630, 0x5630},
86 {0x7634, 0x7630, 0x7630, 0x7630} };
88 0x000003ff, 0x3ff00000, 0x000ffc00, 0x000003ff};
89 static const u32 _tssi_de_cck_long[RF_PATH_NUM_8852B] = {0x5858, 0x7858};
90 static const u32 _tssi_de_cck_short[RF_PATH_NUM_8852B] = {0x5860, 0x7860};
91 static const u32 _tssi_de_mcs_20m[RF_PATH_NUM_8852B] = {0x5838, 0x7838};
92 static const u32 _tssi_de_mcs_40m[RF_PATH_NUM_8852B] = {0x5840, 0x7840};
93 static const u32 _tssi_de_mcs_80m[RF_PATH_NUM_8852B] = {0x5848, 0x7848};
94 static const u32 _tssi_de_mcs_80m_80m[RF_PATH_NUM_8852B] = {0x5850, 0x7850};
95 static const u32 _tssi_de_mcs_5m[RF_PATH_NUM_8852B] = {0x5828, 0x7828};
96 static const u32 _tssi_de_mcs_10m[RF_PATH_NUM_8852B] = {0x5830, 0x7830};
97 static const u32 _a_idxrxgain[RTW8852B_RXK_GROUP_NR] = {0x190, 0x198, 0x350, 0x352};
98 static const u32 _a_idxattc2[RTW8852B_RXK_GROUP_NR] = {0x0f, 0x0f, 0x3f, 0x7f};
99 static const u32 _a_idxattc1[RTW8852B_RXK_GROUP_NR] = {0x3, 0x1, 0x0, 0x0};
100 static const u32 _g_idxrxgain[RTW8852B_RXK_GROUP_NR] = {0x212, 0x21c, 0x350, 0x360};
101 static const u32 _g_idxattc2[RTW8852B_RXK_GROUP_NR] = {0x00, 0x00, 0x28, 0x5f};
102 static const u32 _g_idxattc1[RTW8852B_RXK_GROUP_NR] = {0x3, 0x3, 0x2, 0x1};
103 static const u32 _a_power_range[RTW8852B_RXK_GROUP_NR] = {0x0, 0x0, 0x0, 0x0};
104 static const u32 _a_track_range[RTW8852B_RXK_GROUP_NR] = {0x3, 0x3, 0x6, 0x6};
105 static const u32 _a_gain_bb[RTW8852B_RXK_GROUP_NR] = {0x08, 0x0e, 0x06, 0x0e};
106 static const u32 _a_itqt[RTW8852B_RXK_GROUP_NR] = {0x12, 0x12, 0x12, 0x1b};
107 static const u32 _g_power_range[RTW8852B_RXK_GROUP_NR] = {0x0, 0x0, 0x0, 0x0};
108 static const u32 _g_track_range[RTW8852B_RXK_GROUP_NR] = {0x4, 0x4, 0x6, 0x6};
109 static const u32 _g_gain_bb[RTW8852B_RXK_GROUP_NR] = {0x08, 0x0e, 0x06, 0x0e};
110 static const u32 _g_itqt[RTW8852B_RXK_GROUP_NR] = {0x09, 0x12, 0x1b, 0x24};
112 static const u32 rtw8852b_backup_bb_regs[] = {0x2344, 0x5800, 0x7800};
114 0xde, 0xdf, 0x8b, 0x90, 0x97, 0x85, 0x1e, 0x0, 0x2, 0x5, 0x10005
121 {0x20fc, 0xffff0000, 0x0303},
122 {0x5864, 0x18000000, 0x3},
123 {0x7864, 0x18000000, 0x3},
124 {0x12b8, 0x40000000, 0x1},
125 {0x32b8, 0x40000000, 0x1},
126 {0x030c, 0xff000000, 0x13},
127 {0x032c, 0xffff0000, 0x0041},
128 {0x12b8, 0x10000000, 0x1},
129 {0x58c8, 0x01000000, 0x1},
130 {0x78c8, 0x01000000, 0x1},
131 {0x5864, 0xc0000000, 0x3},
132 {0x7864, 0xc0000000, 0x3},
133 {0x2008, 0x01ffffff, 0x1ffffff},
134 {0x0c1c, 0x00000004, 0x1},
135 {0x0700, 0x08000000, 0x1},
136 {0x0c70, 0x000003ff, 0x3ff},
137 {0x0c60, 0x00000003, 0x3},
138 {0x0c6c, 0x00000001, 0x1},
139 {0x58ac, 0x08000000, 0x1},
140 {0x78ac, 0x08000000, 0x1},
141 {0x0c3c, 0x00000200, 0x1},
142 {0x2344, 0x80000000, 0x1},
143 {0x4490, 0x80000000, 0x1},
144 {0x12a0, 0x00007000, 0x7},
145 {0x12a0, 0x00008000, 0x1},
146 {0x12a0, 0x00070000, 0x3},
147 {0x12a0, 0x00080000, 0x1},
148 {0x32a0, 0x00070000, 0x3},
149 {0x32a0, 0x00080000, 0x1},
150 {0x0700, 0x01000000, 0x1},
151 {0x0700, 0x06000000, 0x2},
152 {0x20fc, 0xffff0000, 0x3333},
156 {0x20fc, 0xffff0000, 0x0303},
157 {0x12b8, 0x40000000, 0x0},
158 {0x32b8, 0x40000000, 0x0},
159 {0x5864, 0xc0000000, 0x0},
160 {0x7864, 0xc0000000, 0x0},
161 {0x2008, 0x01ffffff, 0x0000000},
162 {0x0c1c, 0x00000004, 0x0},
163 {0x0700, 0x08000000, 0x0},
164 {0x0c70, 0x0000001f, 0x03},
165 {0x0c70, 0x000003e0, 0x03},
166 {0x12a0, 0x000ff000, 0x00},
167 {0x32a0, 0x000ff000, 0x00},
168 {0x0700, 0x07000000, 0x0},
169 {0x20fc, 0xffff0000, 0x0000},
170 {0x58c8, 0x01000000, 0x0},
171 {0x78c8, 0x01000000, 0x0},
172 {0x0c3c, 0x00000200, 0x0},
173 {0x2344, 0x80000000, 0x0},
180 for (i = 0; i < BACKUP_BB_REGS_NR; i++) { in _rfk_backup_bb_reg()
195 for (i = 0; i < BACKUP_RF_REGS_NR; i++) { in _rfk_backup_rf_reg()
210 for (i = 0; i < BACKUP_BB_REGS_NR; i++) { in _rfk_restore_bb_reg()
224 for (i = 0; i < BACKUP_RF_REGS_NR; i++) { in _rfk_restore_rf_reg()
238 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x1); in _rfk_rf_direct_cntrl()
240 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0); in _rfk_rf_direct_cntrl()
247 rtw89_write_rf(rtwdev, path, RR_BBDC, RR_BBDC_SEL, 0x1); in _rfk_drf_direct_cntrl()
249 rtw89_write_rf(rtwdev, path, RR_BBDC, RR_BBDC_SEL, 0x0); in _rfk_drf_direct_cntrl()
258 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val == 0x55, in _iqk_check_cal()
259 1, 8200, false, rtwdev, 0xbff8, MASKBYTE0); in _iqk_check_cal()
267 rtw89_phy_write32_mask(rtwdev, R_NCTL_N1, MASKBYTE0, 0x0); in _iqk_check_cal()
271 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x8008 = 0x%x\n", path, val); in _iqk_check_cal()
297 rtw89_write_rf(rtwdev, path, RR_DCK1, RR_DCK1_CLR, 0x0); in _set_rx_dck()
298 rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_LV, 0x0); in _set_rx_dck()
299 rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_LV, 0x1); in _set_rx_dck()
309 "[RX_DCK] ****** RXDCK Start (Ver: 0x%x, CV : 0x%x) ******\n", in _rx_dck()
312 for (path = 0; path < RF_PATH_NUM_8852B; path++) { in _rx_dck()
319 B_P0_TSSI_TRK_EN, 0x1); in _rx_dck()
321 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0); in _rx_dck()
322 rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_FINE, 0x0); in _rx_dck()
331 B_P0_TSSI_TRK_EN, 0x0); in _rx_dck()
346 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0); in _rck()
349 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RCK] RF0x00 = 0x%05x\n", in _rck()
353 rtw89_write_rf(rtwdev, path, RR_RCKC, RFREG_MASK, 0x00240); in _rck()
360 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RCK] rck_val = 0x%x, ret = %d\n", in _rck()
366 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RCK] RF 0x1b = 0x%x\n", in _rck()
372 rtw89_write32(rtwdev, R_AX_PHYREG_SET, 0xf); in _afe_init()
384 rtw89_phy_write32_mask(rtwdev, R_DRCK_V1, B_DRCK_V1_KICK, 0x1); in _drck()
391 rtw89_phy_write32_mask(rtwdev, R_DRCK_V1, B_DRCK_V1_KICK, 0x0); in _drck()
392 rtw89_phy_write32_mask(rtwdev, R_DRCK_FH, B_DRCK_LAT, 0x1); in _drck()
394 rtw89_phy_write32_mask(rtwdev, R_DRCK_FH, B_DRCK_LAT, 0x0); in _drck()
396 rtw89_phy_write32_mask(rtwdev, R_DRCK_V1, B_DRCK_V1_SEL, 0x0); in _drck()
399 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0xc0cc = 0x%x\n", in _drck()
407 rtw89_phy_write32_mask(rtwdev, R_ADDCK0, B_ADDCK0, 0x0); in _addck_backup()
408 dack->addck_d[0][0] = rtw89_phy_read32_mask(rtwdev, R_ADDCKR0, B_ADDCKR0_A0); in _addck_backup()
409 dack->addck_d[0][1] = rtw89_phy_read32_mask(rtwdev, R_ADDCKR0, B_ADDCKR0_A1); in _addck_backup()
411 rtw89_phy_write32_mask(rtwdev, R_ADDCK1, B_ADDCK1, 0x0); in _addck_backup()
412 dack->addck_d[1][0] = rtw89_phy_read32_mask(rtwdev, R_ADDCKR1, B_ADDCKR1_A0); in _addck_backup()
421 rtw89_phy_write32_mask(rtwdev, R_ADDCK0D, B_ADDCK0D_VAL, dack->addck_d[0][0]); in _addck_reload()
422 rtw89_phy_write32_mask(rtwdev, R_ADDCK0, B_ADDCK0_VAL, dack->addck_d[0][1] >> 6); in _addck_reload()
423 rtw89_phy_write32_mask(rtwdev, R_ADDCK0D, B_ADDCK0D_VAL2, dack->addck_d[0][1] & 0x3f); in _addck_reload()
424 rtw89_phy_write32_mask(rtwdev, R_ADDCK0, B_ADDCK0_MAN, 0x3); in _addck_reload()
427 rtw89_phy_write32_mask(rtwdev, R_ADDCK1D, B_ADDCK1D_VAL, dack->addck_d[1][0]); in _addck_reload()
429 rtw89_phy_write32_mask(rtwdev, R_ADDCK1D, B_ADDCK1D_VAL2, dack->addck_d[1][1] & 0x3f); in _addck_reload()
430 rtw89_phy_write32_mask(rtwdev, R_ADDCK1, B_ADDCK1_MAN, 0x3); in _addck_reload()
438 rtw89_phy_write32_mask(rtwdev, R_P0_NRBW, B_P0_NRBW_DBG, 0x1); in _dack_backup_s0()
440 for (i = 0; i < RTW89_DACK_MSBK_NR; i++) { in _dack_backup_s0()
442 dack->msbk_d[0][0][i] = in _dack_backup_s0()
445 dack->msbk_d[0][1][i] = in _dack_backup_s0()
449 dack->biask_d[0][0] = in _dack_backup_s0()
451 dack->biask_d[0][1] = in _dack_backup_s0()
454 dack->dadck_d[0][0] = in _dack_backup_s0()
456 dack->dadck_d[0][1] = in _dack_backup_s0()
465 rtw89_phy_write32_mask(rtwdev, R_P1_DBGMOD, B_P1_DBGMOD_ON, 0x1); in _dack_backup_s1()
467 for (i = 0; i < RTW89_DACK_MSBK_NR; i++) { in _dack_backup_s1()
469 dack->msbk_d[1][0][i] = in _dack_backup_s1()
476 dack->biask_d[1][0] = in _dack_backup_s1()
481 dack->dadck_d[1][0] = in _dack_backup_s1()
489 s32 dc_re = 0, dc_im = 0; in _check_addc()
497 for (i = 0; i < ADDC_T_AVG; i++) { in _check_addc()
499 dc_re += sign_extend32(FIELD_GET(0xfff000, tmp), 11); in _check_addc()
500 dc_im += sign_extend32(FIELD_GET(0xfff, tmp), 11); in _check_addc()
507 "[DACK]S%d,dc_re = 0x%x,dc_im =0x%x\n", path, dc_re, dc_im); in _check_addc()
517 rtw89_phy_write32_mask(rtwdev, R_ADDCK0, B_ADDCK0_MAN, 0x0); in _addck()
518 rtw89_phy_write32_mask(rtwdev, R_PATH1_SAMPL_DLY_T_V1, 0x30, 0x0); in _addck()
519 rtw89_phy_write32_mask(rtwdev, R_P0_NRBW, B_P0_NRBW_DBG, 0x1); in _addck()
520 rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_ADCCLK, 0x0); in _addck()
521 rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_FLTRST, 0x0); in _addck()
522 rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_FLTRST, 0x1); in _addck()
523 rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15_H, 0xf); in _addck()
524 rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_EN, 0x0); in _addck()
525 rtw89_phy_write32_mask(rtwdev, R_PATH0_SAMPL_DLY_T_V1, BIT(1), 0x1); in _addck()
526 rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15_H, 0x3); in _addck()
531 rtw89_phy_write32_mask(rtwdev, R_ADDCK0, B_ADDCK0_TRG, 0x1); in _addck()
532 rtw89_phy_write32_mask(rtwdev, R_ADDCK0, B_ADDCK0_TRG, 0x0); in _addck()
534 rtw89_phy_write32_mask(rtwdev, R_ADDCK0, B_ADDCK0, 0x1); in _addck()
537 false, rtwdev, R_ADDCKR0, BIT(0)); in _addck()
540 dack->addck_timeout[0] = true; in _addck()
546 rtw89_phy_write32_mask(rtwdev, R_PATH0_SAMPL_DLY_T_V1, BIT(1), 0x0); in _addck()
547 rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_EN, 0x1); in _addck()
548 rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15_H, 0xc); in _addck()
549 rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_ADCCLK, 0x1); in _addck()
550 rtw89_phy_write32_mask(rtwdev, R_P0_NRBW, B_P0_NRBW_DBG, 0x0); in _addck()
553 rtw89_phy_write32_mask(rtwdev, R_P1_DBGMOD, B_P1_DBGMOD_ON, 0x1); in _addck()
554 rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_ADCCLK, 0x0); in _addck()
555 rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_FLTRST, 0x0); in _addck()
556 rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_FLTRST, 0x1); in _addck()
557 rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15_H, 0xf); in _addck()
558 rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_EN, 0x0); in _addck()
559 rtw89_phy_write32_mask(rtwdev, R_PATH1_SAMPL_DLY_T_V1, BIT(1), 0x1); in _addck()
560 rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15_H, 0x3); in _addck()
565 rtw89_phy_write32_mask(rtwdev, R_ADDCK1, B_ADDCK1_TRG, 0x1); in _addck()
566 rtw89_phy_write32_mask(rtwdev, R_ADDCK1, B_ADDCK1_TRG, 0x0); in _addck()
568 rtw89_phy_write32_mask(rtwdev, R_ADDCK1, B_ADDCK1, 0x1); in _addck()
571 false, rtwdev, R_ADDCKR1, BIT(0)); in _addck()
580 rtw89_phy_write32_mask(rtwdev, R_PATH1_SAMPL_DLY_T_V1, BIT(1), 0x0); in _addck()
581 rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_EN, 0x1); in _addck()
582 rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15_H, 0xc); in _addck()
583 rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_ADCCLK, 0x1); in _addck()
584 rtw89_phy_write32_mask(rtwdev, R_P1_DBGMOD, B_P1_DBGMOD_ON, 0x0); in _addck()
603 if (rtw89_phy_read32_mask(rtwdev, R_DACK_S0P0, B_DACK_S0P0_OK) == 0 || in _dack_s0_check_done()
604 rtw89_phy_read32_mask(rtwdev, R_DACK_S0P1, B_DACK_S0P1_OK) == 0) in _dack_s0_check_done()
607 if (rtw89_phy_read32_mask(rtwdev, R_DACK_S0P2, B_DACK_S0P2_OK) == 0 || in _dack_s0_check_done()
608 rtw89_phy_read32_mask(rtwdev, R_DACK_S0P3, B_DACK_S0P3_OK) == 0) in _dack_s0_check_done()
627 dack->msbk_timeout[0] = true; in _dack_s0()
637 dack->dadck_timeout[0] = true; in _dack_s0()
646 rtw89_phy_write32_mask(rtwdev, R_P0_NRBW, B_P0_NRBW_DBG, 0x0); in _dack_s0()
652 if (rtw89_phy_read32_mask(rtwdev, R_DACK_S1P0, B_DACK_S1P0_OK) == 0 && in _dack_s1_check_done()
653 rtw89_phy_read32_mask(rtwdev, R_DACK_S1P1, B_DACK_S1P1_OK) == 0) in _dack_s1_check_done()
656 if (rtw89_phy_read32_mask(rtwdev, R_DACK10S, B_DACK_S1P2_OK) == 0 && in _dack_s1_check_done()
657 rtw89_phy_read32_mask(rtwdev, R_DACK11S, B_DACK_S1P3_OK) == 0) in _dack_s1_check_done()
696 rtw89_phy_write32_mask(rtwdev, R_P1_DBGMOD, B_P1_DBGMOD_ON, 0x0); in _dack_s1()
712 "[DACK]S0 ADC_DCK ic = 0x%x, qc = 0x%x\n", in _dack_dump()
713 dack->addck_d[0][0], dack->addck_d[0][1]); in _dack_dump()
715 "[DACK]S1 ADC_DCK ic = 0x%x, qc = 0x%x\n", in _dack_dump()
716 dack->addck_d[1][0], dack->addck_d[1][1]); in _dack_dump()
718 "[DACK]S0 DAC_DCK ic = 0x%x, qc = 0x%x\n", in _dack_dump()
719 dack->dadck_d[0][0], dack->dadck_d[0][1]); in _dack_dump()
721 "[DACK]S1 DAC_DCK ic = 0x%x, qc = 0x%x\n", in _dack_dump()
722 dack->dadck_d[1][0], dack->dadck_d[1][1]); in _dack_dump()
724 "[DACK]S0 biask ic = 0x%x, qc = 0x%x\n", in _dack_dump()
725 dack->biask_d[0][0], dack->biask_d[0][1]); in _dack_dump()
727 "[DACK]S1 biask ic = 0x%x, qc = 0x%x\n", in _dack_dump()
728 dack->biask_d[1][0], dack->biask_d[1][1]); in _dack_dump()
731 for (i = 0; i < 0x10; i++) { in _dack_dump()
732 t = dack->msbk_d[0][0][i]; in _dack_dump()
733 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n", t); in _dack_dump()
737 for (i = 0; i < RTW89_DACK_MSBK_NR; i++) { in _dack_dump()
738 t = dack->msbk_d[0][1][i]; in _dack_dump()
739 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n", t); in _dack_dump()
743 for (i = 0; i < RTW89_DACK_MSBK_NR; i++) { in _dack_dump()
744 t = dack->msbk_d[1][0][i]; in _dack_dump()
745 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n", t); in _dack_dump()
749 for (i = 0; i < RTW89_DACK_MSBK_NR; i++) { in _dack_dump()
751 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n", t); in _dack_dump()
761 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]DACK 0x1\n"); in _dac_cal()
769 rtw89_write_rf(rtwdev, RF_PATH_A, RR_RSV1, RR_RSV1_RST, 0x0); in _dac_cal()
770 rtw89_write_rf(rtwdev, RF_PATH_B, RR_RSV1, RR_RSV1_RST, 0x0); in _dac_cal()
771 rtw89_write_rf(rtwdev, RF_PATH_A, RR_MOD, RFREG_MASK, 0x337e1); in _dac_cal()
772 rtw89_write_rf(rtwdev, RF_PATH_B, RR_MOD, RFREG_MASK, 0x337e1); in _dac_cal()
777 rtw89_write_rf(rtwdev, RF_PATH_A, RR_MODOPT, RFREG_MASK, 0x0); in _dac_cal()
778 rtw89_write_rf(rtwdev, RF_PATH_B, RR_MODOPT, RFREG_MASK, 0x0); in _dac_cal()
785 rtw89_write_rf(rtwdev, RF_PATH_A, RR_RSV1, RR_RSV1_RST, 0x1); in _dac_cal()
786 rtw89_write_rf(rtwdev, RF_PATH_B, RR_RSV1, RR_RSV1_RST, 0x1); in _dac_cal()
798 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, 0xc); in _iqk_rxk_setting()
799 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL2G, 0x1); in _iqk_rxk_setting()
804 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, 0xc); in _iqk_rxk_setting()
805 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL5G, 0x1); in _iqk_rxk_setting()
823 rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x1); in _iqk_one_shot()
824 iqk_cmd = 0x108 | (1 << (4 + path)); in _iqk_one_shot()
827 rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x1); in _iqk_one_shot()
828 iqk_cmd = 0x208 | (1 << (4 + path)); in _iqk_one_shot()
831 rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x1); in _iqk_one_shot()
832 iqk_cmd = 0x308 | (1 << (4 + path)); in _iqk_one_shot()
835 rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x0); in _iqk_one_shot()
836 iqk_cmd = 0x008 | (1 << (path + 4)) | in _iqk_one_shot()
837 (((0x8 + iqk_info->iqk_bw[path]) & 0xf) << 8); in _iqk_one_shot()
840 iqk_cmd = 0x508 | (1 << (4 + path)) | (path << 1); in _iqk_one_shot()
843 rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x1); in _iqk_one_shot()
844 iqk_cmd = 0x008 | (1 << (path + 4)) | in _iqk_one_shot()
845 (((0xb + iqk_info->iqk_bw[path]) & 0xf) << 8); in _iqk_one_shot()
848 rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x0); in _iqk_one_shot()
849 rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_TXT, 0x011); in _iqk_one_shot()
850 iqk_cmd = 0x408 | (1 << (4 + path)); in _iqk_one_shot()
853 rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x1); in _iqk_one_shot()
854 rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_RXT, 0x011); in _iqk_one_shot()
855 iqk_cmd = 0x608 | (1 << (4 + path)); in _iqk_one_shot()
864 rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x0); in _iqk_one_shot()
877 for (gp = 0; gp < RTW8852B_RXK_GROUP_NR; gp++) { in _rxk_group_sel()
900 B_CFIR_LUT_SEL, 0x1); in _rxk_group_sel()
902 B_CFIR_LUT_SET, 0x0); in _rxk_group_sel()
910 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL5G, 0x0); in _rxk_group_sel()
913 iqk_info->nb_rxcfir[path] = 0x40000002; in _rxk_group_sel()
915 B_IQK_RES_RXCFIR, 0x0); in _rxk_group_sel()
918 iqk_info->nb_rxcfir[path] = 0x40000000; in _rxk_group_sel()
920 B_IQK_RES_RXCFIR, 0x5); in _rxk_group_sel()
931 const u8 gp = 0x3; in _iqk_nbrxk()
956 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SEL, 0x1); in _iqk_nbrxk()
957 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SET, 0x0); in _iqk_nbrxk()
959 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RFREG_MASK, 0x80013); in _iqk_nbrxk()
965 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL5G, 0x0); in _iqk_nbrxk()
969 rtw89_phy_read32_mask(rtwdev, R_RXIQC + (path << 8), MASKDWORD) | 0x2; in _iqk_nbrxk()
971 iqk_info->nb_rxcfir[path] = 0x40000002; in _iqk_nbrxk()
981 rtw89_phy_write32_mask(rtwdev, R_P0_NRBW, B_P0_NRBW_DBG, 0x1); in _iqk_rxclk_setting()
982 rtw89_phy_write32_mask(rtwdev, R_P1_DBGMOD, B_P1_DBGMOD_ON, 0x1); in _iqk_rxclk_setting()
984 rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15, 0x0f); in _iqk_rxclk_setting()
986 rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15, 0x03); in _iqk_rxclk_setting()
987 rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_15, 0xa001); in _iqk_rxclk_setting()
989 rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_15, 0xa041); in _iqk_rxclk_setting()
990 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK, B_P0_RXCK_VAL, 0x2); in _iqk_rxclk_setting()
991 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK, B_P0_RXCK_ON, 0x1); in _iqk_rxclk_setting()
992 rtw89_phy_write32_mask(rtwdev, R_P1_RXCK, B_P1_RXCK_VAL, 0x2); in _iqk_rxclk_setting()
993 rtw89_phy_write32_mask(rtwdev, R_P1_RXCK, B_P1_RXCK_ON, 0x1); in _iqk_rxclk_setting()
994 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_UPD_CLK_ADC_ON, 0x1); in _iqk_rxclk_setting()
995 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_UPD_CLK_ADC_VAL, 0x1); in _iqk_rxclk_setting()
997 rtw89_phy_write32_mask(rtwdev, R_P0_NRBW, B_P0_NRBW_DBG, 0x1); in _iqk_rxclk_setting()
998 rtw89_phy_write32_mask(rtwdev, R_P1_DBGMOD, B_P1_DBGMOD_ON, 0x1); in _iqk_rxclk_setting()
1000 rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15, 0x0f); in _iqk_rxclk_setting()
1002 rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15, 0x03); in _iqk_rxclk_setting()
1003 rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_15, 0xa001); in _iqk_rxclk_setting()
1005 rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_15, 0xa041); in _iqk_rxclk_setting()
1006 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK, B_P0_RXCK_VAL, 0x1); in _iqk_rxclk_setting()
1007 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK, B_P0_RXCK_ON, 0x1); in _iqk_rxclk_setting()
1008 rtw89_phy_write32_mask(rtwdev, R_P1_RXCK, B_P1_RXCK_VAL, 0x1); in _iqk_rxclk_setting()
1009 rtw89_phy_write32_mask(rtwdev, R_P1_RXCK, B_P1_RXCK_ON, 0x1); in _iqk_rxclk_setting()
1010 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_UPD_CLK_ADC_ON, 0x1); in _iqk_rxclk_setting()
1011 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_UPD_CLK_ADC_VAL, 0x0); in _iqk_rxclk_setting()
1022 for (gp = 0x0; gp < RTW8852B_RXK_GROUP_NR; gp++) { in _txk_group_sel()
1049 B_CFIR_LUT_SEL, 0x1); in _txk_group_sel()
1051 B_CFIR_LUT_SET, 0x1); in _txk_group_sel()
1053 B_CFIR_LUT_G2, 0x0); in _txk_group_sel()
1056 rtw89_phy_write32_mask(rtwdev, R_NCTL_N1, B_NCTL_N1_CIP, 0x00); in _txk_group_sel()
1064 iqk_info->nb_txcfir[path] = 0x40000002; in _txk_group_sel()
1066 B_IQK_RES_TXCFIR, 0x0); in _txk_group_sel()
1069 iqk_info->nb_txcfir[path] = 0x40000000; in _txk_group_sel()
1071 B_IQK_RES_TXCFIR, 0x5); in _txk_group_sel()
1082 u8 gp = 0x2; in _iqk_nbtxk()
1109 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SEL, 0x1); in _iqk_nbtxk()
1110 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SET, 0x1); in _iqk_nbtxk()
1111 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_G2, 0x0); in _iqk_nbtxk()
1113 rtw89_phy_write32_mask(rtwdev, R_NCTL_N1, B_NCTL_N1_CIP, 0x00); in _iqk_nbtxk()
1119 MASKDWORD) | 0x2; in _iqk_nbtxk()
1121 iqk_info->nb_txcfir[path] = 0x40000002; in _iqk_nbtxk()
1133 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x2); in _lok_res_table()
1135 rtw89_write_rf(rtwdev, path, RR_LUTWA, RFREG_MASK, 0x0); in _lok_res_table()
1137 rtw89_write_rf(rtwdev, path, RR_LUTWA, RFREG_MASK, 0x1); in _lok_res_table()
1139 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x0); in _lok_res_table()
1140 rtw89_write_rf(rtwdev, path, RR_TXVBUF, RR_TXVBUF_DACEN, 0x1); in _lok_res_table()
1142 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x7c = %x\n", path, in _lok_res_table()
1162 if (core_i < 0x2 || core_i > 0x1d || core_q < 0x2 || core_q > 0x1d) in _lok_finetune_check()
1173 if (vbuff_i < 0x2 || vbuff_i > 0x3d || vbuff_q < 0x2 || vbuff_q > 0x3d) in _lok_finetune_check()
1181 "[IQK]S%x, lok_idac[%x][%x] = 0x%x\n", path, ch, path, in _lok_finetune_check()
1184 "[IQK]S%x, lok_vbuf[%x][%x] = 0x%x\n", path, ch, path, in _lok_finetune_check()
1195 rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_TXT, 0x021); in _iqk_lok()
1199 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0, 0x0); in _iqk_lok()
1200 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1, 0x6); in _iqk_lok()
1203 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0, 0x0); in _iqk_lok()
1204 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1, 0x4); in _iqk_lok()
1212 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x0); in _iqk_lok()
1215 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x0); in _iqk_lok()
1221 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), MASKDWORD, 0x9); in _iqk_lok()
1223 iqk_info->lok_cor_fail[0][path] = tmp; in _iqk_lok()
1227 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x12); in _iqk_lok()
1230 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x12); in _iqk_lok()
1236 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), MASKDWORD, 0x24); in _iqk_lok()
1241 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x0); in _iqk_lok()
1244 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x0); in _iqk_lok()
1250 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), MASKDWORD, 0x9); in _iqk_lok()
1251 rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_TXT, 0x021); in _iqk_lok()
1253 iqk_info->lok_fin_fail[0][path] = tmp; in _iqk_lok()
1257 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x12); in _iqk_lok()
1260 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0x12); in _iqk_lok()
1266 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), MASKDWORD, 0x24); in _iqk_lok()
1278 rtw89_write_rf(rtwdev, path, RR_XALNA2, RR_XALNA2_SW2, 0x00); in _iqk_txk_setting()
1279 rtw89_write_rf(rtwdev, path, RR_TXG1, RR_TXG1_ATT2, 0x0); in _iqk_txk_setting()
1280 rtw89_write_rf(rtwdev, path, RR_TXG1, RR_TXG1_ATT1, 0x0); in _iqk_txk_setting()
1281 rtw89_write_rf(rtwdev, path, RR_TXG2, RR_TXG2_ATT0, 0x1); in _iqk_txk_setting()
1282 rtw89_write_rf(rtwdev, path, RR_TXGA, RR_TXGA_LOK_EXT, 0x0); in _iqk_txk_setting()
1283 rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x1); in _iqk_txk_setting()
1284 rtw89_write_rf(rtwdev, path, RR_LUTWA, RR_LUTWA_M1, 0x00); in _iqk_txk_setting()
1285 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_IQK, 0x403e); in _iqk_txk_setting()
1289 rtw89_write_rf(rtwdev, path, RR_XGLNA2, RR_XGLNA2_SW, 0x00); in _iqk_txk_setting()
1290 rtw89_write_rf(rtwdev, path, RR_BIASA, RR_BIASA_A, 0x1); in _iqk_txk_setting()
1291 rtw89_write_rf(rtwdev, path, RR_TXGA, RR_TXGA_LOK_EXT, 0x0); in _iqk_txk_setting()
1292 rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x1); in _iqk_txk_setting()
1293 rtw89_write_rf(rtwdev, path, RR_LUTWA, RR_LUTWA_M1, 0x80); in _iqk_txk_setting()
1294 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_IQK, 0x403e); in _iqk_txk_setting()
1304 rtw89_phy_write32_mask(rtwdev, R_P0_NRBW, B_P0_NRBW_DBG, 0x1); in _iqk_txclk_setting()
1305 rtw89_phy_write32_mask(rtwdev, R_P1_DBGMOD, B_P1_DBGMOD_ON, 0x1); in _iqk_txclk_setting()
1307 rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15, 0x1f); in _iqk_txclk_setting()
1309 rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15, 0x13); in _iqk_txclk_setting()
1310 rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_15, 0x0001); in _iqk_txclk_setting()
1312 rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_15, 0x0041); in _iqk_txclk_setting()
1321 flag = iqk_info->lok_cor_fail[0][path]; in _iqk_info_iqk()
1323 flag = iqk_info->lok_fin_fail[0][path]; in _iqk_info_iqk()
1325 flag = iqk_info->iqk_tx_fail[0][path]; in _iqk_info_iqk()
1327 flag = iqk_info->iqk_rx_fail[0][path]; in _iqk_info_iqk()
1351 u8 ibias = 0x1; in _iqk_by_path()
1357 for (i = 0; i < try; i++) { in _iqk_by_path()
1370 iqk_info->iqk_tx_fail[0][path] = _iqk_nbtxk(rtwdev, phy_idx, path); in _iqk_by_path()
1372 iqk_info->iqk_tx_fail[0][path] = _txk_group_sel(rtwdev, phy_idx, path); in _iqk_by_path()
1378 iqk_info->iqk_rx_fail[0][path] = _iqk_nbrxk(rtwdev, phy_idx, path); in _iqk_by_path()
1380 iqk_info->iqk_rx_fail[0][path] = _rxk_group_sel(rtwdev, phy_idx, path); in _iqk_by_path()
1395 for (idx = 0; idx < RTW89_IQK_CHS_NR; idx++) { in _iqk_get_ch_info()
1396 if (iqk_info->iqk_mcc_ch[idx][path] == 0) { in _iqk_get_ch_info()
1406 idx = 0; in _iqk_get_ch_info()
1419 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x18= 0x%x, idx = %x\n", in _iqk_get_ch_info()
1421 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x18= 0x%x\n", in _iqk_get_ch_info()
1423 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]times = 0x%x, ch =%x\n", in _iqk_get_ch_info()
1425 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]iqk_mcc_ch[%x][%x] = 0x%x\n", in _iqk_get_ch_info()
1428 if (reg_35c == 0x01) in _iqk_get_ch_info()
1429 iqk_info->syn1to2 = 0x1; in _iqk_get_ch_info()
1431 iqk_info->syn1to2 = 0x0; in _iqk_get_ch_info()
1434 "[IQK]S%x, iqk_info->syn1to2= 0x%x\n", path, in _iqk_get_ch_info()
1438 /* 2GHz/5GHz/6GHz = 0/1/2 */ in _iqk_get_ch_info()
1441 /* 20/40/80 = 0/1/2 */ in _iqk_get_ch_info()
1463 0x00000e19 + (path << 4)); in _iqk_restore()
1468 rtw89_phy_write32_mask(rtwdev, R_NCTL_N1, B_NCTL_N1_CIP, 0x00); in _iqk_restore()
1469 rtw89_phy_write32_mask(rtwdev, R_NCTL_RPT, MASKDWORD, 0x00000000); in _iqk_restore()
1470 rtw89_phy_write32_mask(rtwdev, R_KIP_SYSCFG, MASKDWORD, 0x80000000); in _iqk_restore()
1471 rtw89_phy_write32_mask(rtwdev, R_CFIR_SYS, B_IQK_RES_K, 0x0); in _iqk_restore()
1472 rtw89_phy_write32_mask(rtwdev, R_IQRSN, B_IQRSN_K1, 0x0); in _iqk_restore()
1473 rtw89_phy_write32_mask(rtwdev, R_IQRSN, B_IQRSN_K2, 0x0); in _iqk_restore()
1474 rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x0); in _iqk_restore()
1475 rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x0); in _iqk_restore()
1476 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, 0x3); in _iqk_restore()
1477 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x1); in _iqk_restore()
1478 rtw89_write_rf(rtwdev, path, RR_BBDC, RR_BBDC_SEL, 0x1); in _iqk_restore()
1503 for (i = 0; i < size; i++, def++) in _iqk_afebb_restore()
1518 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0); in _iqk_preset()
1519 rtw89_write_rf(rtwdev, path, RR_BBDC, RR_BBDC_SEL, 0x0); in _iqk_preset()
1520 rtw89_phy_write32_mask(rtwdev, R_NCTL_RPT, MASKDWORD, 0x00000080); in _iqk_preset()
1521 rtw89_phy_write32_mask(rtwdev, R_KIP_SYSCFG, MASKDWORD, 0x81ff010a); in _iqk_preset()
1523 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK](1)S%x, 0x8%x54 = 0x%x\n", path, 1 << path, in _iqk_preset()
1525 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK](1)S%x, 0x8%x04 = 0x%x\n", path, 1 << path, in _iqk_preset()
1549 for (i = 0; i < size; i++, def++) in _iqk_macbb_setting()
1558 rtw89_phy_write32_mask(rtwdev, R_IQKINF, MASKDWORD, 0x0); in _iqk_init()
1569 iqk_info->iqk_times = 0x0; in _iqk_init()
1571 for (idx = 0; idx < RTW89_IQK_CHS_NR; idx++) { in _iqk_init()
1572 iqk_info->iqk_channel[idx] = 0x0; in _iqk_init()
1573 for (path = 0; path < RTW8852B_IQK_SS; path++) { in _iqk_init()
1578 iqk_info->iqk_mcc_ch[idx][path] = 0x0; in _iqk_init()
1579 iqk_info->iqk_table_idx[path] = 0x0; in _iqk_init()
1590 for (path = 0; path < RF_PATH_MAX; path++) { in _wait_rx_mode()
1627 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]Test Ver 0x%x\n", iqk_info->version); in _doiqk()
1630 _rfk_backup_bb_reg(rtwdev, &backup_bb_val[0]); in _doiqk()
1631 _rfk_backup_rf_reg(rtwdev, &backup_rf_val[path][0], path); in _doiqk()
1637 _rfk_restore_bb_reg(rtwdev, &backup_bb_val[0]); in _doiqk()
1638 _rfk_restore_rf_reg(rtwdev, &backup_rf_val[path][0], path); in _doiqk()
1669 for (i = 0; i < RTW8852B_DPK_KIP_REG_NUM; i++) { in _dpk_bkup_kip()
1672 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] Backup 0x%x = %x\n", in _dpk_bkup_kip()
1682 for (i = 0; i < RTW8852B_DPK_KIP_REG_NUM; i++) { in _dpk_reload_kip()
1685 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] Reload 0x%x = %x\n", in _dpk_reload_kip()
1696 val = 0x3 >> order; in _dpk_order_convert()
1698 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] convert MDPD order to 0x%x\n", val); in _dpk_order_convert()
1724 dpk_cmd = (id << 8) | (0x19 + (path << 4)); in _dpk_one_shot()
1727 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val == 0x55, in _dpk_one_shot()
1729 rtwdev, 0xbff8, MASKBYTE0); in _dpk_one_shot()
1735 rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, MASKDWORD, 0x00030000); in _dpk_one_shot()
1737 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val == 0x8000, in _dpk_one_shot()
1739 rtwdev, 0x80fc, MASKLWORD); in _dpk_one_shot()
1743 rtw89_phy_write32_mask(rtwdev, R_NCTL_N1, MASKBYTE0, 0x0); in _dpk_one_shot()
1746 "[DPK] one-shot for %s = 0x%x\n", in _dpk_one_shot()
1747 id == 0x06 ? "LBK_RXIQK" : in _dpk_one_shot()
1748 id == 0x10 ? "SYNC" : in _dpk_one_shot()
1749 id == 0x11 ? "MDPK_IDL" : in _dpk_one_shot()
1750 id == 0x12 ? "MDPK_MPA" : in _dpk_one_shot()
1751 id == 0x13 ? "GAIN_LOSS" : in _dpk_one_shot()
1752 id == 0x14 ? "PWR_CAL" : in _dpk_one_shot()
1753 id == 0x15 ? "DPK_RXAGC" : in _dpk_one_shot()
1754 id == 0x16 ? "KIP_PRESET" : in _dpk_one_shot()
1755 id == 0x17 ? "KIP_RESTORE" : "DPK_TXAGC", in _dpk_one_shot()
1762 rtw89_write_rf(rtwdev, path, RR_RXBB2, RR_EN_TIA_IDA, 0x3); in _dpk_rx_dck()
1783 dpk->bp[path][kidx].band == 0 ? "2G" : in _dpk_information()
1786 dpk->bp[path][kidx].bw == 0 ? "20M" : in _dpk_information()
1800 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW1, B_P0_CFCH_EX, 0x1); in _dpk_bb_afe_setting()
1801 rtw89_phy_write32_mask(rtwdev, R_PATH1_BW_SEL_V1, B_PATH1_BW_SEL_EX, 0x1); in _dpk_bb_afe_setting()
1821 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW1, B_P0_CFCH_EX, 0x0); in _dpk_bb_afe_restore()
1822 rtw89_phy_write32_mask(rtwdev, R_PATH1_BW_SEL_V1, B_PATH1_BW_SEL_EX, 0x0); in _dpk_bb_afe_restore()
1842 rtw89_phy_write32_mask(rtwdev, R_DPD_COM + (path << 8), B_DPD_COM_OF, 0x1); in _dpk_kip_restore()
1855 rtw89_phy_write32_mask(rtwdev, R_MDPK_RX_DCK, B_MDPK_RX_DCK_EN, 0x1); in _dpk_lbk_rxiqk()
1856 rtw89_phy_write32_mask(rtwdev, R_IQK_RES + (path << 8), B_IQK_RES_RXCFIR, 0x0); in _dpk_lbk_rxiqk()
1860 rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASKMODE, 0xd); in _dpk_lbk_rxiqk()
1861 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_PLLEN, 0x1); in _dpk_lbk_rxiqk()
1863 if (cur_rxbb >= 0x11) in _dpk_lbk_rxiqk()
1864 rtw89_write_rf(rtwdev, path, RR_TXIQK, RR_TXIQK_ATT1, 0x13); in _dpk_lbk_rxiqk()
1865 else if (cur_rxbb <= 0xa) in _dpk_lbk_rxiqk()
1866 rtw89_write_rf(rtwdev, path, RR_TXIQK, RR_TXIQK_ATT1, 0x00); in _dpk_lbk_rxiqk()
1868 rtw89_write_rf(rtwdev, path, RR_TXIQK, RR_TXIQK_ATT1, 0x05); in _dpk_lbk_rxiqk()
1870 rtw89_write_rf(rtwdev, path, RR_XGLNA2, RR_XGLNA2_SW, 0x0); in _dpk_lbk_rxiqk()
1871 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x0); in _dpk_lbk_rxiqk()
1872 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RFREG_MASK, 0x80014); in _dpk_lbk_rxiqk()
1875 rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x1); in _dpk_lbk_rxiqk()
1876 rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_RXT, 0x025); in _dpk_lbk_rxiqk()
1880 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d LBK RXIQC = 0x%x\n", path, in _dpk_lbk_rxiqk()
1883 rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x0); in _dpk_lbk_rxiqk()
1884 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_PLLEN, 0x0); in _dpk_lbk_rxiqk()
1885 rtw89_phy_write32_mask(rtwdev, R_MDPK_RX_DCK, B_MDPK_RX_DCK_EN, 0x0); in _dpk_lbk_rxiqk()
1886 rtw89_phy_write32_mask(rtwdev, R_KPATH_CFG, B_KPATH_CFG_ED, 0x0); in _dpk_lbk_rxiqk()
1887 rtw89_phy_write32_mask(rtwdev, R_LOAD_COEF + (path << 8), B_LOAD_COEF_DI, 0x1); in _dpk_lbk_rxiqk()
1888 rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASKMODE, 0x5); in _dpk_lbk_rxiqk()
1895 rtw89_write_rf(rtwdev, path, RR_TM, RR_TM_TRI, 0x1); in _dpk_get_thermal()
1896 rtw89_write_rf(rtwdev, path, RR_TM, RR_TM_TRI, 0x0); in _dpk_get_thermal()
1897 rtw89_write_rf(rtwdev, path, RR_TM, RR_TM_TRI, 0x1); in _dpk_get_thermal()
1903 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] thermal@DPK = 0x%x\n", in _dpk_get_thermal()
1913 rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASK, 0x50220); in _dpk_rf_setting()
1914 rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_FATT, 0xf2); in _dpk_rf_setting()
1915 rtw89_write_rf(rtwdev, path, RR_LUTDBG, RR_LUTDBG_TIA, 0x1); in _dpk_rf_setting()
1916 rtw89_write_rf(rtwdev, path, RR_TIA, RR_TIA_N6, 0x1); in _dpk_rf_setting()
1918 rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASK, 0x50220); in _dpk_rf_setting()
1919 rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RAA2_SWATT, 0x5); in _dpk_rf_setting()
1920 rtw89_write_rf(rtwdev, path, RR_LUTDBG, RR_LUTDBG_TIA, 0x1); in _dpk_rf_setting()
1921 rtw89_write_rf(rtwdev, path, RR_TIA, RR_TIA_N6, 0x1); in _dpk_rf_setting()
1922 rtw89_write_rf(rtwdev, path, RR_RXA_LNA, RFREG_MASK, 0x920FC); in _dpk_rf_setting()
1923 rtw89_write_rf(rtwdev, path, RR_XALNA2, RFREG_MASK, 0x002C0); in _dpk_rf_setting()
1924 rtw89_write_rf(rtwdev, path, RR_IQGEN, RFREG_MASK, 0x38800); in _dpk_rf_setting()
1927 rtw89_write_rf(rtwdev, path, RR_RCKD, RR_RCKD_BW, 0x1); in _dpk_rf_setting()
1929 rtw89_write_rf(rtwdev, path, RR_BTC, RR_BTC_RXBB, 0x0); in _dpk_rf_setting()
1932 "[DPK] ARF 0x0/0x11/0x1a = 0x%x/ 0x%x/ 0x%x\n", in _dpk_rf_setting()
1943 B_RXIQC_BYPASS2, 0x1); in _dpk_bypass_rxcfir()
1945 B_RXIQC_BYPASS, 0x1); in _dpk_bypass_rxcfir()
1947 "[DPK] Bypass RXIQC (0x8%d3c = 0x%x)\n", 1 + path, in _dpk_bypass_rxcfir()
1954 "[DPK] restore 0x8%d3c = 0x%x\n", 1 + path, in _dpk_bypass_rxcfir()
1968 rtw89_phy_write32_mask(rtwdev, R_TPG_MOD, B_TPG_MOD_F, 0x2); in _dpk_tpg_sel()
1970 rtw89_phy_write32_mask(rtwdev, R_TPG_MOD, B_TPG_MOD_F, 0x1); in _dpk_tpg_sel()
1982 val = 0x80 + kidx * 0x20 + gain * 0x10; in _dpk_table_select()
1985 "[DPK] table select for Kidx[%d], Gain[%d] (0x%x)\n", kidx, in _dpk_table_select()
2010 rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, B_KIP_RPT1_SEL, 0x9); in _dpk_sync_check()
2043 rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, B_KIP_RPT1_SEL, 0x0); in _dpk_dgain_read()
2047 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] DGain = 0x%x\n", dgain); in _dpk_dgain_read()
2055 0xbf1, 0xaa5, 0x97d, 0x875, 0x789, 0x6b7, 0x5fc, 0x556, in _dpk_dgain_mapping()
2056 0x4c1, 0x43d, 0x3c7, 0x35e, 0x2ac, 0x262, 0x220 in _dpk_dgain_mapping()
2060 if (dgain >= bnd[0]) in _dpk_dgain_mapping()
2061 offset = 0x6; in _dpk_dgain_mapping()
2062 else if (bnd[0] > dgain && dgain >= bnd[1]) in _dpk_dgain_mapping()
2063 offset = 0x6; in _dpk_dgain_mapping()
2065 offset = 0x5; in _dpk_dgain_mapping()
2067 offset = 0x4; in _dpk_dgain_mapping()
2069 offset = 0x3; in _dpk_dgain_mapping()
2071 offset = 0x2; in _dpk_dgain_mapping()
2073 offset = 0x1; in _dpk_dgain_mapping()
2075 offset = 0x0; in _dpk_dgain_mapping()
2077 offset = 0xff; in _dpk_dgain_mapping()
2079 offset = 0xfe; in _dpk_dgain_mapping()
2081 offset = 0xfd; in _dpk_dgain_mapping()
2083 offset = 0xfc; in _dpk_dgain_mapping()
2085 offset = 0xfb; in _dpk_dgain_mapping()
2087 offset = 0xfa; in _dpk_dgain_mapping()
2089 offset = 0xf9; in _dpk_dgain_mapping()
2091 offset = 0xf8; in _dpk_dgain_mapping()
2093 offset = 0x0; in _dpk_dgain_mapping()
2102 rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, B_KIP_RPT1_SEL, 0x6); in _dpk_gainloss_read()
2103 rtw89_phy_write32_mask(rtwdev, R_DPK_CFG2, B_DPK_CFG2_ST, 0x1); in _dpk_gainloss_read()
2125 rtw89_phy_write32_mask(rtwdev, R_NCTL_RPT, MASKDWORD, 0x00000080); in _dpk_kip_pwr_clk_on()
2126 rtw89_phy_write32_mask(rtwdev, R_KIP_SYSCFG, MASKDWORD, 0x807f030a); in _dpk_kip_pwr_clk_on()
2127 rtw89_phy_write32_mask(rtwdev, R_CFIR_SYS + (path << 8), MASKDWORD, 0xce000a08); in _dpk_kip_pwr_clk_on()
2136 rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x1); in _dpk_kip_set_txagc()
2138 rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x0); in _dpk_kip_set_txagc()
2140 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] set TXAGC = 0x%x\n", txagc); in _dpk_kip_set_txagc()
2150 rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x1); in _dpk_kip_set_rxagc()
2152 rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_EN, 0x0); in _dpk_kip_set_rxagc()
2153 rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, B_KIP_RPT1_SEL_V1, 0x8); in _dpk_kip_set_rxagc()
2156 "[DPK] set RXBB = 0x%x (RF0x0[9:5] = 0x%x)\n", in _dpk_kip_set_rxagc()
2177 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] tmp_txagc (GL=%d) = 0x%x\n", in _dpk_set_offset()
2184 u32 val1_i = 0, val1_q = 0, val2_i = 0, val2_q = 0; in _dpk_pas_read()
2187 rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, MASKBYTE2, 0x06); in _dpk_pas_read()
2188 rtw89_phy_write32_mask(rtwdev, R_DPK_CFG2, B_DPK_CFG2_ST, 0x0); in _dpk_pas_read()
2189 rtw89_phy_write32_mask(rtwdev, R_DPK_CFG3, MASKBYTE2, 0x08); in _dpk_pas_read()
2192 rtw89_phy_write32_mask(rtwdev, R_DPK_CFG3, MASKBYTE3, 0x00); in _dpk_pas_read()
2198 rtw89_phy_write32_mask(rtwdev, R_DPK_CFG3, MASKBYTE3, 0x1f); in _dpk_pas_read()
2204 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] PAS_delta = 0x%x\n", in _dpk_pas_read()
2208 for (i = 0; i < 32; i++) { in _dpk_pas_read()
2211 "[DPK] PAS_Read[%02d]= 0x%08x\n", i, in _dpk_pas_read()
2229 u8 tmp_txagc, tmp_rxbb = 0, tmp_gl_idx = 0; in _dpk_agc()
2230 u8 goout = 0, agc_cnt = 0, limited_rxbb = 0; in _dpk_agc()
2231 u16 dgain = 0; in _dpk_agc()
2241 tmp_txagc = 0xff; in _dpk_agc()
2259 if (tmp_rxbb + offset > 0x1f) { in _dpk_agc()
2260 tmp_rxbb = 0x1f; in _dpk_agc()
2262 } else if (tmp_rxbb + offset < 0) { in _dpk_agc()
2263 tmp_rxbb = 0; in _dpk_agc()
2272 "[DPK] Adjust RXBB (%d) = 0x%x\n", offset, tmp_rxbb); in _dpk_agc()
2273 if (offset || agc_cnt == 0) { in _dpk_agc()
2291 if ((tmp_gl_idx == 0 && _dpk_pas_read(rtwdev, true)) || in _dpk_agc()
2294 else if (tmp_gl_idx == 0) in _dpk_agc()
2301 if (tmp_txagc == 0x2e) { in _dpk_agc()
2306 tmp_txagc = _dpk_set_offset(rtwdev, phy, path, 0x3); in _dpk_agc()
2313 if (tmp_txagc == 0x3f) { in _dpk_agc()
2318 tmp_txagc = _dpk_set_offset(rtwdev, phy, path, 0xfe); in _dpk_agc()
2333 } while (!goout && agc_cnt < 6 && limit-- > 0); in _dpk_agc()
2336 "[DPK] Txagc / RXBB for DPK = 0x%x / 0x%x\n", tmp_txagc, in _dpk_agc()
2345 case 0: in _dpk_set_mdpd_para()
2347 rtw89_phy_write32_mask(rtwdev, R_LDL_NORM, B_LDL_NORM_PN, 0x3); in _dpk_set_mdpd_para()
2348 rtw89_phy_write32_mask(rtwdev, R_MDPK_SYNC, B_MDPK_SYNC_MAN, 0x1); in _dpk_set_mdpd_para()
2362 "[DPK] Wrong MDPD order!!(0x%x)\n", order); in _dpk_set_mdpd_para()
2367 "[DPK] Set MDPD order to 0x%x for IDL\n", order); in _dpk_set_mdpd_para()
2377 _dpk_set_mdpd_para(rtwdev, 0x2); in _dpk_idl_mpa()
2379 _dpk_set_mdpd_para(rtwdev, 0x0); in _dpk_idl_mpa()
2388 const u16 pwsf = 0x78; in _dpk_fill_result()
2395 "[DPK] Fill txagc/ pwsf/ gs = 0x%x/ 0x%x/ 0x%x\n", txagc, in _dpk_fill_result()
2400 0x3F << ((gain << 3) + (kidx << 4)), txagc); in _dpk_fill_result()
2404 0x1FF << (gain << 4), pwsf); in _dpk_fill_result()
2406 rtw89_phy_write32_mask(rtwdev, R_LOAD_COEF + (path << 8), B_LOAD_COEF_MDPD, 0x1); in _dpk_fill_result()
2407 rtw89_phy_write32_mask(rtwdev, R_LOAD_COEF + (path << 8), B_LOAD_COEF_MDPD, 0x0); in _dpk_fill_result()
2410 if (dpk->dpk_gs[phy] == 0x7f) in _dpk_fill_result()
2412 MASKDWORD, 0x007f7f7f); in _dpk_fill_result()
2415 MASKDWORD, 0x005b5b5b); in _dpk_fill_result()
2419 rtw89_phy_write32_mask(rtwdev, R_DPD_V1 + (path << 8), MASKDWORD, 0x0); in _dpk_fill_result()
2420 rtw89_phy_write32_mask(rtwdev, R_MDPK_SYNC, B_MDPK_SYNC_SEL, 0x0); in _dpk_fill_result()
2434 for (idx = 0; idx < RTW89_DPK_BKUP_NUM; idx++) { in _dpk_reload_check()
2455 u8 txagc = 0x38, kidx = dpk->cur_idx[path]; in _dpk_main()
2474 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] Adjust txagc = 0x%x\n", txagc); in _dpk_main()
2476 if (txagc == 0xff) { in _dpk_main()
2504 static const u32 kip_reg[] = {0x813c, 0x8124, 0x8120}; in _dpk_cal_select()
2512 for (path = 0; path < RTW8852B_DPK_RF_PATH; path++) { in _dpk_cal_select()
2515 if (!reloaded[path] && dpk->bp[path][0].ch) in _dpk_cal_select()
2521 for (path = 0; path < RTW8852B_DPK_RF_PATH; path++) in _dpk_cal_select()
2522 dpk->cur_idx[path] = 0; in _dpk_cal_select()
2525 _rfk_backup_bb_reg(rtwdev, &backup_bb_val[0]); in _dpk_cal_select()
2527 for (path = 0; path < RTW8852B_DPK_RF_PATH; path++) { in _dpk_cal_select()
2529 _rfk_backup_rf_reg(rtwdev, &backup_rf_val[path][0], path); in _dpk_cal_select()
2537 for (path = 0; path < RTW8852B_DPK_RF_PATH; path++) { in _dpk_cal_select()
2543 _rfk_restore_bb_reg(rtwdev, &backup_bb_val[0]); in _dpk_cal_select()
2545 for (path = 0; path < RTW8852B_DPK_RF_PATH; path++) { in _dpk_cal_select()
2548 _rfk_restore_rf_reg(rtwdev, &backup_rf_val[path][0], path); in _dpk_cal_select()
2583 for (path = 0; path < RTW8852B_DPK_RF_PATH; path++) { in _dpk_force_bypass()
2593 "[DPK] ****** DPK Start (Ver: 0x%x, Cv: %d, RF_para: %d) ******\n", in _dpk()
2606 s8 txagc_bb, txagc_bb_tp, ini_diff = 0, txagc_ofst; in _dpk_track()
2614 for (path = 0; path < RF_PATH_NUM_8852B; path++) { in _dpk_track()
2635 0x0000003f); in _dpk_track()
2641 "[DPK_TRK] txagc_RF / track_idx = 0x%x / %d\n", in _dpk_track()
2652 "[DPK_TRK] txagc_bb_tp / txagc_bb = 0x%x / 0x%x\n", in _dpk_track()
2664 if (tmp == 0x1) { in _dpk_track()
2665 txagc_ofst = 0; in _dpk_track()
2676 if (tmp == 0x0) { in _dpk_track()
2677 pwsf[0] = dpk->bp[path][kidx].pwsf + in _dpk_track()
2682 pwsf[0] = dpk->bp[path][kidx].pwsf + ini_diff; in _dpk_track()
2687 pwsf[0] = (dpk->bp[path][kidx].pwsf + delta_ther[path]) & 0x1ff; in _dpk_track()
2688 pwsf[1] = (dpk->bp[path][kidx].pwsf + delta_ther[path]) & 0x1ff; in _dpk_track()
2694 "[DPK_TRK] New pwsf[0] / pwsf[1] = 0x%x / 0x%x\n", in _dpk_track()
2695 pwsf[0], pwsf[1]); in _dpk_track()
2699 B_DPD_BND_0, pwsf[0]); in _dpk_track()
2718 /* move dpd backoff to bb, and set dpd backoff to 0 */ in _set_dpd_backoff()
2719 dpk->dpk_gs[phy] = 0x7f; in _set_dpd_backoff()
2720 for (path = 0; path < RF_PATH_NUM_8852B; path++) { in _set_dpd_backoff()
2725 B_DPD_CFG, 0x7f7f7f); in _set_dpd_backoff()
2727 "[RFK] Set S%d DPD backoff to 0dB\n", path); in _set_dpd_backoff()
2730 dpk->dpk_gs[phy] = 0x5b; in _set_dpd_backoff()
2740 rtw89_write_rf(rtwdev, path, RR_TXPOW, RR_TXPOW_TXG, 0x1); in _tssi_rf_setting()
2742 rtw89_write_rf(rtwdev, path, RR_TXPOW, RR_TXPOW_TXA, 0x1); in _tssi_rf_setting()
2795 u32 __val = 0; \ in _tssi_set_tmeter_tbl()
2796 for (__i = 0; __i < 4; __i++) { \ in _tssi_set_tmeter_tbl()
2809 u8 thermal = 0xff; in _tssi_set_tmeter_tbl()
2810 s8 thm_ofst[64] = {0}; in _tssi_set_tmeter_tbl()
2811 u32 tmp = 0; in _tssi_set_tmeter_tbl()
2823 thm_up_a = rtw89_8852b_trk_cfg.delta_swingidx_5ga_p[0]; in _tssi_set_tmeter_tbl()
2824 thm_down_a = rtw89_8852b_trk_cfg.delta_swingidx_5ga_n[0]; in _tssi_set_tmeter_tbl()
2825 thm_up_b = rtw89_8852b_trk_cfg.delta_swingidx_5gb_p[0]; in _tssi_set_tmeter_tbl()
2826 thm_down_b = rtw89_8852b_trk_cfg.delta_swingidx_5gb_n[0]; in _tssi_set_tmeter_tbl()
2846 "[TSSI] ch=%d thermal_pathA=0x%x\n", ch, thermal); in _tssi_set_tmeter_tbl()
2848 rtw89_phy_write32_mask(rtwdev, R_P0_TMETER, B_P0_TMETER_DIS, 0x0); in _tssi_set_tmeter_tbl()
2849 rtw89_phy_write32_mask(rtwdev, R_P0_TMETER, B_P0_TMETER_TRK, 0x1); in _tssi_set_tmeter_tbl()
2851 if (thermal == 0xff) { in _tssi_set_tmeter_tbl()
2855 for (i = 0; i < 64; i += 4) { in _tssi_set_tmeter_tbl()
2856 rtw89_phy_write32(rtwdev, R_P0_TSSI_BASE + i, 0x0); in _tssi_set_tmeter_tbl()
2859 "[TSSI] write 0x%x val=0x%08x\n", in _tssi_set_tmeter_tbl()
2860 R_P0_TSSI_BASE + i, 0x0); in _tssi_set_tmeter_tbl()
2868 i = 0; in _tssi_set_tmeter_tbl()
2869 for (j = 0; j < 32; j++) in _tssi_set_tmeter_tbl()
2880 for (i = 0; i < 64; i += 4) { in _tssi_set_tmeter_tbl()
2885 "[TSSI] write 0x%x val=0x%08x\n", in _tssi_set_tmeter_tbl()
2886 0x5c00 + i, tmp); in _tssi_set_tmeter_tbl()
2889 rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, R_P0_RFCTM_RDY, 0x1); in _tssi_set_tmeter_tbl()
2890 rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, R_P0_RFCTM_RDY, 0x0); in _tssi_set_tmeter_tbl()
2896 "[TSSI] ch=%d thermal_pathB=0x%x\n", ch, thermal); in _tssi_set_tmeter_tbl()
2898 rtw89_phy_write32_mask(rtwdev, R_P1_TMETER, B_P1_TMETER_DIS, 0x0); in _tssi_set_tmeter_tbl()
2899 rtw89_phy_write32_mask(rtwdev, R_P1_TMETER, B_P1_TMETER_TRK, 0x1); in _tssi_set_tmeter_tbl()
2901 if (thermal == 0xff) { in _tssi_set_tmeter_tbl()
2905 for (i = 0; i < 64; i += 4) { in _tssi_set_tmeter_tbl()
2906 rtw89_phy_write32(rtwdev, R_TSSI_THOF + i, 0x0); in _tssi_set_tmeter_tbl()
2909 "[TSSI] write 0x%x val=0x%08x\n", in _tssi_set_tmeter_tbl()
2910 0x7c00 + i, 0x0); in _tssi_set_tmeter_tbl()
2918 i = 0; in _tssi_set_tmeter_tbl()
2919 for (j = 0; j < 32; j++) in _tssi_set_tmeter_tbl()
2930 for (i = 0; i < 64; i += 4) { in _tssi_set_tmeter_tbl()
2935 "[TSSI] write 0x%x val=0x%08x\n", in _tssi_set_tmeter_tbl()
2936 0x7c00 + i, tmp); in _tssi_set_tmeter_tbl()
2939 rtw89_phy_write32_mask(rtwdev, R_P1_RFCTM, R_P1_RFCTM_RDY, 0x1); in _tssi_set_tmeter_tbl()
2940 rtw89_phy_write32_mask(rtwdev, R_P1_RFCTM, R_P1_RFCTM_RDY, 0x0); in _tssi_set_tmeter_tbl()
3038 rtw89_phy_write32_mask(rtwdev, R_P0_TSSIC, B_P0_TSSIC_BYPASS, 0x0); in _tssi_set_tssi_track()
3040 rtw89_phy_write32_mask(rtwdev, R_P1_TSSIC, B_P1_TSSIC_BYPASS, 0x0); in _tssi_set_tssi_track()
3051 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_MV_AVG, B_P0_TSSI_MV_MIX, 0x010); in _tssi_set_txagc_offset_mv_avg()
3053 rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_MV_AVG, B_P1_RFCTM_DEL, 0x010); in _tssi_set_txagc_offset_mv_avg()
3060 for (i = 0; i < RF_PATH_NUM_8852B; i++) { in _tssi_enable()
3066 B_P0_TSSI_MV_CLR, 0x0); in _tssi_enable()
3068 B_P0_TSSI_EN, 0x0); in _tssi_enable()
3070 B_P0_TSSI_EN, 0x1); in _tssi_enable()
3072 RR_TXGA_V1_TRK_EN, 0x1); in _tssi_enable()
3074 B_P0_TSSI_RFC, 0x3); in _tssi_enable()
3077 B_P0_TSSI_OFT, 0xc0); in _tssi_enable()
3079 B_P0_TSSI_OFT_EN, 0x0); in _tssi_enable()
3081 B_P0_TSSI_OFT_EN, 0x1); in _tssi_enable()
3086 B_P1_TSSI_MV_CLR, 0x0); in _tssi_enable()
3088 B_P1_TSSI_EN, 0x0); in _tssi_enable()
3090 B_P1_TSSI_EN, 0x1); in _tssi_enable()
3092 RR_TXGA_V1_TRK_EN, 0x1); in _tssi_enable()
3094 B_P1_TSSI_RFC, 0x3); in _tssi_enable()
3097 B_P1_TSSI_OFT, 0xc0); in _tssi_enable()
3099 B_P1_TSSI_OFT_EN, 0x0); in _tssi_enable()
3101 B_P1_TSSI_OFT_EN, 0x1); in _tssi_enable()
3110 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_AVG, B_P0_TSSI_EN, 0x0); in _tssi_disable()
3111 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_RFC, 0x1); in _tssi_disable()
3112 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_MV_AVG, B_P0_TSSI_MV_CLR, 0x1); in _tssi_disable()
3113 rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_AVG, B_P1_TSSI_EN, 0x0); in _tssi_disable()
3114 rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_RFC, 0x1); in _tssi_disable()
3115 rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_MV_AVG, B_P1_TSSI_MV_CLR, 0x1); in _tssi_disable()
3125 return 0; in _tssi_get_cck_group()
3138 return 0; in _tssi_get_cck_group()
3151 return 0; in _tssi_get_ofdm_group()
3212 return 0; in _tssi_get_ofdm_group()
3219 return 0; in _tssi_get_trim_group()
3236 return 0; in _tssi_get_trim_group()
3252 "[TSSI][TRIM]: path=%d mcs group_idx=0x%x\n", path, gidx); in _tssi_get_ofdm_de()
3287 "[TSSI][TRIM]: path=%d mcs trim_group_idx=0x%x\n", in _tssi_get_ofdm_trim_de()
3331 "[TSSI][TRIM]: path=%d cck[%d]=0x%x trim=0x%x\n", in _tssi_set_efuse_to_de()
3338 "[TSSI] Set TSSI CCK DE 0x%x[21:12]=0x%x\n", in _tssi_set_efuse_to_de()
3348 "[TSSI][TRIM]: path=%d mcs=0x%x trim=0x%x\n", in _tssi_set_efuse_to_de()
3359 "[TSSI] Set TSSI MCS DE 0x%x[21:12]=0x%x\n", in _tssi_set_efuse_to_de()
3369 "[TSSI PA K]\n0x%x = 0x%08x\n0x%x = 0x%08x\n0x%x = 0x%08x\n0x%x = 0x%08x\n" in _tssi_alimentk_dump_result()
3370 "0x%x = 0x%08x\n0x%x = 0x%08x\n0x%x = 0x%08x\n0x%x = 0x%08x\n", in _tssi_alimentk_dump_result()
3413 tssi_info->alignment_value[path][band][0]); in _tssi_alimentk_done()
3456 for (i = 0; i < reg_num; i++) { in _tssi_backup_bb_registers()
3460 "[TSSI] Backup BB 0x%x = 0x%x\n", reg[i], in _tssi_backup_bb_registers()
3472 for (i = 0; i < reg_num; i++) { in _tssi_reload_bb_registers()
3476 "[TSSI] Reload BB 0x%x = 0x%x\n", reg[i], in _tssi_reload_bb_registers()
3494 channel_index = 0; in _tssi_ch_to_idx()
3508 for (j = 0; j < RTW8852B_TSSI_PATH_NR; j++) { in _tssi_get_cw_report()
3509 rtw89_phy_write32_mask(rtwdev, _tssi_trigger[path], B_P0_TSSI_EN, 0x0); in _tssi_get_cw_report()
3510 rtw89_phy_write32_mask(rtwdev, _tssi_trigger[path], B_P0_TSSI_EN, 0x1); in _tssi_get_cw_report()
3516 "[TSSI PA K] 0x%x = 0x%08x path=%d\n", in _tssi_get_cw_report()
3519 if (j == 0) in _tssi_get_cw_report()
3532 for (k = 0; k < retry; k++) { in _tssi_get_cw_report()
3577 static const u32 bb_reg[8] = {0x5820, 0x7820, 0x4978, 0x58e4, in _tssi_alimentk()
3578 0x78e4, 0x49c0, 0x0d18, 0x0d80}; in _tssi_alimentk()
3583 u32 tssi_cw_rpt[RTW8852B_TSSI_PATH_NR] = {0}; in _tssi_alimentk()
3589 u32 bb_reg_backup[8] = {0}; in _tssi_alimentk()
3602 tssi_info->alignment_backup_by_ch[path][ch_idx][0]); in _tssi_alimentk()
3637 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_AVG, B_P0_TSSI_AVG, 0x8); in _tssi_alimentk()
3638 rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_AVG, B_P1_TSSI_AVG, 0x8); in _tssi_alimentk()
3639 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_MV_AVG, B_P0_TSSI_MV_AVG, 0x2); in _tssi_alimentk()
3640 rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_MV_AVG, B_P1_TSSI_MV_AVG, 0x2); in _tssi_alimentk()
3646 for (j = 0; j < RTW8852B_TSSI_PATH_NR; j++) { in _tssi_alimentk()
3655 tssi_alim_offset_1 = tssi_cw_rpt[0] - ((power[0] - power[1]) * 2) - in _tssi_alimentk()
3678 "[TSSI PA K] tssi_alim_offset = 0x%x 0x%x 0x%x 0x%x\n", in _tssi_alimentk()
3692 "[TSSI PA K] tssi_alim_offset = 0x%x 0x%x 0x%x 0x%x\n", in _tssi_alimentk()
3700 tssi_info->alignment_value[path][band][0] = in _tssi_alimentk()
3710 tssi_info->alignment_backup_by_ch[path][ch_idx][0] = in _tssi_alimentk()
3720 "[TSSI PA K] tssi_info->alignment_value[path=%d][band=%d][0], 0x%x = 0x%08x\n", in _tssi_alimentk()
3722 tssi_info->alignment_value[path][band][0]); in _tssi_alimentk()
3724 "[TSSI PA K] tssi_info->alignment_value[path=%d][band=%d][1], 0x%x = 0x%08x\n", in _tssi_alimentk()
3728 "[TSSI PA K] tssi_info->alignment_value[path=%d][band=%d][2], 0x%x = 0x%08x\n", in _tssi_alimentk()
3732 "[TSSI PA K] tssi_info->alignment_value[path=%d][band=%d][3], 0x%x = 0x%08x\n", in _tssi_alimentk()
3739 rtw8852bx_bb_tx_mode_switch(rtwdev, phy, 0); in _tssi_alimentk()
3758 for (path = 0; path < RF_PATH_NUM_8852B; path++) in rtw8852b_rck()
3764 u8 phy_map = rtw89_btc_phymap(rtwdev, RTW89_PHY_0, 0, chanctx_idx); in rtw8852b_dack()
3774 u8 phy_map = rtw89_btc_phymap(rtwdev, phy_idx, 0, chanctx_idx); in rtw8852b_iqk()
3791 u8 phy_map = rtw89_btc_phymap(rtwdev, phy_idx, 0, chanctx_idx); in rtw8852b_rx_dck()
3807 u8 phy_map = rtw89_btc_phymap(rtwdev, phy_idx, 0, chanctx_idx); in rtw8852b_dpk()
3922 "======>%s 1 SCAN_END Set 0x5818[7:0]=0x%x 0x7818[7:0]=0x%x\n", in rtw8852b_tssi_default_txagc()
3927 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_OFT, 0xc0); in rtw8852b_tssi_default_txagc()
3928 rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_OFT, 0xc0); in rtw8852b_tssi_default_txagc()
3929 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_OFT_EN, 0x0); in rtw8852b_tssi_default_txagc()
3930 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_OFT_EN, 0x1); in rtw8852b_tssi_default_txagc()
3931 rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_OFT_EN, 0x0); in rtw8852b_tssi_default_txagc()
3932 rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_OFT_EN, 0x1); in rtw8852b_tssi_default_txagc()
3938 "======>%s 2 SCAN_END Set 0x5818[7:0]=0x%x 0x7818[7:0]=0x%x\n", in rtw8852b_tssi_default_txagc()
3994 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RFK] set %x at path%d, %x =0x%x\n", in _bw_setting()
4015 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LDO, RR_LDO_SEL, 0x1); in _set_s0_arfc18()
4018 ret = read_poll_timeout_atomic(rtw89_read_rf, tmp, tmp == 0, 1, 1000, in _set_s0_arfc18()
4032 if (rtw89_read_rf(rtwdev, RF_PATH_A, RR_SYNFB, RR_SYNFB_LK) == 0) { in _lck_check()
4035 rtw89_write_rf(rtwdev, RF_PATH_A, RR_MMD, RR_MMD_RST_EN, 0x1); in _lck_check()
4036 rtw89_write_rf(rtwdev, RF_PATH_A, RR_MMD, RR_MMD_RST_SYN, 0x0); in _lck_check()
4037 rtw89_write_rf(rtwdev, RF_PATH_A, RR_MMD, RR_MMD_RST_SYN, 0x1); in _lck_check()
4038 rtw89_write_rf(rtwdev, RF_PATH_A, RR_MMD, RR_MMD_RST_EN, 0x0); in _lck_check()
4043 if (rtw89_read_rf(rtwdev, RF_PATH_A, RR_SYNFB, RR_SYNFB_LK) == 0) { in _lck_check()
4044 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[LCK]re-set RF 0x18\n"); in _lck_check()
4046 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LCK_TRG, RR_LCK_TRGSEL, 0x1); in _lck_check()
4049 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LCK_TRG, RR_LCK_TRGSEL, 0x0); in _lck_check()
4052 if (rtw89_read_rf(rtwdev, RF_PATH_A, RR_SYNFB, RR_SYNFB_LK) == 0) { in _lck_check()
4060 rtw89_write_rf(rtwdev, RF_PATH_A, RR_SYNLUT, RR_SYNLUT_MOD, 0x1); in _lck_check()
4061 rtw89_write_rf(rtwdev, RF_PATH_A, RR_POW, RR_POW_SYN, 0x0); in _lck_check()
4062 rtw89_write_rf(rtwdev, RF_PATH_A, RR_POW, RR_POW_SYN, 0x3); in _lck_check()
4063 rtw89_write_rf(rtwdev, RF_PATH_A, RR_SYNLUT, RR_SYNLUT_MOD, 0x0); in _lck_check()
4065 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LCK_TRG, RR_LCK_TRGSEL, 0x1); in _lck_check()
4068 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LCK_TRG, RR_LCK_TRGSEL, 0x0); in _lck_check()
4070 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[LCK]0xb2=%x, 0xc5=%x\n", in _lck_check()
4112 rtw89_write_rf(rtwdev, path, RR_LCKST, RR_LCKST_BIN, 0); in _ch_setting()
4116 "[RFK]CH: %d for Path-%d, reg0x%x = 0x%x\n", in _ch_setting()
4132 rtw89_write_rf(rtwdev, path, RR_LUTWE2, RR_LUTWE2_RTXBW, 0x1); in _set_rxbb_bw()
4133 rtw89_write_rf(rtwdev, path, RR_LUTWA, RR_LUTWA_M2, 0x12); in _set_rxbb_bw()
4136 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RR_LUTWD0_LB, 0x1b); in _set_rxbb_bw()
4138 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RR_LUTWD0_LB, 0x13); in _set_rxbb_bw()
4140 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RR_LUTWD0_LB, 0xb); in _set_rxbb_bw()
4142 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RR_LUTWD0_LB, 0x3); in _set_rxbb_bw()
4144 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RFK] set S%d RXBB BW 0x3F = 0x%x\n", path, in _set_rxbb_bw()
4147 rtw89_write_rf(rtwdev, path, RR_LUTWE2, RR_LUTWE2_RTXBW, 0x0); in _set_rxbb_bw()
4157 for (path = 0; path < RF_PATH_NUM_8852B; path++) { in _rxbb_bw()