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/linux/arch/arm/boot/dts/vt8500/
H A Dwm8505.dtsi15 #size-cells = <0>;
17 cpu@0 {
20 reg = <0x0>;
43 reg = <0xd8140000 0x10000>;
52 reg = <0xD8150000 0x10000>;
58 reg = <0xd8110000 0x10000>;
67 reg = <0xd8120000 0x4>;
72 reg = <0xd8130000 0x1000>;
75 #size-cells = <0>;
78 #clock-cells = <0>;
[all …]
H A Dvt8500.dtsi15 #size-cells = <0>;
17 cpu@0 {
20 reg = <0x0>;
41 reg = <0xd8140000 0x10000>;
47 reg = <0xd8110000 0x10000>;
56 reg = <0xd8120000 0x4>;
61 reg = <0xd8130000 0x1000>;
65 #size-cells = <0>;
68 #clock-cells = <0>;
74 #clock-cells = <0>;
[all …]
H A Dwm8750.dtsi15 #size-cells = <0>;
17 cpu@0 {
20 reg = <0x0>;
45 reg = <0xd8140000 0x10000>;
54 reg = <0xD8150000 0x10000>;
60 reg = <0xd8110000 0x10000>;
69 reg = <0xd8120000 0x4>;
74 reg = <0xd8130000 0x1000>;
78 #size-cells = <0>;
81 #clock-cells = <0>;
[all …]
H A Dwm8650.dtsi15 #size-cells = <0>;
17 cpu@0 {
20 reg = <0x0>;
39 reg = <0xd8140000 0x10000>;
48 reg = <0xD8150000 0x10000>;
54 reg = <0xd8110000 0x10000>;
63 reg = <0xd8120000 0x4>;
68 reg = <0xd8130000 0x1000>;
72 #size-cells = <0>;
75 #clock-cells = <0>;
[all …]
H A Dwm8850.dtsi15 #size-cells = <0>;
17 cpu@0 {
20 reg = <0x0>;
42 reg = <0xd8140000 0x10000>;
51 reg = <0xD8150000 0x10000>;
57 reg = <0xd8110000 0x10000>;
66 reg = <0xd8120000 0x4>;
71 reg = <0xd8130000 0x1000>;
75 #size-cells = <0>;
78 #clock-cells = <0>;
[all …]
/linux/Documentation/sound/cards/
H A Dmultisound.sh77 # 0x250, 0x260 or 0x270. This port can be disabled to have the card
96 # to obtain one with the command `pnpdump 1 0x203' -- this may vary
107 # io base 0x210, irq 5 and mem 0xd8000, and also sets the Kurzweil
108 # synth to 0x330 and irq 9 (may need editing for your system):
110 # (READPORT 0x0203)
115 # (CONFIGURE BVJ0440/-1 (LD 0
116 # (INT 0 (IRQ 5 (MODE +E))) (IO 0 (BASE 0x0210)) (MEM 0 (BASE 0x0d8000))
121 # (IO 0 (BASE 0x0330)) (INT 0 (IRQ 9 (MODE +E)))
140 # If you specify cfg=0x250 for the snd-msnd-pinnacle module, it
143 # on the card to 0x250, 0x260 or 0x270).
[all …]
/linux/drivers/pmdomain/sunxi/
H A Dsun50i-h6-prcm-ppu.c29 #define PD_H6_PPU_OFFSET 0x250
30 #define PD_H6_VDD_SYS_REG 0x250
34 #define PD_H6_GPU_REG 0x254
35 #define PD_H6_GPU_GATE BIT(0)
44 #define FLAG_PPU_ALWAYS_ON BIT(0)
101 return 0; in sun50i_h6_ppu_pd_set_power()
147 base = devm_platform_ioremap_resource(pdev, 0); in sun50i_h6_ppu_probe()
151 for (i = 0; i < data->nr_domains; i++) { in sun50i_h6_ppu_probe()
176 return 0; in sun50i_h6_ppu_probe()
180 for (i--; i >= 0; i--) in sun50i_h6_ppu_probe()
/linux/drivers/clk/mediatek/
H A Dclk-mt8196-apmixedsys.c21 #define MAINPLL_CON0 0x250
22 #define MAINPLL_CON1 0x254
23 #define UNIVPLL_CON0 0x264
24 #define UNIVPLL_CON1 0x268
25 #define MSDCPLL_CON0 0x278
26 #define MSDCPLL_CON1 0x27c
27 #define ADSPPLL_CON0 0x28c
28 #define ADSPPLL_CON1 0x290
29 #define EMIPLL_CON0 0x2a0
30 #define EMIPLL_CON1 0x2a4
[all …]
H A Dclk-mt6795-apmixedsys.c15 #define REG_REF2USB 0x8
16 #define REG_AP_PLL_CON7 0x1c
17 #define MD1_MTCMOS_OFF BIT(0)
23 #define MT6795_CON0_EN BIT(0)
43 .pll_en_bit = 0, \
47 PLL(CLK_APMIXED_ARMCA53PLL, "armca53pll", 0x200, 0x20c, 0, PLL_AO,
48 21, 0x204, 24, 0x0, 0x204, 0),
49 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x220, 0x22c, 0xf0000101, HAVE_RST_BAR,
50 21, 0x220, 4, 0x0, 0x224, 0),
51 PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x230, 0x23c, 0xfe000101, HAVE_RST_BAR,
[all …]
H A Dclk-mt8173-apmixedsys.c17 #define REGOFF_REF2USB 0x8
18 #define REGOFF_HDMI_REF 0x40
52 { .div = 0, .freq = MT8173_PLL_FMAX },
61 PLL(CLK_APMIXED_ARMCA15PLL, "armca15pll", 0x200, 0x20c, 0, PLL_AO,
62 21, 0x204, 24, 0x0, 0x204, 0),
63 PLL(CLK_APMIXED_ARMCA7PLL, "armca7pll", 0x210, 0x21c, 0, PLL_AO,
64 21, 0x214, 24, 0x0, 0x214, 0),
65 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x220, 0x22c, 0xf0000100, HAVE_RST_BAR, 21,
66 0x220, 4, 0x0, 0x224, 0),
67 PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x230, 0x23c, 0xfe000000, HAVE_RST_BAR, 7,
[all …]
/linux/Documentation/locking/
H A Dlockstat.rst56 - shortest (non-0) time we ever had to wait for a lock
69 - shortest (non-0) time we ever held the lock
97 # echo 0 >/proc/sys/kernel/lock_stat
114 … &mm->mmap_sem 1 [<ffffffff811502a7>] khugepaged_scan_mm_slot+0x57/0x280
115 … &mm->mmap_sem 96 [<ffffffff815351c4>] __do_page_fault+0x1d4/0x510
116 … &mm->mmap_sem 34 [<ffffffff81113d77>] vm_mmap_pgoff+0x87/0xd0
117 … &mm->mmap_sem 17 [<ffffffff81127e71>] vm_munmap+0x41/0x80
119 … &mm->mmap_sem 1 [<ffffffff81046fda>] dup_mmap+0x2a/0x3f0
120 … &mm->mmap_sem 60 [<ffffffff81129e29>] SyS_mprotect+0xe9/0x250
121 … &mm->mmap_sem 41 [<ffffffff815351c4>] __do_page_fault+0x1d4/0x510
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mq-pinfunc.h15 #define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0…
16 #define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0…
17 #define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0…
18 #define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0…
19 #define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0…
20 #define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
21 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
22 #define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
23 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
24 #define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
[all …]
H A Dimx8mm-pinfunc.h14 #define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
15 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
16 #define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
17 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
18 #define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
19 #define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0…
20 #define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0…
21 #define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0…
22 #define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0…
23 #define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0…
[all …]
H A Dimx8mn-pinfunc.h14 …ne MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x020 0x25C 0x000 0x0 0x0
15 …ne MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x020 0x25C 0x55C 0x1 0x3
16 …ne MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x024 0x260 0x000 0x0 0x0
17 …ne MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x024 0x260 0x56C 0x1 0x3
18 …ne MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0
19 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x000 0x1 0x0
20 …ne MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0
21 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0
22 …ne MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0
23 …ne MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0
[all …]
/linux/Documentation/translations/it_IT/locking/
H A Dlockstat.rst118 # echo 0 >/proc/sys/kernel/lock_stat
135 … &mm->mmap_sem 1 [<ffffffff811502a7>] khugepaged_scan_mm_slot+0x57/0x280
136 … &mm->mmap_sem 96 [<ffffffff815351c4>] __do_page_fault+0x1d4/0x510
137 … &mm->mmap_sem 34 [<ffffffff81113d77>] vm_mmap_pgoff+0x87/0xd0
138 … &mm->mmap_sem 17 [<ffffffff81127e71>] vm_munmap+0x41/0x80
140 … &mm->mmap_sem 1 [<ffffffff81046fda>] dup_mmap+0x2a/0x3f0
141 … &mm->mmap_sem 60 [<ffffffff81129e29>] SyS_mprotect+0xe9/0x250
142 … &mm->mmap_sem 41 [<ffffffff815351c4>] __do_page_fault+0x1d4/0x510
143 … &mm->mmap_sem 68 [<ffffffff81113d77>] vm_mmap_pgoff+0x87/0xd0
149 … unix_table_lock 45 [<ffffffff8150ad8e>] unix_create1+0x16e/0x1b0
[all …]
/linux/sound/isa/gus/
H A Dgusclassic.c27 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
30 static long port[SNDRV_CARDS] = SNDRV_DEFAULT_PORT; /* 0x220,0x230,0x240,0x250,0x260 */
34 static int joystick_dac[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 29};
35 /* 0 to 31, (0.59V-4.52V or 0.389V-2.98V) */
36 static int channels[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 24};
37 static int pcm_channels[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 2};
69 static const long possible_ports[] = {0x220, 0x230, 0x240, 0x250, 0x260}; in snd_gusclassic_create()
77 if (irq[n] < 0) { in snd_gusclassic_create()
84 if (dma1[n] < 0) { in snd_gusclassic_create()
91 if (dma2[n] < 0) { in snd_gusclassic_create()
[all …]
/linux/drivers/net/ethernet/sunplus/
H A Dspl2sw_register.h10 #define L2SW_SW_INT_STATUS_0 0x0
11 #define L2SW_SW_INT_MASK_0 0x4
12 #define L2SW_FL_CNTL_TH 0x8
13 #define L2SW_CPU_FL_CNTL_TH 0xc
14 #define L2SW_PRI_FL_CNTL 0x10
15 #define L2SW_VLAN_PRI_TH 0x14
16 #define L2SW_EN_TOS_BUS 0x18
17 #define L2SW_TOS_MAP0 0x1c
18 #define L2SW_TOS_MAP1 0x20
19 #define L2SW_TOS_MAP2 0x24
[all …]
/linux/include/soc/tegra/
H A Dfuse.h11 #define TEGRA20 0x20
12 #define TEGRA30 0x30
13 #define TEGRA114 0x35
14 #define TEGRA124 0x40
15 #define TEGRA132 0x13
16 #define TEGRA210 0x21
17 #define TEGRA186 0x18
18 #define TEGRA194 0x19
19 #define TEGRA234 0x23
20 #define TEGRA241 0x24
[all …]
/linux/arch/arc/include/asm/
H A Dperf_event.h15 #define ARC_REG_CC_BUILD 0xF6
16 #define ARC_REG_CC_INDEX 0x240
17 #define ARC_REG_CC_NAME0 0x241
18 #define ARC_REG_CC_NAME1 0x242
20 #define ARC_REG_PCT_BUILD 0xF5
21 #define ARC_REG_PCT_COUNTL 0x250
22 #define ARC_REG_PCT_COUNTH 0x251
23 #define ARC_REG_PCT_SNAPL 0x252
24 #define ARC_REG_PCT_SNAPH 0x253
25 #define ARC_REG_PCT_CONFIG 0x254
[all …]
/linux/drivers/media/platform/mediatek/mdp3/
H A Dmdp_reg_rdma.h10 #define MDP_RDMA_EN 0x000
11 #define MDP_RDMA_RESET 0x008
12 #define MDP_RDMA_CON 0x020
13 #define MDP_RDMA_GMCIF_CON 0x028
14 #define MDP_RDMA_SRC_CON 0x030
15 #define MDP_RDMA_MF_BKGD_SIZE_IN_BYTE 0x060
16 #define MDP_RDMA_MF_BKGD_SIZE_IN_PXL 0x068
17 #define MDP_RDMA_MF_SRC_SIZE 0x070
18 #define MDP_RDMA_MF_CLIP_SIZE 0x078
19 #define MDP_RDMA_MF_OFFSET_1 0x080
[all …]
/linux/arch/arm/boot/dts/ti/keystone/
H A Dkeystone-k2hk.dtsi16 #size-cells = <0>;
20 cpu@0 {
23 reg = <0>;
62 reg = <0x0c000000 0x600000>;
63 ranges = <0x0 0x0c000000 0x600000>;
68 reg = <0x5f0000 0x8000>;
78 0xa3c 8 0xa3c 8 0x83c 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 0: dsp0 */
79 0xa40 8 0xa40 8 0x840 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 1: dsp1 */
80 0xa44 8 0xa44 8 0x844 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 2: dsp2 */
81 0xa48 8 0xa48 8 0x848 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 3: dsp3 */
[all …]
/linux/drivers/ufs/host/
H A Dufs-rockchip.h11 #define SEL_TX_LANE0 0x0
12 #define SEL_TX_LANE1 0x1
13 #define SEL_TX_LANE2 0x2
14 #define SEL_TX_LANE3 0x3
15 #define SEL_RX_LANE0 0x4
16 #define SEL_RX_LANE1 0x5
17 #define SEL_RX_LANE2 0x6
18 #define SEL_RX_LANE3 0x7
20 #define VND_TX_CLK_PRD 0xAA
21 #define VND_TX_CLK_PRD_EN 0xA9
[all …]
/linux/drivers/clk/renesas/
H A Dr8a77995-cpg-mssr.c109 DEF_GEN3_SDH("sd0h", R8A77995_CLK_SD0H, CLK_SDSRC, 0x268),
110 DEF_GEN3_SD("sd0", R8A77995_CLK_SD0, R8A77995_CLK_SD0H, 0x268),
115 DEF_DIV6P1("canfd", R8A77995_CLK_CANFD, CLK_PLL0D3, 0x244),
116 DEF_DIV6P1("mso", R8A77995_CLK_MSO, CLK_PLL1D2, 0x014),
213 * 0 48 x 1 x250/4 x100/3 x100/3
214 * 1 48 x 1 x250/4 x100/3 x58/3
236 return rcar_gen3_cpg_init(cpg_pll_config, 0, cpg_mode); in r8a77995_cpg_mssr_init()
/linux/include/linux/bcma/
H A Dbcma_driver_gmac_cmn.h7 #define BCMA_GMAC_CMN_STAG0 0x000
8 #define BCMA_GMAC_CMN_STAG1 0x004
9 #define BCMA_GMAC_CMN_STAG2 0x008
10 #define BCMA_GMAC_CMN_STAG3 0x00C
11 #define BCMA_GMAC_CMN_PARSER_CTL 0x020
12 #define BCMA_GMAC_CMN_MIB_MAX_LEN 0x024
13 #define BCMA_GMAC_CMN_PHY_ACCESS 0x100
14 #define BCMA_GMAC_CMN_PA_DATA_MASK 0x0000ffff
15 #define BCMA_GMAC_CMN_PA_ADDR_MASK 0x001f0000
17 #define BCMA_GMAC_CMN_PA_REG_MASK 0x1f000000
[all …]
/linux/arch/arm64/boot/dts/broadcom/stingray/
H A Dstingray-pinctrl.dtsi37 reg = <0x00140000 0x250>;
45 reg = <0x0014029c 0x26c>;
47 #size-cells = <0>;
49 pinctrl-single,function-mask = <0xf>;
51 &range 0 91 MODE_GPIO
61 0x038 MODE_NITRO /* tsio_0 */
62 0x03c MODE_NITRO /* tsio_1 */
68 0x0ac MODE_PNOR /* nand_ce1_n */
69 0x0b0 MODE_PNOR /* nand_ce0_n */
70 0x0b4 MODE_PNOR /* nand_we_n */
[all …]

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