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/linux/include/sound/
H A Dgus.h21 #define SNDRV_g_u_s_MIDICTRL (0x320-0x220)
22 #define SNDRV_g_u_s_MIDISTAT (0x320-0x220)
23 #define SNDRV_g_u_s_MIDIDATA (0x321-0x220)
25 #define SNDRV_g_u_s_GF1PAGE (0x32
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/linux/include/dt-bindings/clock/
H A Dam4.h8 #define AM4_CLKCTRL_OFFSET 0x20
12 #define AM4_L3S_TSC_CLKCTRL_OFFSET 0x120
14 #define AM4_L3S_TSC_ADC_TSC_CLKCTRL AM4_L3S_TSC_CLKCTRL_INDEX(0x120)
17 #define AM4_L4_WKUP_AON_CLKCTRL_OFFSET 0x228
19 #define AM4_L4_WKUP_AON_WKUP_M3_CLKCTRL AM4_L4_WKUP_AON_CLKCTRL_INDEX(0x228)
20 #define AM4_L4_WKUP_AON_COUNTER_32K_CLKCTRL AM4_L4_WKUP_AON_CLKCTRL_INDEX(0x230)
23 #define AM4_L4_WKUP_CLKCTRL_OFFSET 0x220
25 #define AM4_L4_WKUP_L4_WKUP_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x220)
26 #define AM4_L4_WKUP_TIMER1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x328)
27 #define AM4_L4_WKUP_WD_TIMER2_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x338)
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H A Ddm814.h8 #define DM814_CLKCTRL_OFFSET 0x0
12 #define DM814_USB_OTG_HS_CLKCTRL DM814_CLKCTRL_INDEX(0x58)
15 #define DM814_UART1_CLKCTRL DM814_CLKCTRL_INDEX(0x150)
16 #define DM814_UART2_CLKCTRL DM814_CLKCTRL_INDEX(0x154)
17 #define DM814_UART3_CLKCTRL DM814_CLKCTRL_INDEX(0x158)
18 #define DM814_GPIO1_CLKCTRL DM814_CLKCTRL_INDEX(0x15c)
19 #define DM814_GPIO2_CLKCTRL DM814_CLKCTRL_INDEX(0x160)
20 #define DM814_I2C1_CLKCTRL DM814_CLKCTRL_INDEX(0x164)
21 #define DM814_I2C2_CLKCTRL DM814_CLKCTRL_INDEX(0x168)
22 #define DM814_WD_TIMER_CLKCTRL DM814_CLKCTRL_INDEX(0x18c)
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H A Dlpc18xx-ccu.h13 #define CLK_APB3_BUS 0x100
14 #define CLK_APB3_I2C1 0x108
15 #define CLK_APB3_DAC 0x110
16 #define CLK_APB3_ADC0 0x118
17 #define CLK_APB3_ADC1 0x120
18 #define CLK_APB3_CAN0 0x128
19 #define CLK_APB1_BUS 0x200
20 #define CLK_APB1_MOTOCON_PWM 0x208
21 #define CLK_APB1_I2C0 0x210
22 #define CLK_APB1_I2S 0x218
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/linux/sound/isa/gus/
H A Dgusextreme.c31 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
34 static long port[SNDRV_CARDS] = SNDRV_DEFAULT_PORT; /* 0x220,0x240,0x260 */
35 static long gf1_port[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS) - 1] = -1}; /* 0x210,0x220,0x23
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H A Dgusclassic.c27 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
30 static long port[SNDRV_CARDS] = SNDRV_DEFAULT_PORT; /* 0x220,0x230,0x240,0x250,0x260 */
34 static int joystick_dac[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 29};
35 /* 0 to 31, (0.59V-4.52V or 0.389V-2.98V) */
36 static int channels[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 24};
37 static int pcm_channels[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 2};
69 static const long possible_ports[] = {0x220, 0x230, 0x240, 0x250, 0x260}; in snd_gusclassic_create()
77 if (irq[n] < 0) { in snd_gusclassic_create()
84 if (dma1[n] < 0) { in snd_gusclassic_create()
91 if (dma2[n] < 0) { in snd_gusclassic_create()
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H A Dgusmax.c25 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
28 static long port[SNDRV_CARDS] = SNDRV_DEFAULT_PORT; /* 0x220,0x230,0x240,0x250,0x260 */
32 static int joystick_dac[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 29};
33 /* 0 to 31, (0.59V-4.52V or 0.389V-2.98V) */
34 static int channels[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 24};
35 static int pcm_channels[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 2};
71 snd_gf1_i_write8(gus, SNDRV_GF1_GB_RESET, 0); /* reset GF1 */ in snd_gusmax_detect()
73 if ((d & 0x07) != 0) { in snd_gusmax_detect()
74 dev_dbg(gus->card->dev, "[0x%lx] check 1 failed - 0x%x\n", gus->gf1.port, d); in snd_gusmax_detect()
81 if ((d & 0x07) != 1) { in snd_gusmax_detect()
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/linux/Documentation/sound/
H A Dalsa-configuration.rst57 (0 = disable debug prints, 1 = normal debug messages,
71 Default: 0
80 the card #0. Similarly, when ``adsp_map=0``, /dev/adsp will be mapped
81 to PCM #0 of the card #0.
83 commas, such like ``dsp_map=0,1``.
98 Default: 0
119 Values: 0 through 31 or negative;
142 appearing card. They can do it by specifying "index=1,0" module
158 the port must be specified. For actual AdLib FM cards it will be 0x388.
170 64:0 OPL2 FM synth OPL2 FM Port
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/linux/drivers/clk/mediatek/
H A Dclk-mt6795-apmixedsys.c15 #define REG_REF2USB 0x8
16 #define REG_AP_PLL_CON7 0x1c
17 #define MD1_MTCMOS_OFF BIT(0)
23 #define MT6795_CON0_EN BIT(0)
43 .pll_en_bit = 0, \
47 PLL(CLK_APMIXED_ARMCA53PLL, "armca53pll", 0x200, 0x20c, 0, PLL_AO,
48 21, 0x204, 24, 0x0, 0x204, 0),
49 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x220, 0x22c, 0xf0000101, HAVE_RST_BAR,
50 21, 0x220, 4, 0x0, 0x224, 0),
51 PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x230, 0x23c, 0xfe000101, HAVE_RST_BAR,
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H A Dclk-mt8173-apmixedsys.c17 #define REGOFF_REF2USB 0x8
18 #define REGOFF_HDMI_REF 0x40
52 { .div = 0, .freq = MT8173_PLL_FMAX },
61 PLL(CLK_APMIXED_ARMCA15PLL, "armca15pll", 0x200, 0x20c, 0, PLL_AO,
62 21, 0x204, 24, 0x0, 0x204, 0),
63 PLL(CLK_APMIXED_ARMCA7PLL, "armca7pll", 0x210, 0x21c, 0, PLL_AO,
64 21, 0x214, 24, 0x0, 0x214, 0),
65 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x220, 0x22c, 0xf0000100, HAVE_RST_BAR, 21,
66 0x220, 4, 0x0, 0x224, 0),
67 PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x230, 0x23c, 0xfe000000, HAVE_RST_BAR, 7,
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/linux/sound/isa/sb/
H A Dsb8.c22 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
25 static long port[SNDRV_CARDS] = SNDRV_DEFAULT_PORT; /* 0x220,0x240,0x260 */
61 return 0; in snd_sb8_match()
64 return 0; in snd_sb8_match()
68 return 0; in snd_sb8_match()
83 if (err < 0) in snd_sb8_probe()
88 * Block the 0x388 port to avoid PnP conflicts. in snd_sb8_probe()
92 acard->fm_res = devm_request_region(card->dev, 0x388, 4, in snd_sb8_probe()
99 if (err < 0) in snd_sb8_probe()
104 0x220, 0x240, 0x260, in snd_sb8_probe()
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/linux/arch/powerpc/include/asm/
H A Dtsi108_pci.h12 #define TSI108_PCI_P2O_BAR0 (TSI108_PCI_OFFSET + 0x10)
13 #define TSI108_PCI_P2O_BAR0_UPPER (TSI108_PCI_OFFSET + 0x14)
14 #define TSI108_PCI_P2O_BAR2 (TSI108_PCI_OFFSET + 0x18)
15 #define TSI108_PCI_P2O_BAR2_UPPER (TSI108_PCI_OFFSET + 0x1c)
16 #define TSI108_PCI_P2O_PAGE_SIZES (TSI108_PCI_OFFSET + 0x4c)
17 #define TSI108_PCI_PFAB_BAR0 (TSI108_PCI_OFFSET + 0x204)
18 #define TSI108_PCI_PFAB_BAR0_UPPER (TSI108_PCI_OFFSET + 0x208)
19 #define TSI108_PCI_PFAB_IO (TSI108_PCI_OFFSET + 0x20c)
20 #define TSI108_PCI_PFAB_IO_UPPER (TSI108_PCI_OFFSET + 0x210)
21 #define TSI108_PCI_PFAB_MEM32 (TSI108_PCI_OFFSET + 0x214)
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/linux/drivers/phy/qualcomm/
H A Dphy-qcom-qmp-qserdes-txrx-v6_20.h9 #define QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_TX 0x30
10 #define QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_RX 0x34
11 #define QSERDES_V6_20_TX_TRAN_DRVR_EMP_EN 0xac
12 #define QSERDES_V6_20_TX_LANE_MODE_1 0x78
13 #define QSERDES_V6_20_TX_LANE_MODE_2 0x7c
14 #define QSERDES_V6_20_TX_LANE_MODE_3 0x80
16 #define QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2 0x08
17 #define QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3 0x0c
18 #define QSERDES_V6_20_RX_UCDR_SO_GAIN_RATE_2 0x18
19 #define QSERDES_V6_20_RX_UCDR_PI_CONTROLS 0x20
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H A Dphy-qcom-qmp-qserdes-txrx-v5_20.h10 #define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX 0x30
11 #define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX 0x34
12 #define QSERDES_V5_20_TX_LANE_MODE_1 0x78
13 #define QSERDES_V5_20_TX_LANE_MODE_2 0x7c
14 #define QSERDES_V5_20_TX_LANE_MODE_3 0x80
15 #define QSERDES_V5_20_TX_RCV_DETECT_LVL_2 0x90
16 #define QSERDES_V5_20_TX_VMODE_CTRL1 0xb0
17 #define QSERDES_V5_20_TX_PI_QEC_CTRL 0xcc
20 #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2 0x008
21 #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3 0x00c
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/linux/drivers/net/ethernet/marvell/octeontx2/nic/
H A Dotx2_reg.h14 #define RVU_PF_VFX_PFVF_MBOX0 (0x00000)
15 #define RVU_PF_VFX_PFVF_MBOX1 (0x00008)
16 #define RVU_PF_VFX_PFVF_MBOXX(a, b) (0x0 | (a) << 12 | (b) << 3)
17 #define RVU_PF_VF_BAR4_ADDR (0x10)
18 #define RVU_PF_BLOCK_ADDRX_DISC(a) (0x200 | (a) << 3)
19 #define RVU_PF_VFME_STATUSX(a) (0x800 | (a) << 3)
20 #define RVU_PF_VFTRPENDX(a) (0x820 | (a) << 3)
21 #define RVU_PF_VFTRPEND_W1SX(a) (0x840 | (a) << 3)
22 #define RVU_PF_VFPF_MBOX_INTX(a) (0x880 | (a) << 3)
23 #define RVU_PF_VFPF_MBOX_INT_W1SX(a) (0x8A0 | (a) << 3)
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/linux/arch/xtensa/include/asm/
H A Dmxregs.h20 * 00nn 0...0p..p Interrupt Routing, route IRQ n to processor p
21 * 01pp 0...0d..d 16 bits (d) 'ored' as single IPI to processor p
22 * 0180 0...0m..m Clear enable specified by mask (m)
23 * 0184 0...0m..m Set enable specified by mask (m)
24 * 0190 0...0x..x 8-bit IPI partition register
30 * 0200 0...0m..m RunStall core 'n'
34 #define MIROUT(irq) (0x000 + (irq))
35 #define MIPICAUSE(cpu) (0x100 + (cpu))
36 #define MIPISET(cause) (0x140 + (cause))
37 #define MIENG 0x180
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/linux/drivers/net/ethernet/sunplus/
H A Dspl2sw_register.h10 #define L2SW_SW_INT_STATUS_0 0x0
11 #define L2SW_SW_INT_MASK_0 0x4
12 #define L2SW_FL_CNTL_TH 0x8
13 #define L2SW_CPU_FL_CNTL_TH 0xc
14 #define L2SW_PRI_FL_CNTL 0x10
15 #define L2SW_VLAN_PRI_TH 0x14
16 #define L2SW_EN_TOS_BUS 0x18
17 #define L2SW_TOS_MAP0 0x1c
18 #define L2SW_TOS_MAP1 0x20
19 #define L2SW_TOS_MAP2 0x24
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/linux/arch/alpha/kernel/
H A Des1888.c16 inb(0x0229); in es1888_init()
17 inb(0x0229); in es1888_init()
18 inb(0x0229); in es1888_init()
19 inb(0x022b); in es1888_init()
20 inb(0x0229); in es1888_init()
21 inb(0x022b); in es1888_init()
22 inb(0x0229); in es1888_init()
23 inb(0x0229); in es1888_init()
24 inb(0x022b); in es1888_init()
25 inb(0x0229); in es1888_init()
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/linux/drivers/ufs/host/
H A Dufs-rockchip.h11 #define SEL_TX_LANE0 0x0
12 #define SEL_TX_LANE1 0x1
13 #define SEL_TX_LANE2 0x2
14 #define SEL_TX_LANE3 0x3
15 #define SEL_RX_LANE0 0x4
16 #define SEL_RX_LANE1 0x5
17 #define SEL_RX_LANE2 0x6
18 #define SEL_RX_LANE3 0x7
20 #define VND_TX_CLK_PRD 0xAA
21 #define VND_TX_CLK_PRD_EN 0xA9
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/linux/include/linux/bcma/
H A Dbcma_driver_gmac_cmn.h7 #define BCMA_GMAC_CMN_STAG0 0x000
8 #define BCMA_GMAC_CMN_STAG1 0x004
9 #define BCMA_GMAC_CMN_STAG2 0x008
10 #define BCMA_GMAC_CMN_STAG3 0x00C
11 #define BCMA_GMAC_CMN_PARSER_CTL 0x020
12 #define BCMA_GMAC_CMN_MIB_MAX_LEN 0x024
13 #define BCMA_GMAC_CMN_PHY_ACCESS 0x100
14 #define BCMA_GMAC_CMN_PA_DATA_MASK 0x0000ffff
15 #define BCMA_GMAC_CMN_PA_ADDR_MASK 0x001f0000
17 #define BCMA_GMAC_CMN_PA_REG_MASK 0x1f000000
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/linux/sound/isa/es1688/
H A Des1688.c31 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
37 static long port[SNDRV_CARDS] = SNDRV_DEFAULT_PORT; /* 0x220,0x240,0x260 */
38 static long fm_port[SNDRV_CARDS] = SNDRV_DEFAULT_PORT; /* Usually 0x388 */
39 static long mpu_port[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = -1};
42 static int dma8[SNDRV_CARDS] = SNDRV_DEFAULT_DMA; /* 0,1,3 */
70 #define is_isapnp_selected(dev) 0
82 static const long possible_ports[] = {0x220, 0x240, 0x260}; in snd_es1688_legacy_create()
84 static const int possible_dmas[] = {1, 3, 0, -1}; in snd_es1688_legacy_create()
90 if (irq[n] < 0) { in snd_es1688_legacy_create()
97 if (dma8[n] < 0) { in snd_es1688_legacy_create()
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/linux/drivers/pinctrl/
H A Dpinctrl-pic32.h12 #define ANSEL_REG 0x00
13 #define TRIS_REG 0x10
14 #define PORT_REG 0x20
15 #define LAT_REG 0x30
16 #define ODCU_REG 0x40
17 #define CNPU_REG 0x50
18 #define CNPD_REG 0x60
19 #define CNCON_REG 0x70
20 #define CNEN_REG 0x80
21 #define CNSTAT_REG 0x90
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/linux/sound/soc/fsl/
H A Dfsl_audmix.h15 #define FSL_AUDMIX_CTR 0x200 /* Control */
16 #define FSL_AUDMIX_STR 0x204 /* Status */
18 #define FSL_AUDMIX_ATCR0 0x208 /* Attenuation Control */
19 #define FSL_AUDMIX_ATIVAL0 0x20c /* Attenuation Initial Value */
20 #define FSL_AUDMIX_ATSTPUP0 0x210 /* Attenuation step up factor */
21 #define FSL_AUDMIX_ATSTPDN0 0x214 /* Attenuation step down factor */
22 #define FSL_AUDMIX_ATSTPTGT0 0x218 /* Attenuation step target */
23 #define FSL_AUDMIX_ATTNVAL0 0x21c /* Attenuation Value */
24 #define FSL_AUDMIX_ATSTP0 0x220 /* Attenuation step number */
26 #define FSL_AUDMIX_ATCR1 0x228 /* Attenuation Control */
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/linux/drivers/reset/
H A Dreset-aspeed.c16 #define SCU0_RESET_CTRL1 0x200
17 #define SCU0_RESET_CTRL2 0x220
18 #define SCU1_RESET_CTRL1 0x200
19 #define SCU1_RESET_CTRL2 0x220
20 #define SCU1_PCIE3_CTRL 0x908
40 [SCU0_RESET_SDRAM] = { true, SCU0_RESET_CTRL1, BIT(0) },
72 [SCU0_RESET_PORTA_VHUB] = { true, SCU0_RESET_CTRL2, BIT(0) },
88 [SCU1_RESET_LPC0] = { true, SCU1_RESET_CTRL1, BIT(0) },
120 [SCU1_RESET_MCU0] = { true, SCU1_RESET_CTRL2, BIT(0) },
151 [SCU1_RESET_PCIE2RST] = { false, SCU1_PCIE3_CTRL, BIT(0) },
[all …]
/linux/sound/isa/
H A Dsc6000.c33 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
36 static long port[SNDRV_CARDS] = SNDRV_DEFAULT_PORT; /* 0x220, 0x240 */
38 static long mss_port[SNDRV_CARDS] = SNDRV_DEFAULT_PORT; /* 0x530, 0xe80 */
40 /* 0x300, 0x310, 0x320, 0x330 */
41 static int mpu_irq[SNDRV_CARDS] = SNDRV_DEFAULT_IRQ; /* 5, 7, 9, 10, 0 */
42 static int dma[SNDRV_CARDS] = SNDRV_DEFAULT_DMA; /* 0, 1, 3 */
43 static bool joystick[SNDRV_CARDS] = { [0 ... (SNDRV_CARDS-1)] = false };
70 #define WRITE_MDIRQ_CFG 0x50 /* Set M&I&DRQ mask (the real config) */
71 #define COMMAND_52 0x52 /* */
72 #define READ_HARD_CFG 0x58 /* Read Hardware Config (I/O base etc) */
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