Lines Matching +full:0 +full:x220
16 #define SCU0_RESET_CTRL1 0x200
17 #define SCU0_RESET_CTRL2 0x220
18 #define SCU1_RESET_CTRL1 0x200
19 #define SCU1_RESET_CTRL2 0x220
20 #define SCU1_PCIE3_CTRL 0x908
40 [SCU0_RESET_SDRAM] = { true, SCU0_RESET_CTRL1, BIT(0) },
72 [SCU0_RESET_PORTA_VHUB] = { true, SCU0_RESET_CTRL2, BIT(0) },
88 [SCU1_RESET_LPC0] = { true, SCU1_RESET_CTRL1, BIT(0) },
120 [SCU1_RESET_MCU0] = { true, SCU1_RESET_CTRL2, BIT(0) },
151 [SCU1_RESET_PCIE2RST] = { false, SCU1_PCIE3_CTRL, BIT(0) },
171 return 0; in aspeed_reset_assert()
180 writel(rc->info->signal[id].bit, reg_offset + 0x04); in aspeed_reset_deassert()
186 return 0; in aspeed_reset_deassert()
194 return (readl(reg_offset) & rc->info->signal[id].bit) ? 1 : 0; in aspeed_reset_status()