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/freebsd/sys/contrib/device-tree/Bindings/arm/marvell/
H A Dmvebu-cpu-config.txt19 reg = <0x21000 0x8>;
/freebsd/sys/contrib/device-tree/src/powerpc/fsl/
H A Dpq3-dma-0.dtsi2 * PQ3 DMA device tree stub [ controller @ offset 0x21000 ]
39 reg = <0x21300 0x4>;
40 ranges = <0x0 0x21100 0x200>;
41 cell-index = <0>;
42 dma-channel@0 {
44 reg = <0x0 0x80>;
45 cell-index = <0>;
46 interrupts = <20 2 0 0>;
50 reg = <0x80 0x80>;
52 interrupts = <21 2 0 0>;
[all …]
/freebsd/sys/contrib/device-tree/src/arc/
H A Dvdk_axs10x_mb.dtsi13 ranges = <0x00000000 0xe0000000 0x10000000>;
20 #clock-cells = <0>;
26 #clock-cells = <0>;
30 #clock-cells = <0>;
39 reg = < 0x18000 0x2000 >;
43 snps,phy-addr = < 0 >; // VDK model phy address is 0
51 reg = < 0x40000 0x100 >;
57 reg = <0x20000 0x100>;
67 reg = <0x21000 0x100>;
77 reg = <0x22000 0x100>;
[all …]
H A Daxs10x_mb.dtsi17 ranges = <0x00000000 0x0 0xe0000000 0x10000000>;
23 reg = <0x11220 0x4>;
28 reg = <0x100a0 0x10>;
30 #clock-cells = <0>;
37 #clock-cells = <0>;
43 #clock-cells = <0>;
49 #clock-cells = <0>;
62 #clock-cells = <0>;
68 reg = <0x10080 0x10>, <0x110 0x10>;
69 #clock-cells = <0>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/dma/
H A Dfsl,eloplus-dma.yaml41 controller index. 0 for controller @ 0x21000, 1 for controller @ 0xc000
56 "^dma-channel@[0-9a-f]+$":
81 description: DMA channel index starts at 0.
97 reg = <0x21300 4>;
100 ranges = <0 0x21100 0x200>;
101 cell-index = <0>;
103 dma-channel@0 {
105 reg = <0 0x80>;
106 cell-index = <0>;
112 reg = <0x80 0x80>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Ddm816x.dtsi27 #size-cells = <0>;
28 cpu@0 {
31 reg = <0>;
61 reg = <0x44000000 0x10000>;
69 reg = <0x48180000 0x4000>;
72 ranges = <0 0x48180000 0x4000>;
76 #size-cells = <0>;
85 reg = <0x48140000 0x21000>;
89 ranges = <0 0x48140000 0x21000>;
93 reg = <0x800 0x50a>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/broadcom/
H A Dbcm-nsp.dtsi54 #size-cells = <0>;
56 cpu0: cpu@0 {
60 reg = <0x0>;
68 secondary-boot-reg = <0xffff0fec>;
69 reg = <0x1>;
82 ranges = <0x00000000 0x19000000 0x00023000>;
86 a9pll: arm_clk@0 {
87 #clock-cells = <0>;
[all...]
H A Dbcm-hr2.dtsi45 #size-cells = <0>;
47 cpu0: cpu@0 {
51 reg = <0x0>;
64 ranges = <0x00000000 0x19000000 0x00023000>;
68 a9pll: arm_clk@0 {
69 #clock-cells = <0>;
72 reg = <0x0 0x100
[all...]
H A Dbcm-ns.dtsi26 ranges = <0x00000000 0x18000000 0x00001000>;
32 reg = <0x0300 0x100>;
40 reg = <0x0400 0x100>;
44 pinctrl-0 = <&pinmux_uart1>;
51 ranges = <0x00000000 0x1900000
[all...]
H A Dbcm-cygnus.dtsi48 memory@0 {
50 reg = <0 0>;
55 #size-cells = <0>;
57 cpu@0 {
61 reg = <0x0>;
74 ranges = <0x00000000 0x19000000 0x1000000>;
80 reg = <0x2020
[all...]
/freebsd/sys/contrib/device-tree/src/arm64/allwinner/
H A Dsun50i-a100.dtsi19 #size-cells = <0>;
21 cpu0: cpu@0 {
24 reg = <0x0>;
32 reg = <0x1>;
40 reg = <0x2>;
48 reg = <0x3>;
72 #clock-cells = <0>;
80 #clock-cells = <0>;
87 #clock-cells = <0>;
106 ranges = <0 0 0 0x3fffffff>;
[all …]
/freebsd/sys/dev/qcom_gcc/
H A Dqcom_gcc_ipq4018_reset.c57 [WIFI0_CPU_INIT_RESET] = { 0x1f008, 5 },
58 [WIFI0_RADIO_SRIF_RESET] = { 0x1f008, 4 },
59 [WIFI0_RADIO_WARM_RESET] = { 0x1f008, 3 },
60 [WIFI0_RADIO_COLD_RESET] = { 0x1f008, 2 },
61 [WIFI0_CORE_WARM_RESET] = { 0x1f008, 1 },
62 [WIFI0_CORE_COLD_RESET] = { 0x1f008, 0 },
63 [WIFI1_CPU_INIT_RESET] = { 0x20008, 5 },
64 [WIFI1_RADIO_SRIF_RESET] = { 0x20008, 4 },
65 [WIFI1_RADIO_WARM_RESET] = { 0x20008, 3 },
66 [WIFI1_RADIO_COLD_RESET] = { 0x20008, 2 },
[all …]
/freebsd/sys/contrib/device-tree/Bindings/powerpc/fsl/
H A Ddma.txt14 - cell-index : controller index. 0 for controller @ 0x8100
21 - cell-index : DMA channel index starts at 0.
33 reg = <0x82a8 4>;
34 ranges = <0 0x8100 0x1a4>;
37 cell-index = <0>;
38 dma-channel@0 {
40 cell-index = <0>;
41 reg = <0 0x80>;
48 reg = <0x80 0x80>;
55 reg = <0x100 0x80>;
[all …]
/freebsd/sys/contrib/dev/mediatek/mt76/mt7615/
H A Dmmio.c15 [MT_TOP_CFG_BASE] = 0x01000,
16 [MT_HW_BASE] = 0x01000,
17 [MT_PCIE_REMAP_2] = 0x02504,
18 [MT_ARB_BASE] = 0x20c00,
19 [MT_HIF_BASE] = 0x04000,
20 [MT_CSR_BASE] = 0x07000,
21 [MT_PLE_BASE] = 0x08000,
22 [MT_PSE_BASE] = 0x0c000,
23 [MT_CFG_BASE] = 0x20200,
24 [MT_AGG_BASE] = 0x20a00,
[all …]
/freebsd/sys/contrib/device-tree/src/arm/marvell/
H A Darmada-xp.dtsi35 reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
41 reg = <0x1400 0x500>;
46 reg = <0x08000 0x1000>;
47 cache-id-part = <0x100>;
55 pinctrl-0 = <&uart2_pins>;
57 reg = <0x12200 0x100>;
61 clocks = <&coreclk 0>;
67 pinctrl-0 = <&uart3_pins>;
69 reg = <0x12300 0x100>;
73 clocks = <&coreclk 0>;
[all …]
H A Darmada-xp-98dx3236.dtsi28 #size-cells = <0>;
31 cpu@0 {
34 reg = <0>;
35 clocks = <&cpuclk 0>;
43 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
44 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
45 MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
46 MBUS_ID(0x03, 0x00) 0 0 0xa8000000 0x4000000
47 MBUS_ID(0x08, 0x00) 0 0 0xac000000 0x100000>;
51 reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
[all …]
H A Darmada-370.dtsi35 reg = <MBUS_ID(0x01, 0xe0) 0 0x100000>;
47 bus-range = <0x00 0xff>;
50 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
51 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
52 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
53 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
54 0x82000000 0x2 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
55 0x81000000 0x2 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>;
57 pcie0: pcie@1,0 {
59 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
[all …]
/freebsd/tests/sys/fs/fusefs/
H A Dmockfs.hh68 strcmp(in.body.lookup, (path)) == 0); \
80 const uint32_t max_max_write = 0x20000;
150 * In fusefs-libs 3.4.2 and below the buffer size is fixed at 0x21000
158 max_max_write + 0x1000 - sizeof(struct fuse_in_header)
174 char lookup[0];
185 char rmdir[0];
190 char unlink[0];
209 uint8_t bytes[0x40000];
241 memset(this, 0, sizeof(*this)); in mockfs_buf_out()
399 int expected_errno = 0);
[all …]
/freebsd/sys/contrib/dev/mediatek/mt76/mt7996/
H A Dmmio.c28 [WF_AGG_BASE] = { { 0x820e2000, 0x820f2000, 0x830e2000 } },
29 [WF_ARB_BASE] = { { 0x820e3000, 0x820f3000, 0x830e3000 } },
30 [WF_TMAC_BASE] = { { 0x820e4000, 0x820f4000, 0x830e4000 } },
31 [WF_RMAC_BASE] = { { 0x820e5000, 0x820f5000, 0x830e5000 } },
32 [WF_DMA_BASE] = { { 0x820e7000, 0x820f7000, 0x830e7000 } },
33 [WF_WTBLOFF_BASE] = { { 0x820e9000, 0x820f9000, 0x830e9000 } },
34 [WF_ETBF_BASE] = { { 0x820ea000, 0x820fa000, 0x830ea000 } },
35 [WF_LPON_BASE] = { { 0x820eb000, 0x820fb000, 0x830eb000 } },
36 [WF_MIB_BASE] = { { 0x820ed000, 0x820fd000, 0x830ed000 } },
37 [WF_RATE_BASE] = { { 0x820ee000, 0x820fe000, 0x830ee000 } },
[all …]
/freebsd/sys/contrib/dev/mediatek/mt76/mt7915/
H A Dmmio.c25 [INT_SOURCE_CSR] = 0xd7010,
26 [INT_MASK_CSR] = 0xd7014,
27 [INT1_SOURCE_CSR] = 0xd7088,
28 [INT1_MASK_CSR] = 0xd708c,
29 [INT_MCU_CMD_SOURCE] = 0xd51f0,
30 [INT_MCU_CMD_EVENT] = 0x3108,
31 [WFDMA0_ADDR] = 0xd4000,
32 [WFDMA0_PCIE1_ADDR] = 0xd8000,
33 [WFDMA_EXT_CSR_ADDR] = 0xd7000,
34 [CBTOP1_PHY_END] = 0x77ffffff,
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dipq5018.dtsi21 #clock-cells = <0>;
26 #clock-cells = <0>;
32 #size-cells = <0>;
34 cpu0: cpu@0 {
37 reg = <0x0>;
47 reg = <0x1>;
57 cache-size = <0x80000>;
82 qcom,dload-mode = <&tcsr 0x6100>;
90 reg = <0x0 0x40000000 0x0 0x0>;
109 reg = <0x0 0x4a800000 0x0 0x200000>;
[all …]
H A Dipq5332.dtsi21 #clock-cells = <0>;
26 #clock-cells = <0>;
32 #size-cells = <0>;
34 cpu0: cpu@0 {
37 reg = <0x0>;
47 reg = <0x1>;
57 reg = <0x2>;
67 reg = <0x3>;
84 qcom,dload-mode = <&tcsr 0x6100>;
91 reg = <0x0 0x40000000 0x0 0x0>;
[all …]
/freebsd/sys/contrib/dev/mediatek/mt76/
H A Dmt792x_regs.h8 #define MT_MCU_WFDMA1_BASE 0x3000
11 #define MT_MCU_INT_EVENT MT_MCU_WFDMA1(0x108)
12 #define MT_MCU_INT_EVENT_DMA_STOPPED BIT(0)
17 #define MT_PLE_BASE 0x820c0000
20 #define MT_PLE_FL_Q0_CTRL MT_PLE(0x3e0)
21 #define MT_PLE_FL_Q1_CTRL MT_PLE(0x3e4)
22 #define MT_PLE_FL_Q2_CTRL MT_PLE(0x3e8)
23 #define MT_PLE_FL_Q3_CTRL MT_PLE(0x3ec)
25 #define MT_PLE_AC_QEMPTY(_n) MT_PLE(0x500 + 0x40 * (_n))
26 #define MT_PLE_AMSDU_PACK_MSDU_CNT(n) MT_PLE(0x10e0 + ((n) << 2))
[all …]
/freebsd/sys/contrib/dev/mediatek/mt76/mt7921/
H A Dpci.c21 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7961),
23 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7922),
25 { PCI_DEVICE(PCI_VENDOR_ID_ITTIM, 0x7922),
27 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x0608),
29 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x0616),
31 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7920),
74 { 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */ in __mt7921_reg_addr()
75 { 0x820ed000, 0x24800, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */ in __mt7921_reg_addr()
76 { 0x820e4000, 0x21000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */ in __mt7921_reg_addr()
77 { 0x820e7000, 0x21e00, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */ in __mt7921_reg_addr()
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/apple/
H A Dt7001-pmgr.dtsi11 reg = <0x20000 4>;
12 #power-domain-cells = <0>;
13 #reset-cells = <0>;
20 reg = <0x20008 4>;
21 #power-domain-cells = <0>;
22 #reset-cells = <0>;
29 reg = <0x20010 4>;
30 #power-domain-cells = <0>;
31 #reset-cells = <0>;
38 reg = <0x20040 4>;
[all …]

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