xref: /freebsd/sys/dev/qcom_gcc/qcom_gcc_ipq4018_reset.c (revision 7fead5f144a874a317cba29130a76a11629903ea)
1cd32ac64SAdrian Chadd /*-
24d846d26SWarner Losh  * SPDX-License-Identifier: BSD-2-Clause
3cd32ac64SAdrian Chadd  *
4cd32ac64SAdrian Chadd  * Copyright (c) 2021, Adrian Chadd <adrian@FreeBSD.org>
5cd32ac64SAdrian Chadd  *
6cd32ac64SAdrian Chadd  * Redistribution and use in source and binary forms, with or without
7cd32ac64SAdrian Chadd  * modification, are permitted provided that the following conditions
8cd32ac64SAdrian Chadd  * are met:
9cd32ac64SAdrian Chadd  * 1. Redistributions of source code must retain the above copyright
10cd32ac64SAdrian Chadd  *    notice unmodified, this list of conditions, and the following
11cd32ac64SAdrian Chadd  *    disclaimer.
12cd32ac64SAdrian Chadd  * 2. Redistributions in binary form must reproduce the above copyright
13cd32ac64SAdrian Chadd  *    notice, this list of conditions and the following disclaimer in the
14cd32ac64SAdrian Chadd  *    documentation and/or other materials provided with the distribution.
15cd32ac64SAdrian Chadd  *
16cd32ac64SAdrian Chadd  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17cd32ac64SAdrian Chadd  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18cd32ac64SAdrian Chadd  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19cd32ac64SAdrian Chadd  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20cd32ac64SAdrian Chadd  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21cd32ac64SAdrian Chadd  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22cd32ac64SAdrian Chadd  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23cd32ac64SAdrian Chadd  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24cd32ac64SAdrian Chadd  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25cd32ac64SAdrian Chadd  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26cd32ac64SAdrian Chadd  */
27cd32ac64SAdrian Chadd 
28cd32ac64SAdrian Chadd /* Driver for Qualcomm IPQ4018 clock and reset device */
29cd32ac64SAdrian Chadd 
30cd32ac64SAdrian Chadd #include <sys/param.h>
31cd32ac64SAdrian Chadd #include <sys/kernel.h>
32cd32ac64SAdrian Chadd #include <sys/malloc.h>
33cd32ac64SAdrian Chadd #include <sys/module.h>
34cd32ac64SAdrian Chadd #include <sys/sglist.h>
35cd32ac64SAdrian Chadd #include <sys/random.h>
36cd32ac64SAdrian Chadd #include <sys/stdatomic.h>
37cd32ac64SAdrian Chadd #include <sys/mutex.h>
38cd32ac64SAdrian Chadd 
39cd32ac64SAdrian Chadd #include <machine/bus.h>
40cd32ac64SAdrian Chadd #include <machine/resource.h>
41cd32ac64SAdrian Chadd #include <sys/bus.h>
42cd32ac64SAdrian Chadd 
43cd32ac64SAdrian Chadd #include <dev/fdt/fdt_common.h>
44cd32ac64SAdrian Chadd #include <dev/ofw/ofw_bus.h>
45cd32ac64SAdrian Chadd #include <dev/ofw/ofw_bus_subr.h>
46cd32ac64SAdrian Chadd 
471f469a9fSEmmanuel Vadot #include <dev/hwreset/hwreset.h>
48cd32ac64SAdrian Chadd 
49cd32ac64SAdrian Chadd #include "hwreset_if.h"
50cd32ac64SAdrian Chadd 
51cd32ac64SAdrian Chadd #include <dt-bindings/clock/qcom,gcc-ipq4019.h>
52cd32ac64SAdrian Chadd 
53*7fead5f1SAdrian Chadd #include "qcom_gcc_var.h"
54*7fead5f1SAdrian Chadd #include "qcom_gcc_ipq4018.h"
55cd32ac64SAdrian Chadd 
56*7fead5f1SAdrian Chadd static const struct qcom_gcc_reset_entry gcc_ipq4019_reset_list[] = {
57cd32ac64SAdrian Chadd 	[WIFI0_CPU_INIT_RESET] = { 0x1f008, 5 },
58cd32ac64SAdrian Chadd 	[WIFI0_RADIO_SRIF_RESET] = { 0x1f008, 4 },
59cd32ac64SAdrian Chadd 	[WIFI0_RADIO_WARM_RESET] = { 0x1f008, 3 },
60cd32ac64SAdrian Chadd 	[WIFI0_RADIO_COLD_RESET] = { 0x1f008, 2 },
61cd32ac64SAdrian Chadd 	[WIFI0_CORE_WARM_RESET] = { 0x1f008, 1 },
62cd32ac64SAdrian Chadd 	[WIFI0_CORE_COLD_RESET] = { 0x1f008, 0 },
63cd32ac64SAdrian Chadd 	[WIFI1_CPU_INIT_RESET] = { 0x20008, 5 },
64cd32ac64SAdrian Chadd 	[WIFI1_RADIO_SRIF_RESET] = { 0x20008, 4 },
65cd32ac64SAdrian Chadd 	[WIFI1_RADIO_WARM_RESET] = { 0x20008, 3 },
66cd32ac64SAdrian Chadd 	[WIFI1_RADIO_COLD_RESET] = { 0x20008, 2 },
67cd32ac64SAdrian Chadd 	[WIFI1_CORE_WARM_RESET] = { 0x20008, 1 },
68cd32ac64SAdrian Chadd 	[WIFI1_CORE_COLD_RESET] = { 0x20008, 0 },
69cd32ac64SAdrian Chadd 	[USB3_UNIPHY_PHY_ARES] = { 0x1e038, 5 },
70cd32ac64SAdrian Chadd 	[USB3_HSPHY_POR_ARES] = { 0x1e038, 4 },
71cd32ac64SAdrian Chadd 	[USB3_HSPHY_S_ARES] = { 0x1e038, 2 },
72cd32ac64SAdrian Chadd 	[USB2_HSPHY_POR_ARES] = { 0x1e01c, 4 },
73cd32ac64SAdrian Chadd 	[USB2_HSPHY_S_ARES] = { 0x1e01c, 2 },
74cd32ac64SAdrian Chadd 	[PCIE_PHY_AHB_ARES] = { 0x1d010, 11 },
75cd32ac64SAdrian Chadd 	[PCIE_AHB_ARES] = { 0x1d010, 10 },
76cd32ac64SAdrian Chadd 	[PCIE_PWR_ARES] = { 0x1d010, 9 },
77cd32ac64SAdrian Chadd 	[PCIE_PIPE_STICKY_ARES] = { 0x1d010, 8 },
78cd32ac64SAdrian Chadd 	[PCIE_AXI_M_STICKY_ARES] = { 0x1d010, 7 },
79cd32ac64SAdrian Chadd 	[PCIE_PHY_ARES] = { 0x1d010, 6 },
80cd32ac64SAdrian Chadd 	[PCIE_PARF_XPU_ARES] = { 0x1d010, 5 },
81cd32ac64SAdrian Chadd 	[PCIE_AXI_S_XPU_ARES] = { 0x1d010, 4 },
82cd32ac64SAdrian Chadd 	[PCIE_AXI_M_VMIDMT_ARES] = { 0x1d010, 3 },
83cd32ac64SAdrian Chadd 	[PCIE_PIPE_ARES] = { 0x1d010, 2 },
84cd32ac64SAdrian Chadd 	[PCIE_AXI_S_ARES] = { 0x1d010, 1 },
85cd32ac64SAdrian Chadd 	[PCIE_AXI_M_ARES] = { 0x1d010, 0 },
86cd32ac64SAdrian Chadd 	[ESS_RESET] = { 0x12008, 0},
87cd32ac64SAdrian Chadd 	[GCC_BLSP1_BCR] = {0x01000, 0},
88cd32ac64SAdrian Chadd 	[GCC_BLSP1_QUP1_BCR] = {0x02000, 0},
89cd32ac64SAdrian Chadd 	[GCC_BLSP1_UART1_BCR] = {0x02038, 0},
90cd32ac64SAdrian Chadd 	[GCC_BLSP1_QUP2_BCR] = {0x03008, 0},
91cd32ac64SAdrian Chadd 	[GCC_BLSP1_UART2_BCR] = {0x03028, 0},
92cd32ac64SAdrian Chadd 	[GCC_BIMC_BCR] = {0x04000, 0},
93cd32ac64SAdrian Chadd 	[GCC_TLMM_BCR] = {0x05000, 0},
94cd32ac64SAdrian Chadd 	[GCC_IMEM_BCR] = {0x0E000, 0},
95cd32ac64SAdrian Chadd 	[GCC_ESS_BCR] = {0x12008, 0},
96cd32ac64SAdrian Chadd 	[GCC_PRNG_BCR] = {0x13000, 0},
97cd32ac64SAdrian Chadd 	[GCC_BOOT_ROM_BCR] = {0x13008, 0},
98cd32ac64SAdrian Chadd 	[GCC_CRYPTO_BCR] = {0x16000, 0},
99cd32ac64SAdrian Chadd 	[GCC_SDCC1_BCR] = {0x18000, 0},
100cd32ac64SAdrian Chadd 	[GCC_SEC_CTRL_BCR] = {0x1A000, 0},
101cd32ac64SAdrian Chadd 	[GCC_AUDIO_BCR] = {0x1B008, 0},
102cd32ac64SAdrian Chadd 	[GCC_QPIC_BCR] = {0x1C000, 0},
103cd32ac64SAdrian Chadd 	[GCC_PCIE_BCR] = {0x1D000, 0},
104cd32ac64SAdrian Chadd 	[GCC_USB2_BCR] = {0x1E008, 0},
105cd32ac64SAdrian Chadd 	[GCC_USB2_PHY_BCR] = {0x1E018, 0},
106cd32ac64SAdrian Chadd 	[GCC_USB3_BCR] = {0x1E024, 0},
107cd32ac64SAdrian Chadd 	[GCC_USB3_PHY_BCR] = {0x1E034, 0},
108cd32ac64SAdrian Chadd 	[GCC_SYSTEM_NOC_BCR] = {0x21000, 0},
109cd32ac64SAdrian Chadd 	[GCC_PCNOC_BCR] = {0x2102C, 0},
110cd32ac64SAdrian Chadd 	[GCC_DCD_BCR] = {0x21038, 0},
111cd32ac64SAdrian Chadd 	[GCC_SNOC_BUS_TIMEOUT0_BCR] = {0x21064, 0},
112cd32ac64SAdrian Chadd 	[GCC_SNOC_BUS_TIMEOUT1_BCR] = {0x2106C, 0},
113cd32ac64SAdrian Chadd 	[GCC_SNOC_BUS_TIMEOUT2_BCR] = {0x21074, 0},
114cd32ac64SAdrian Chadd 	[GCC_SNOC_BUS_TIMEOUT3_BCR] = {0x2107C, 0},
115cd32ac64SAdrian Chadd 	[GCC_PCNOC_BUS_TIMEOUT0_BCR] = {0x21084, 0},
116cd32ac64SAdrian Chadd 	[GCC_PCNOC_BUS_TIMEOUT1_BCR] = {0x2108C, 0},
117cd32ac64SAdrian Chadd 	[GCC_PCNOC_BUS_TIMEOUT2_BCR] = {0x21094, 0},
118cd32ac64SAdrian Chadd 	[GCC_PCNOC_BUS_TIMEOUT3_BCR] = {0x2109C, 0},
119cd32ac64SAdrian Chadd 	[GCC_PCNOC_BUS_TIMEOUT4_BCR] = {0x210A4, 0},
120cd32ac64SAdrian Chadd 	[GCC_PCNOC_BUS_TIMEOUT5_BCR] = {0x210AC, 0},
121cd32ac64SAdrian Chadd 	[GCC_PCNOC_BUS_TIMEOUT6_BCR] = {0x210B4, 0},
122cd32ac64SAdrian Chadd 	[GCC_PCNOC_BUS_TIMEOUT7_BCR] = {0x210BC, 0},
123cd32ac64SAdrian Chadd 	[GCC_PCNOC_BUS_TIMEOUT8_BCR] = {0x210C4, 0},
124cd32ac64SAdrian Chadd 	[GCC_PCNOC_BUS_TIMEOUT9_BCR] = {0x210CC, 0},
125cd32ac64SAdrian Chadd 	[GCC_TCSR_BCR] = {0x22000, 0},
126cd32ac64SAdrian Chadd 	[GCC_MPM_BCR] = {0x24000, 0},
127cd32ac64SAdrian Chadd 	[GCC_SPDM_BCR] = {0x25000, 0},
128cd32ac64SAdrian Chadd };
129cd32ac64SAdrian Chadd 
130*7fead5f1SAdrian Chadd static int
qcom_gcc_ipq4018_hwreset_assert(device_t dev,intptr_t id,bool reset)131cd32ac64SAdrian Chadd qcom_gcc_ipq4018_hwreset_assert(device_t dev, intptr_t id, bool reset)
132cd32ac64SAdrian Chadd {
133*7fead5f1SAdrian Chadd 	struct qcom_gcc_softc *sc;
134cd32ac64SAdrian Chadd 	uint32_t reg;
135cd32ac64SAdrian Chadd 
136cd32ac64SAdrian Chadd 	sc = device_get_softc(dev);
137cd32ac64SAdrian Chadd 
138cd32ac64SAdrian Chadd 	if (id > nitems(gcc_ipq4019_reset_list)) {
139cd32ac64SAdrian Chadd 		device_printf(dev, "%s: invalid id (%d)\n", __func__, id);
140cd32ac64SAdrian Chadd 		return (EINVAL);
141cd32ac64SAdrian Chadd 	}
142cd32ac64SAdrian Chadd 
143cd32ac64SAdrian Chadd 	mtx_lock(&sc->mtx);
144cd32ac64SAdrian Chadd 	reg = bus_read_4(sc->reg, gcc_ipq4019_reset_list[id].reg);
145cd32ac64SAdrian Chadd 	if (reset)
146cd32ac64SAdrian Chadd 		reg |= (1U << gcc_ipq4019_reset_list[id].bit);
147cd32ac64SAdrian Chadd 	else
148cd32ac64SAdrian Chadd 		reg &= ~(1U << gcc_ipq4019_reset_list[id].bit);
149cd32ac64SAdrian Chadd 	bus_write_4(sc->reg, gcc_ipq4019_reset_list[id].reg, reg);
150cd32ac64SAdrian Chadd 	mtx_unlock(&sc->mtx);
151cd32ac64SAdrian Chadd 	return (0);
152cd32ac64SAdrian Chadd }
153cd32ac64SAdrian Chadd 
154*7fead5f1SAdrian Chadd static int
qcom_gcc_ipq4018_hwreset_is_asserted(device_t dev,intptr_t id,bool * reset)155cd32ac64SAdrian Chadd qcom_gcc_ipq4018_hwreset_is_asserted(device_t dev, intptr_t id, bool *reset)
156cd32ac64SAdrian Chadd {
157*7fead5f1SAdrian Chadd 	struct qcom_gcc_softc *sc;
158cd32ac64SAdrian Chadd 	uint32_t reg;
159cd32ac64SAdrian Chadd 
160cd32ac64SAdrian Chadd 	sc = device_get_softc(dev);
161cd32ac64SAdrian Chadd 
162cd32ac64SAdrian Chadd 	if (id > nitems(gcc_ipq4019_reset_list)) {
163cd32ac64SAdrian Chadd 		device_printf(dev, "%s: invalid id (%d)\n", __func__, id);
164cd32ac64SAdrian Chadd 		return (EINVAL);
165cd32ac64SAdrian Chadd 	}
166cd32ac64SAdrian Chadd 	mtx_lock(&sc->mtx);
167cd32ac64SAdrian Chadd 	reg = bus_read_4(sc->reg, gcc_ipq4019_reset_list[id].reg);
168cd32ac64SAdrian Chadd 	if (reg & ((1U << gcc_ipq4019_reset_list[id].bit)))
169cd32ac64SAdrian Chadd 		*reset = true;
170cd32ac64SAdrian Chadd 	else
171cd32ac64SAdrian Chadd 		*reset = false;
172cd32ac64SAdrian Chadd 	mtx_unlock(&sc->mtx);
173cd32ac64SAdrian Chadd 
174cd32ac64SAdrian Chadd 	device_printf(dev, "called; id=%d\n", id);
175cd32ac64SAdrian Chadd 	return (0);
176cd32ac64SAdrian Chadd }
177cd32ac64SAdrian Chadd 
178*7fead5f1SAdrian Chadd void
qcom_gcc_ipq4018_hwreset_init(struct qcom_gcc_softc * sc)179*7fead5f1SAdrian Chadd qcom_gcc_ipq4018_hwreset_init(struct qcom_gcc_softc *sc)
180*7fead5f1SAdrian Chadd {
181*7fead5f1SAdrian Chadd 	sc->sc_cb.hw_reset_assert = qcom_gcc_ipq4018_hwreset_assert;
182*7fead5f1SAdrian Chadd 	sc->sc_cb.hw_reset_is_asserted = qcom_gcc_ipq4018_hwreset_is_asserted;
183*7fead5f1SAdrian Chadd }
184