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/linux/arch/mips/include/asm/mach-ralink/
H A Dmt7621.h12 #define MT7621_PALMBUS_BASE 0x1C000000
13 #define MT7621_PALMBUS_SIZE 0x03FFFFFF
15 #define MT7621_SYSC_BASE IOMEM(0x1E000000)
17 #define SYSC_REG_CHIP_NAME0 0x00
18 #define SYSC_REG_CHIP_NAME1 0x04
19 #define SYSC_REG_CHIP_REV 0x0c
20 #define SYSC_REG_SYSTEM_CONFIG0 0x10
21 #define SYSC_REG_SYSTEM_CONFIG1 0x14
23 #define CHIP_REV_PKG_MASK 0x1
25 #define CHIP_REV_VER_MASK 0xf
[all …]
H A Drt3883.h15 #define RT3883_SDRAM_BASE 0x00000000
16 #define RT3883_SYSC_BASE IOMEM(0x10000000)
17 #define RT3883_TIMER_BASE 0x10000100
18 #define RT3883_INTC_BASE 0x10000200
19 #define RT3883_MEMC_BASE 0x10000300
20 #define RT3883_UART0_BASE 0x10000500
21 #define RT3883_PIO_BASE 0x10000600
22 #define RT3883_FSCC_BASE 0x10000700
23 #define RT3883_NANDC_BASE 0x10000810
24 #define RT3883_I2C_BASE 0x10000900
[all …]
/linux/arch/mips/cobalt/
H A Dled.c15 .start = 0x1c000000,
16 .end = 0x1c000000,
42 return 0; in cobalt_led_add()
H A Dreset.c20 #define RESET_PORT ((void __iomem *)CKSEG1ADDR(0x1c000000))
21 #define RESET 0x0f
28 return 0; in ledtrig_power_off_init()
/linux/Documentation/devicetree/bindings/bus/
H A Dqcom,ebi2.yaml31 CS0 GPIO134 0x1a800000-0x1b000000 (8MB)
32 CS1 GPIO39 (A) / GPIO123 (B) 0x1b000000-0x1b800000 (8MB)
33 CS2 GPIO40 (A) / GPIO124 (B) 0x1b800000-0x1c000000 (8MB)
34 CS3 GPIO133 0x1d000000-0x25000000 (128 MB)
35 CS4 GPIO132 0x1c800000-0x1d000000 (8MB)
36 CS5 GPIO131 0x1c000000-0x1c800000 (8MB)
105 "^.*@[0-5],[0-9a-f]+$":
120 actually 1, so a value of 0 will still yield 1 recovery cycle.
121 minimum: 0
129 asserted. With a hold of 1 (value = 0), the CS stays active
[all …]
/linux/arch/sh/boards/
H A Dboard-urquell.c32 * SW2 0x1x xxxx -> little endian
39 * 0x00000000 - 0x04000000 (CS0) Nor Flash
40 * 0x04000000 - 0x04200000 (CS1) SRAM
41 * 0x05000000 - 0x05800000 (CS1) on board register
42 * 0x05800000 - 0x06000000 (CS1) LAN91C111
43 * 0x06000000 - 0x06400000 (CS1) PCMCIA
44 * 0x08000000 - 0x10000000 (CS2-CS3) DDR3
45 * 0x10000000 - 0x14000000 (CS4) PCIe
46 * 0x14000000 - 0x14800000 (CS5) Core0 LRAM/URAM
47 * 0x14800000 - 0x15000000 (CS5) Core1 LRAM/URAM
[all …]
/linux/arch/sh/include/cpu-sh4/cpu/
H A Daddrspace.h10 #define P0SEG 0x00000000
11 #define P1SEG 0x80000000
12 #define P2SEG 0xa0000000
13 #define P3SEG 0xc0000000
14 #define P4SEG 0xe0000000
18 #define P4SEG_IC_ADDR 0xf0000000
19 #define P4SEG_IC_DATA 0xf1000000
20 #define P4SEG_ITLB_ADDR 0xf2000000
21 #define P4SEG_ITLB_DATA 0xf3000000
22 #define P4SEG_OC_ADDR 0xf4000000
[all …]
/linux/drivers/accel/habanalabs/include/goya/asic_reg/
H A Dmme_masks.h23 #define MME_ARCH_STATUS_A_SHIFT 0
24 #define MME_ARCH_STATUS_A_MASK 0x1
26 #define MME_ARCH_STATUS_B_MASK 0x2
28 #define MME_ARCH_STATUS_CIN_MASK 0x4
30 #define MME_ARCH_STATUS_COUT_MASK 0x8
32 #define MME_ARCH_STATUS_TE_MASK 0x10
34 #define MME_ARCH_STATUS_LD_MASK 0x20
36 #define MME_ARCH_STATUS_ST_MASK 0x40
38 #define MME_ARCH_STATUS_SB_A_EMPTY_MASK 0x80
40 #define MME_ARCH_STATUS_SB_B_EMPTY_MASK 0x100
[all …]
/linux/arch/arm/include/debug/
H A Dvexpress.S10 #define DEBUG_LL_PHYS_BASE 0x10000000
11 #define DEBUG_LL_UART_OFFSET 0x00009000
13 #define DEBUG_LL_PHYS_BASE_RS1 0x1c000000
14 #define DEBUG_LL_UART_OFFSET_RS1 0x00090000
16 #define DEBUG_LL_UART_PHYS_CRX 0xb0090000
18 #define DEBUG_LL_VIRT_BASE 0xf8000000
27 @ should use UART at 0x10009000
29 @ at 0x1c090000
30 mrc p15, 0, \rp, c0, c0, 0
31 movw \rv, #0xc091
[all …]
/linux/arch/mips/include/asm/mach-malta/
H A Dspaces.h17 * 0x00000000 - 0x0fffffff: 1st RAM region, 256MB
18 * 0x10000000 - 0x1bffffff: GIC and CPC Control Registers
19 * 0x1c000000 - 0x1fffffff: I/O And Flash
20 * 0x20000000 - 0x7fffffff: 2nd RAM region, 1.5GB
21 * 0x80000000 - 0xffffffff: Physical memory aliases to 0x0 (2GB)
23 * The kernel is still located in 0x80000000(kseg0). However,
24 * the physical mask has been shifted to 0x80000000 which exploits the alias
27 * words, the 0x80000000 virtual address maps to 0x80000000 physical address
28 * which in turn aliases to 0x0. We do this in order to be able to use a flat
29 * 2GB of memory (0x80000000 - 0xffffffff) so we can avoid the I/O hole in
[all …]
/linux/arch/arm/mach-pxa/
H A Dpxa-regs.h14 #define UNCACHED_PHYS_0 0xfe000000
15 #define UNCACHED_PHYS_0_SIZE 0x00100000
20 * 0x40000000 - 0x41ffffff <--> 0xf2000000 - 0xf3ffffff
21 * 0x44000000 - 0x45ffffff <--> 0xf4000000 - 0xf5ffffff
22 * 0x48000000 - 0x49ffffff <--> 0xf6000000 - 0xf7ffffff
23 * 0x4c000000 - 0x4dffffff <--> 0xf8000000 - 0xf9ffffff
24 * 0x50000000 - 0x51ffffff <--> 0xfa000000 - 0xfbffffff
25 * 0x54000000 - 0x55ffffff <--> 0xfc000000 - 0xfdffffff
26 * 0x58000000 - 0x59ffffff <--> 0xfe000000 - 0xffffffff
31 #define io_v2p(x) (0x3c000000 + ((x) & 0x01ffffff) + (((x) & 0x0e000000) << 1))
[all …]
/linux/arch/mips/boot/dts/ralink/
H A Dmt7621-gnubee-gb-pc1.dts13 memory@0 {
15 reg = <0x00000000 0x1c000000>,
16 <0x20000000 0x04000000>;
57 flash@0 {
61 reg = <0>;
65 partition@0 {
67 reg = <0x0 0x30000>;
73 reg = <0x30000 0x10000>;
79 reg = <0x40000 0x10000>;
85 reg = <0x50000 0x1fb0000>;
[all …]
H A Dmt7621-gnubee-gb-pc2.dts13 memory@0 {
15 reg = <0x00000000 0x1c000000>,
16 <0x20000000 0x04000000>;
77 flash@0 {
81 reg = <0>;
85 partition@0 {
87 reg = <0x0 0x30000>;
93 reg = <0x30000 0x10000>;
99 reg = <0x40000 0x10000>;
105 reg = <0x50000 0x1fb0000>;
[all …]
/linux/arch/mips/include/asm/dec/
H A Dkn02xa.h22 #define KN02XA_SLOT_BASE 0x1c000000
27 #define KN02XA_MER 0x0c400000 /* memory error register */
28 #define KN02XA_MSR 0x0c800000 /* memory size register */
33 #define KN02XA_MEM_CONF 0x0e000000 /* write timeout config */
34 #define KN02XA_EAR 0x0e000004 /* error address register */
35 #define KN02XA_BOOT0 0x0e000008 /* boot 0 register */
36 #define KN02XA_MEM_INTR 0x0e00000c /* write err IRQ stat & ack */
42 #define KN02XA_MER_RES_28 (0xf<<28) /* unused */
43 #define KN02XA_MER_RES_17 (0x3ff<<17) /* unused */
49 #define KN02XA_MER_BYTERR (0xf<<8) /* byte lane error bitmask: */
[all …]
/linux/Documentation/devicetree/bindings/memory-controllers/
H A Darm,pl172.txt11 first address cell and it may accept values 0..N-1
88 Example for pl172 with nor flash on chip select 0 shown below.
92 reg = <0x40005000 0x1000>;
97 ranges = <0 0 0x1c000000 0x1000000
98 1 0 0x1d000000 0x1000000
99 2 0 0x1e000000 0x1000000
100 3 0 0x1f000000 0x1000000>;
107 mpmc,cs = <0>;
110 mpmc,write-enable-delay = <0>;
111 mpmc,output-enable-delay = <0>;
[all …]
/linux/include/linux/bcma/
H A Dbcma_regs.h7 #define BCMA_CLKCTLST 0x01E0 /* Clock control and status */
8 #define BCMA_CLKCTLST_FORCEALP 0x00000001 /* Force ALP request */
9 #define BCMA_CLKCTLST_FORCEHT 0x00000002 /* Force HT request */
10 #define BCMA_CLKCTLST_FORCEILP 0x00000004 /* Force ILP request */
11 #define BCMA_CLKCTLST_HAVEALPREQ 0x00000008 /* ALP available request */
12 #define BCMA_CLKCTLST_HAVEHTREQ 0x00000010 /* HT available request */
13 #define BCMA_CLKCTLST_HWCROFF 0x00000020 /* Force HW clock request off */
14 #define BCMA_CLKCTLST_HQCLKREQ 0x00000040 /* HQ Clock */
15 #define BCMA_CLKCTLST_EXTRESREQ 0x00000700 /* Mask of external resource requests */
17 #define BCMA_CLKCTLST_HAVEALP 0x00010000 /* ALP available */
[all …]
/linux/arch/sh/include/mach-common/mach/
H A Durquell.h6 * ------ 0x00000000 ------------------------------------
8 * -----+ 0x04000000 ------------------------------------
10 * -----+ 0x08000000 ------------------------------------
13 * -----+ 0x10000000 ------------------------------------
15 * -----+ 0x14000000 ------------------------------------
17 * -----+ 0x18000000 ------------------------------------
19 * -----+ 0x1c000000 ------------------------------------
24 #define NOR_FLASH_ADDR 0x00000000
25 #define NOR_FLASH_SIZE 0x04000000
27 #define CS1_BASE 0x05000000
[all …]
/linux/arch/mips/kernel/
H A Dspram.c21 #define SPRAM_TAG0_ENABLE 0x00000080
22 #define SPRAM_TAG0_PA_MASK 0xfffff000
23 #define SPRAM_TAG1_SIZE_MASK 0xfffff000
119 unsigned int firstsize = 0, lastsize = 0; in probe_spram()
120 unsigned int firstpa = 0, lastpa = 0, pa = 0; in probe_spram()
121 unsigned int offset = 0; in probe_spram()
131 for (i = 0; i < 8; i++) { in probe_spram()
139 if (size == 0) in probe_spram()
142 if (i != 0) { in probe_spram()
163 if (i == 0) { in probe_spram()
[all …]
/linux/Documentation/devicetree/bindings/spi/
H A Dsnps,dw-apb-ssi.yaml144 default: 0
163 "^.*@[0-9a-f]+$":
169 minimum: 0
185 reg = <0xfff00000 0x1000>;
187 #size-cells = <0>;
188 interrupts = <0 154 4>;
191 cs-gpios = <&gpio0 13 0>,
192 <&gpio0 14 0>;
203 reg = <0x1f040100 0x900>,
204 <0x1c000000 0x1000000>;
[all …]
/linux/arch/loongarch/include/asm/
H A Dloongson.h20 #define LOONGSON_LIO_BASE 0x18000000
21 #define LOONGSON_LIO_SIZE 0x00100000 /* 1M */
24 #define LOONGSON_BOOT_BASE 0x1c000000
25 #define LOONGSON_BOOT_SIZE 0x02000000 /* 32M */
28 #define LOONGSON_REG_BASE 0x1fe00000
29 #define LOONGSON_REG_SIZE 0x00100000 /* 1M */
34 #define LOONGSON_GPIODATA LOONGSON_REG(0x11c)
35 #define LOONGSON_GPIOIE LOONGSON_REG(0x120)
36 #define LOONGSON_REG_GPIO_BASE (LOONGSON_REG_BASE + 0x11c)
46 " st.w %[v], %[hw], 0 \n" in xconf_writel()
[all …]
/linux/arch/mips/boot/dts/mti/
H A Dsead3.dts4 /memreserve/ 0x00000000 0x00001000; // reserved
5 /memreserve/ 0x00001000 0x000ef000; // ROM data
6 /memreserve/ 0x000f0000 0x004cc000; // reserved
26 cpu@0 {
33 reg = <0x0 0x08000000>;
45 reg = <0x1b1c0000 0x20000>;
61 reg = <0x1b200000 0x1000>;
64 interrupts = <GIC_SHARED 0 IRQ_TYPE_LEVEL_HIGH>; /* GIC 0 or CPU 6 */
71 reg = <0x1c000000 0x2000000>;
81 user-fs@0 {
[all …]
/linux/drivers/clk/qcom/
H A Dapss-ipq-pll.c12 .offset = 0x0,
16 .enable_reg = 0x0,
17 .enable_mask = BIT(0),
30 .offset = 0x0,
34 .enable_reg = 0x0,
35 .enable_mask = BIT(0),
48 .offset = 0x0,
56 .enable_reg = 0x0,
57 .enable_mask = BIT(0),
71 .l = 0x2a,
[all …]
/linux/arch/arm64/boot/dts/arm/
H A Dfoundation-v8.dtsi12 /memreserve/ 0x80000000 0x00010000;
34 #size-cells = <0>;
36 cpu0: cpu@0 {
39 reg = <0x0 0x0>;
45 reg = <0x0 0x1>;
51 reg = <0x0 0x2>;
57 reg = <0x0 0x3>;
70 reg = <0x00000000 0x80000000 0 0x80000000>,
71 <0x00000008 0x80000000 0 0x80000000>;
98 reg = <0x0 0x2a440000 0 0x1000>,
[all …]
/linux/arch/arm/mach-versatile/
H A Dintegrator-hardware.h14 #define IO_BASE 0xF0000000 // VA of IO
15 #define IO_SIZE 0x0B000000 // How much?
19 #define IO_ADDRESS(x) (((x) & 0x000fffff) | (((x) >> 4) & 0x0ff00000) | IO_BASE)
25 #define INTEGRATOR_BOOT_ROM_LO 0x00000000
26 #define INTEGRATOR_BOOT_ROM_HI 0x20000000
40 #define INTEGRATOR_SSRAM_BASE 0x00000000
41 #define INTEGRATOR_SSRAM_ALIAS_BASE 0x10800000
44 #define INTEGRATOR_FLASH_BASE 0x24000000
47 #define INTEGRATOR_MBRD_SSRAM_BASE 0x28000000
53 #define INTEGRATOR_SDRAM_BASE 0x00040000
[all …]
/linux/arch/mips/ath25/
H A Dar5312_regs.h17 #define AR5312_IRQ_WLAN0 (MIPS_CPU_IRQ_BASE + 2) /* C0_CAUSE: 0x0400 */
18 #define AR5312_IRQ_ENET0 (MIPS_CPU_IRQ_BASE + 3) /* C0_CAUSE: 0x0800 */
19 #define AR5312_IRQ_ENET1 (MIPS_CPU_IRQ_BASE + 4) /* C0_CAUSE: 0x1000 */
20 #define AR5312_IRQ_WLAN1 (MIPS_CPU_IRQ_BASE + 5) /* C0_CAUSE: 0x2000 */
21 #define AR5312_IRQ_MISC (MIPS_CPU_IRQ_BASE + 6) /* C0_CAUSE: 0x4000 */
26 #define AR5312_MISC_IRQ_TIMER 0
41 * actually use 1 of them (i.e. Only MAC 0 is actually connected to an enet
44 #define AR5312_WLAN0_BASE 0x18000000
45 #define AR5312_ENET0_BASE 0x18100000
46 #define AR5312_ENET1_BASE 0x18200000
[all …]

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