Lines Matching +full:0 +full:x1c000000
32 * SW2 0x1x xxxx -> little endian
39 * 0x00000000 - 0x04000000 (CS0) Nor Flash
40 * 0x04000000 - 0x04200000 (CS1) SRAM
41 * 0x05000000 - 0x05800000 (CS1) on board register
42 * 0x05800000 - 0x06000000 (CS1) LAN91C111
43 * 0x06000000 - 0x06400000 (CS1) PCMCIA
44 * 0x08000000 - 0x10000000 (CS2-CS3) DDR3
45 * 0x10000000 - 0x14000000 (CS4) PCIe
46 * 0x14000000 - 0x14800000 (CS5) Core0 LRAM/URAM
47 * 0x14800000 - 0x15000000 (CS5) Core1 LRAM/URAM
48 * 0x18000000 - 0x1C000000 (CS6) ATA/NAND-Flash
49 * 0x1C000000 - (CS7) SH7786 Control register
72 [0] = {
74 .start = 0x05800300,
75 .end = 0x0580030f,
79 .start = evt2irq(0x360),
97 .offset = 0x00000000,
126 [0] = {
155 __raw_writew(__raw_readw(UBOARDREG(IRL2MSKR)) & ~0x00000001, in urquell_devices_setup()
165 __raw_writew(0xa5a5, UBOARDREG(SRSTR)); in urquell_power_off()