Lines Matching +full:0 +full:x1c000000
14 #define IO_BASE 0xF0000000 // VA of IO
15 #define IO_SIZE 0x0B000000 // How much?
19 #define IO_ADDRESS(x) (((x) & 0x000fffff) | (((x) >> 4) & 0x0ff00000) | IO_BASE)
25 #define INTEGRATOR_BOOT_ROM_LO 0x00000000
26 #define INTEGRATOR_BOOT_ROM_HI 0x20000000
40 #define INTEGRATOR_SSRAM_BASE 0x00000000
41 #define INTEGRATOR_SSRAM_ALIAS_BASE 0x10800000
44 #define INTEGRATOR_FLASH_BASE 0x24000000
47 #define INTEGRATOR_MBRD_SSRAM_BASE 0x28000000
53 #define INTEGRATOR_SDRAM_BASE 0x00040000
55 #define INTEGRATOR_SDRAM_ALIAS_BASE 0x80000000
56 #define INTEGRATOR_HDR0_SDRAM_BASE 0x80000000
57 #define INTEGRATOR_HDR1_SDRAM_BASE 0x90000000
58 #define INTEGRATOR_HDR2_SDRAM_BASE 0xA0000000
59 #define INTEGRATOR_HDR3_SDRAM_BASE 0xB0000000
65 #define INTEGRATOR_LOGIC_MODULES_BASE 0xC0000000
66 #define INTEGRATOR_LOGIC_MODULE0_BASE 0xC0000000
67 #define INTEGRATOR_LOGIC_MODULE1_BASE 0xD0000000
68 #define INTEGRATOR_LOGIC_MODULE2_BASE 0xE0000000
69 #define INTEGRATOR_LOGIC_MODULE3_BASE 0xF0000000
74 #define INTEGRATOR_HDR_ID_OFFSET 0x00
75 #define INTEGRATOR_HDR_PROC_OFFSET 0x04
76 #define INTEGRATOR_HDR_OSC_OFFSET 0x08
77 #define INTEGRATOR_HDR_CTRL_OFFSET 0x0C
78 #define INTEGRATOR_HDR_STAT_OFFSET 0x10
79 #define INTEGRATOR_HDR_LOCK_OFFSET 0x14
80 #define INTEGRATOR_HDR_SDRAM_OFFSET 0x20
81 #define INTEGRATOR_HDR_INIT_OFFSET 0x24 /* CM9x6 */
82 #define INTEGRATOR_HDR_IC_OFFSET 0x40
83 #define INTEGRATOR_HDR_SPDBASE_OFFSET 0x100
84 #define INTEGRATOR_HDR_SPDTOP_OFFSET 0x200
86 #define INTEGRATOR_HDR_BASE 0x10000000
99 #define INTEGRATOR_HDR_CTRL_LED 0x01
100 #define INTEGRATOR_HDR_CTRL_MBRD_DETECH 0x02
101 #define INTEGRATOR_HDR_CTRL_REMAP 0x04
102 #define INTEGRATOR_HDR_CTRL_RESET 0x08
103 #define INTEGRATOR_HDR_CTRL_HIGHVECTORS 0x10
104 #define INTEGRATOR_HDR_CTRL_BIG_ENDIAN 0x20
105 #define INTEGRATOR_HDR_CTRL_FASTBUS 0x40
106 #define INTEGRATOR_HDR_CTRL_SYNC 0x80
108 #define INTEGRATOR_HDR_OSC_CORE_10MHz 0x102
109 #define INTEGRATOR_HDR_OSC_CORE_15MHz 0x107
110 #define INTEGRATOR_HDR_OSC_CORE_20MHz 0x10C
111 #define INTEGRATOR_HDR_OSC_CORE_25MHz 0x111
112 #define INTEGRATOR_HDR_OSC_CORE_30MHz 0x116
113 #define INTEGRATOR_HDR_OSC_CORE_35MHz 0x11B
114 #define INTEGRATOR_HDR_OSC_CORE_40MHz 0x120
115 #define INTEGRATOR_HDR_OSC_CORE_45MHz 0x125
116 #define INTEGRATOR_HDR_OSC_CORE_50MHz 0x12A
117 #define INTEGRATOR_HDR_OSC_CORE_55MHz 0x12F
118 #define INTEGRATOR_HDR_OSC_CORE_60MHz 0x134
119 #define INTEGRATOR_HDR_OSC_CORE_65MHz 0x139
120 #define INTEGRATOR_HDR_OSC_CORE_70MHz 0x13E
121 #define INTEGRATOR_HDR_OSC_CORE_75MHz 0x143
122 #define INTEGRATOR_HDR_OSC_CORE_80MHz 0x148
123 #define INTEGRATOR_HDR_OSC_CORE_85MHz 0x14D
124 #define INTEGRATOR_HDR_OSC_CORE_90MHz 0x152
125 #define INTEGRATOR_HDR_OSC_CORE_95MHz 0x157
126 #define INTEGRATOR_HDR_OSC_CORE_100MHz 0x15C
127 #define INTEGRATOR_HDR_OSC_CORE_105MHz 0x161
128 #define INTEGRATOR_HDR_OSC_CORE_110MHz 0x166
129 #define INTEGRATOR_HDR_OSC_CORE_115MHz 0x16B
130 #define INTEGRATOR_HDR_OSC_CORE_120MHz 0x170
131 #define INTEGRATOR_HDR_OSC_CORE_125MHz 0x175
132 #define INTEGRATOR_HDR_OSC_CORE_130MHz 0x17A
133 #define INTEGRATOR_HDR_OSC_CORE_135MHz 0x17F
134 #define INTEGRATOR_HDR_OSC_CORE_140MHz 0x184
135 #define INTEGRATOR_HDR_OSC_CORE_145MHz 0x189
136 #define INTEGRATOR_HDR_OSC_CORE_150MHz 0x18E
137 #define INTEGRATOR_HDR_OSC_CORE_155MHz 0x193
138 #define INTEGRATOR_HDR_OSC_CORE_160MHz 0x198
139 #define INTEGRATOR_HDR_OSC_CORE_MASK 0x7FF
141 #define INTEGRATOR_HDR_OSC_MEM_10MHz 0x10C000
142 #define INTEGRATOR_HDR_OSC_MEM_15MHz 0x116000
143 #define INTEGRATOR_HDR_OSC_MEM_20MHz 0x120000
144 #define INTEGRATOR_HDR_OSC_MEM_25MHz 0x12A000
145 #define INTEGRATOR_HDR_OSC_MEM_30MHz 0x134000
146 #define INTEGRATOR_HDR_OSC_MEM_33MHz 0x13A000
147 #define INTEGRATOR_HDR_OSC_MEM_40MHz 0x148000
148 #define INTEGRATOR_HDR_OSC_MEM_50MHz 0x15C000
149 #define INTEGRATOR_HDR_OSC_MEM_60MHz 0x170000
150 #define INTEGRATOR_HDR_OSC_MEM_66MHz 0x17C000
151 #define INTEGRATOR_HDR_OSC_MEM_MASK 0x7FF000
153 #define INTEGRATOR_HDR_OSC_BUS_MODE_CM7x0 0x0
154 #define INTEGRATOR_HDR_OSC_BUS_MODE_CM9x0 0x0800000
155 #define INTEGRATOR_HDR_OSC_BUS_MODE_CM9x6 0x1000000
156 #define INTEGRATOR_HDR_OSC_BUS_MODE_CM10x00 0x1800000
157 #define INTEGRATOR_HDR_OSC_BUS_MODE_MASK 0x1800000
168 #define INTEGRATOR_SC_ID_OFFSET 0x00
169 #define INTEGRATOR_SC_OSC_OFFSET 0x04
170 #define INTEGRATOR_SC_CTRLS_OFFSET 0x08
171 #define INTEGRATOR_SC_CTRLC_OFFSET 0x0C
172 #define INTEGRATOR_SC_DEC_OFFSET 0x10
173 #define INTEGRATOR_SC_ARB_OFFSET 0x14
174 #define INTEGRATOR_SC_LOCK_OFFSET 0x1C
176 #define INTEGRATOR_SC_BASE 0x11000000
186 #define INTEGRATOR_SC_OSC_SYS_10MHz 0x20
187 #define INTEGRATOR_SC_OSC_SYS_15MHz 0x34
188 #define INTEGRATOR_SC_OSC_SYS_20MHz 0x48
189 #define INTEGRATOR_SC_OSC_SYS_25MHz 0x5C
190 #define INTEGRATOR_SC_OSC_SYS_33MHz 0x7C
191 #define INTEGRATOR_SC_OSC_SYS_MASK 0xFF
193 #define INTEGRATOR_SC_OSC_PCI_25MHz 0x100
194 #define INTEGRATOR_SC_OSC_PCI_33MHz 0x0
195 #define INTEGRATOR_SC_OSC_PCI_MASK 0x100
197 #define INTEGRATOR_SC_CTRL_SOFTRST (1 << 0)
208 #define INTEGRATOR_EBI_BASE 0x12000000
210 #define INTEGRATOR_EBI_CSR0_OFFSET 0x00
211 #define INTEGRATOR_EBI_CSR1_OFFSET 0x04
212 #define INTEGRATOR_EBI_CSR2_OFFSET 0x08
213 #define INTEGRATOR_EBI_CSR3_OFFSET 0x0C
214 #define INTEGRATOR_EBI_LOCK_OFFSET 0x20
222 #define INTEGRATOR_EBI_8_BIT 0x00
223 #define INTEGRATOR_EBI_16_BIT 0x01
224 #define INTEGRATOR_EBI_32_BIT 0x02
225 #define INTEGRATOR_EBI_WRITE_ENABLE 0x04
226 #define INTEGRATOR_EBI_SYNC 0x08
227 #define INTEGRATOR_EBI_WS_2 0x00
228 #define INTEGRATOR_EBI_WS_3 0x10
229 #define INTEGRATOR_EBI_WS_4 0x20
230 #define INTEGRATOR_EBI_WS_5 0x30
231 #define INTEGRATOR_EBI_WS_6 0x40
232 #define INTEGRATOR_EBI_WS_7 0x50
233 #define INTEGRATOR_EBI_WS_8 0x60
234 #define INTEGRATOR_EBI_WS_9 0x70
235 #define INTEGRATOR_EBI_WS_10 0x80
236 #define INTEGRATOR_EBI_WS_11 0x90
237 #define INTEGRATOR_EBI_WS_12 0xA0
238 #define INTEGRATOR_EBI_WS_13 0xB0
239 #define INTEGRATOR_EBI_WS_14 0xC0
240 #define INTEGRATOR_EBI_WS_15 0xD0
241 #define INTEGRATOR_EBI_WS_16 0xE0
242 #define INTEGRATOR_EBI_WS_17 0xF0
245 #define INTEGRATOR_CT_BASE 0x13000000 /* Counter/Timers */
246 #define INTEGRATOR_IC_BASE 0x14000000 /* Interrupt Controller */
247 #define INTEGRATOR_RTC_BASE 0x15000000 /* Real Time Clock */
248 #define INTEGRATOR_UART0_BASE 0x16000000 /* UART 0 */
249 #define INTEGRATOR_UART1_BASE 0x17000000 /* UART 1 */
250 #define INTEGRATOR_KBD_BASE 0x18000000 /* Keyboard */
251 #define INTEGRATOR_MOUSE_BASE 0x19000000 /* Mouse */
256 #define INTEGRATOR_DBG_ALPHA_OFFSET 0x00
257 #define INTEGRATOR_DBG_LEDS_OFFSET 0x04
258 #define INTEGRATOR_DBG_SWITCH_OFFSET 0x08
260 #define INTEGRATOR_DBG_BASE 0x1A000000
265 #define INTEGRATOR_AP_GPIO_BASE 0x1B000000 /* GPIO */
267 #define INTEGRATOR_CP_MMC_BASE 0x1C000000 /* MMC */
268 #define INTEGRATOR_CP_AACI_BASE 0x1D000000 /* AACI */
269 #define INTEGRATOR_CP_ETH_BASE 0xC8000000 /* Ethernet */
270 #define INTEGRATOR_CP_GPIO_BASE 0xC9000000 /* GPIO */
271 #define INTEGRATOR_CP_SIC_BASE 0xCA000000 /* SIC */
272 #define INTEGRATOR_CP_CTL_BASE 0xCB000000 /* CP system control */
294 #define IRQ_STATUS 0
295 #define IRQ_RAW_STATUS 0x04
296 #define IRQ_ENABLE 0x08
297 #define IRQ_ENABLE_SET 0x08
298 #define IRQ_ENABLE_CLEAR 0x0C
300 #define INT_SOFT_SET 0x10
301 #define INT_SOFT_CLEAR 0x14
303 #define FIQ_STATUS 0x20
304 #define FIQ_RAW_STATUS 0x24
305 #define FIQ_ENABLE 0x28
306 #define FIQ_ENABLE_SET 0x28
307 #define FIQ_ENABLE_CLEAR 0x2C
313 #define GREEN_LED 0x01
314 #define YELLOW_LED 0x02
315 #define RED_LED 0x04
316 #define GREEN_LED_2 0x08
317 #define ALL_LEDS 0x0F
327 * Timer 0 runs at bus frequency
330 #define INTEGRATOR_TIMER1_BASE (INTEGRATOR_CT_BASE + 0x100)
331 #define INTEGRATOR_TIMER2_BASE (INTEGRATOR_CT_BASE + 0x200)
333 #define INTEGRATOR_CSR_BASE 0x10000000
334 #define INTEGRATOR_CSR_SIZE 0x10000000