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/linux/Documentation/dev-tools/
H A Dkfence.rst29 CONFIG_KFENCE_SAMPLE_INTERVAL=0
41 ``CONFIG_KFENCE_SAMPLE_INTERVAL``. Setting ``kfence.sample_interval=0``
87 BUG: KFENCE: out-of-bounds read in test_out_of_bounds_read+0xa6/0x234
89 Out-of-bounds read at 0xffff8c3f2e291fff (1B left of kfence-#72):
90 test_out_of_bounds_read+0xa6/0x234
91 kunit_try_run_case+0x61/0xa0
92 kunit_generic_run_threadfn_adapter+0x16/0x30
93 kthread+0x176/0x1b0
94 ret_from_fork+0x22/0x30
96 kfence-#72: 0xffff8c3f2e292000-0xffff8c3f2e29201f, size=32, cache=kmalloc-32
[all …]
/linux/drivers/phy/qualcomm/
H A Dphy-qcom-qmp-pcs-v5.h10 #define QPHY_V5_PCS_SW_RESET 0x000
11 #define QPHY_V5_PCS_PCS_STATUS1 0x014
12 #define QPHY_V5_PCS_POWER_DOWN_CONTROL 0x040
13 #define QPHY_V5_PCS_START_CONTROL 0x044
14 #define QPHY_V5_PCS_LOCK_DETECT_CONFIG1 0x0c4
15 #define QPHY_V5_PCS_LOCK_DETECT_CONFIG2 0x0c8
16 #define QPHY_V5_PCS_LOCK_DETECT_CONFIG3 0x0cc
17 #define QPHY_V5_PCS_LOCK_DETECT_CONFIG6 0x0d8
18 #define QPHY_V5_PCS_REFGEN_REQ_CONFIG1 0x0dc
19 #define QPHY_V5_PCS_G3S2_PRE_GAIN 0x170
[all …]
H A Dphy-qcom-qmp-pcs-v7.h10 #define QPHY_V7_PCS_SW_RESET 0x000
11 #define QPHY_V7_PCS_PCS_STATUS1 0x014
12 #define QPHY_V7_PCS_POWER_DOWN_CONTROL 0x040
13 #define QPHY_V7_PCS_START_CONTROL 0x044
14 #define QPHY_V7_PCS_POWER_STATE_CONFIG1 0x090
15 #define QPHY_V7_PCS_LOCK_DETECT_CONFIG1 0x0c4
16 #define QPHY_V7_PCS_LOCK_DETECT_CONFIG2 0x0c8
17 #define QPHY_V7_PCS_LOCK_DETECT_CONFIG3 0x0cc
18 #define QPHY_V7_PCS_LOCK_DETECT_CONFIG6 0x0d8
19 #define QPHY_V7_PCS_REFGEN_REQ_CONFIG1 0x0dc
[all …]
H A Dphy-qcom-qmp-pcs-v6-n4.h10 #define QPHY_V6_N4_PCS_SW_RESET 0x000
11 #define QPHY_V6_N4_PCS_PCS_STATUS1 0x014
12 #define QPHY_V6_N4_PCS_POWER_DOWN_CONTROL 0x040
13 #define QPHY_V6_N4_PCS_START_CONTROL 0x044
14 #define QPHY_V6_N4_PCS_POWER_STATE_CONFIG1 0x090
15 #define QPHY_V6_N4_PCS_LOCK_DETECT_CONFIG1 0x0c4
16 #define QPHY_V6_N4_PCS_LOCK_DETECT_CONFIG2 0x0c8
17 #define QPHY_V6_N4_PCS_LOCK_DETECT_CONFIG3 0x0cc
18 #define QPHY_V6_N4_PCS_LOCK_DETECT_CONFIG6 0x0d8
19 #define QPHY_V6_N4_PCS_REFGEN_REQ_CONFIG1 0x0dc
[all …]
H A Dphy-qcom-qmp-pcs-v8.h10 #define QPHY_V8_PCS_SW_RESET 0x000
11 #define QPHY_V8_PCS_PCS_STATUS1 0x014
12 #define QPHY_V8_PCS_POWER_DOWN_CONTROL 0x040
13 #define QPHY_V8_PCS_START_CONTROL 0x044
14 #define QPHY_V8_PCS_POWER_STATE_CONFIG1 0x090
15 #define QPHY_V8_PCS_LOCK_DETECT_CONFIG1 0x0c4
16 #define QPHY_V8_PCS_LOCK_DETECT_CONFIG2 0x0c8
17 #define QPHY_V8_PCS_LOCK_DETECT_CONFIG3 0x0cc
18 #define QPHY_V8_PCS_LOCK_DETECT_CONFIG6 0x0d8
19 #define QPHY_V8_PCS_REFGEN_REQ_CONFIG1 0x0dc
[all …]
H A Dphy-qcom-qmp-qserdes-txrx-v8.h9 #define QSERDES_V8_TX_TX_EMP_POST1_LVL 0x00c
10 #define QSERDES_V8_TX_TX_DRV_LVL 0x014
11 #define QSERDES_V8_TX_RES_CODE_LANE_TX 0x034
12 #define QSERDES_V8_TX_RES_CODE_LANE_RX 0x038
13 #define QSERDES_V8_TX_RES_CODE_LANE_OFFSET_TX 0x03c
14 #define QSERDES_V8_TX_RES_CODE_LANE_OFFSET_RX 0x040
15 #define QSERDES_V8_TX_TRANSCEIVER_BIAS_EN 0x054
16 #define QSERDES_V8_TX_HIGHZ_DRVR_EN 0x058
17 #define QSERDES_V8_TX_TX_POL_INV 0x05c
18 #define QSERDES_V8_TX_LANE_MODE_1 0x084
[all …]
H A Dphy-qcom-qmp-qserdes-txrx-v7.h9 #define QSERDES_V7_TX_CLKBUF_ENABLE 0x08
10 #define QSERDES_V7_TX_RESET_TSYNC_EN 0x1c
11 #define QSERDES_V7_TX_PRE_STALL_LDO_BOOST_EN 0x20
12 #define QSERDES_V7_TX_TX_BAND 0x24
13 #define QSERDES_V7_TX_INTERFACE_SELECT 0x2c
14 #define QSERDES_V7_TX_RES_CODE_LANE_TX 0x34
15 #define QSERDES_V7_TX_RES_CODE_LANE_RX 0x38
16 #define QSERDES_V7_TX_RES_CODE_LANE_OFFSET_TX 0x3c
17 #define QSERDES_V7_TX_RES_CODE_LANE_OFFSET_RX 0x40
18 #define QSERDES_V7_TX_PARRATE_REC_DETECT_IDLE_EN 0x60
[all …]
H A Dphy-qcom-qmp-qserdes-txrx-v5_20.h10 #define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX 0x30
11 #define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX 0x34
12 #define QSERDES_V5_20_TX_LANE_MODE_1 0x78
13 #define QSERDES_V5_20_TX_LANE_MODE_2 0x7c
14 #define QSERDES_V5_20_TX_LANE_MODE_3 0x80
15 #define QSERDES_V5_20_TX_RCV_DETECT_LVL_2 0x90
16 #define QSERDES_V5_20_TX_VMODE_CTRL1 0xb0
17 #define QSERDES_V5_20_TX_PI_QEC_CTRL 0xcc
20 #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2 0x008
21 #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3 0x00c
[all …]
/linux/drivers/media/dvb-frontends/
H A Dmxl5xx_regs.h13 #define HYDRA_INTR_STATUS_REG 0x80030008
14 #define HYDRA_INTR_MASK_REG 0x8003000C
16 #define HYDRA_CRYSTAL_SETTING 0x3FFFC5F0 /* 0 - 24 MHz & 1 - 27 MHz */
17 #define HYDRA_CRYSTAL_CAP 0x3FFFEDA4 /* 0 - 24 MHz & 1 - 27 MHz */
19 #define HYDRA_CPU_RESET_REG 0x8003003C
20 #define HYDRA_CPU_RESET_DATA 0x00000400
22 #define HYDRA_RESET_TRANSPORT_FIFO_REG 0x80030028
23 #define HYDRA_RESET_TRANSPORT_FIFO_DATA 0x00000000
25 #define HYDRA_RESET_BBAND_REG 0x80030024
26 #define HYDRA_RESET_BBAND_DATA 0x00000000
[all …]
/linux/drivers/media/platform/chips-media/coda/
H A Dcoda_regs.h14 #define CODA_REG_BIT_CODE_RUN 0x000
15 #define CODA_REG_RUN_ENABLE (1 << 0)
16 #define CODA_REG_BIT_CODE_DOWN 0x004
17 #define CODA_DOWN_ADDRESS_SET(x) (((x) & 0xffff) << 16)
18 #define CODA_DOWN_DATA_SET(x) ((x) & 0xffff)
19 #define CODA_REG_BIT_HOST_IN_REQ 0x008
20 #define CODA_REG_BIT_INT_CLEAR 0x00c
21 #define CODA_REG_BIT_INT_CLEAR_SET 0x1
22 #define CODA_REG_BIT_INT_STATUS 0x010
23 #define CODA_REG_BIT_CODE_RESET 0x014
[all …]
/linux/Documentation/locking/
H A Dlockstat.rst56 - shortest (non-0) time we ever had to wait for a lock
69 - shortest (non-0) time we ever held the lock
97 # echo 0 >/proc/sys/kernel/lock_stat
114 … &mm->mmap_sem 1 [<ffffffff811502a7>] khugepaged_scan_mm_slot+0x57/0x280
115 … &mm->mmap_sem 96 [<ffffffff815351c4>] __do_page_fault+0x1d4/0x510
116 … &mm->mmap_sem 34 [<ffffffff81113d77>] vm_mmap_pgoff+0x87/0xd0
117 … &mm->mmap_sem 17 [<ffffffff81127e71>] vm_munmap+0x41/0x80
119 … &mm->mmap_sem 1 [<ffffffff81046fda>] dup_mmap+0x2a/0x3f0
120 … &mm->mmap_sem 60 [<ffffffff81129e29>] SyS_mprotect+0xe9/0x250
121 … &mm->mmap_sem 41 [<ffffffff815351c4>] __do_page_fault+0x1d4/0x510
[all …]
/linux/Documentation/translations/it_IT/locking/
H A Dlockstat.rst118 # echo 0 >/proc/sys/kernel/lock_stat
135 … &mm->mmap_sem 1 [<ffffffff811502a7>] khugepaged_scan_mm_slot+0x57/0x280
136 … &mm->mmap_sem 96 [<ffffffff815351c4>] __do_page_fault+0x1d4/0x510
137 … &mm->mmap_sem 34 [<ffffffff81113d77>] vm_mmap_pgoff+0x87/0xd0
138 … &mm->mmap_sem 17 [<ffffffff81127e71>] vm_munmap+0x41/0x80
140 … &mm->mmap_sem 1 [<ffffffff81046fda>] dup_mmap+0x2a/0x3f0
141 … &mm->mmap_sem 60 [<ffffffff81129e29>] SyS_mprotect+0xe9/0x250
142 … &mm->mmap_sem 41 [<ffffffff815351c4>] __do_page_fault+0x1d4/0x510
143 … &mm->mmap_sem 68 [<ffffffff81113d77>] vm_mmap_pgoff+0x87/0xd0
149 … unix_table_lock 45 [<ffffffff8150ad8e>] unix_create1+0x16e/0x1b0
[all …]
/linux/drivers/clk/hisilicon/
H A Dclk-hi3670.c17 { HI3670_CLKIN_SYS, "clkin_sys", NULL, 0, 19200000, },
18 { HI3670_CLKIN_REF, "clkin_ref", NULL, 0, 32764, },
19 { HI3670_CLK_FLL_SRC, "clk_fll_src", NULL, 0, 134400000, },
20 { HI3670_CLK_PPLL0, "clk_ppll0", NULL, 0, 1660000000, },
21 { HI3670_CLK_PPLL1, "clk_ppll1", NULL, 0, 1866000000, },
22 { HI3670_CLK_PPLL2, "clk_ppll2", NULL, 0, 1920000000, },
23 { HI3670_CLK_PPLL3, "clk_ppll3", NULL, 0, 1200000000, },
24 { HI3670_CLK_PPLL4, "clk_ppll4", NULL, 0, 900000000, },
25 { HI3670_CLK_PPLL6, "clk_ppll6", NULL, 0, 393216000, },
26 { HI3670_CLK_PPLL7, "clk_ppll7", NULL, 0, 1008000000, },
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mn-pinfunc.h14 …ne MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x020 0x25C 0x000 0x0 0x0
15 …ne MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x020 0x25C 0x55C 0x1 0x3
16 …ne MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x024 0x260 0x000 0x0 0x0
17 …ne MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x024 0x260 0x56C 0x1 0x3
18 …ne MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0
19 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x000 0x1 0x0
20 …ne MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0
21 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0
22 …ne MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0
23 …ne MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0
[all …]
H A Dimx8mm-pinfunc.h14 #define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
15 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
16 #define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
17 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
18 #define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
19 #define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0…
20 #define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0…
21 #define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0…
22 #define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0…
23 #define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0…
[all …]
/linux/arch/arm/mach-s3c/
H A Dregs-gpio-memport-s3c64xx.h14 #define S3C64XX_MEM0CONSTOP S3C64XX_GPIOREG(0x1B0)
15 #define S3C64XX_MEM1CONSTOP S3C64XX_GPIOREG(0x1B4)
17 #define S3C64XX_MEM0CONSLP0 S3C64XX_GPIOREG(0x1C0)
18 #define S3C64XX_MEM0CONSLP1 S3C64XX_GPIOREG(0x1C4)
19 #define S3C64XX_MEM1CONSLP S3C64XX_GPIOREG(0x1C8)
21 #define S3C64XX_MEM0DRVCON S3C64XX_GPIOREG(0x1D0)
22 #define S3C64XX_MEM1DRVCON S3C64XX_GPIOREG(0x1D4)
/linux/drivers/tty/serial/8250/
H A D8250_fourport.c16 SERIAL8250_FOURPORT(0x1a0, 9),
17 SERIAL8250_FOURPORT(0x1a8, 9),
18 SERIAL8250_FOURPORT(0x1b0, 9),
19 SERIAL8250_FOURPORT(0x1b8, 9),
20 SERIAL8250_FOURPORT(0x2a0, 5),
21 SERIAL8250_FOURPORT(0x2a8, 5),
22 SERIAL8250_FOURPORT(0x2b0, 5),
23 SERIAL8250_FOURPORT(0x2b8, 5),
/linux/include/dt-bindings/clock/
H A Ddm816.h8 #define DM816_CLKCTRL_OFFSET 0x0
12 #define DM816_USB_OTG_HS_CLKCTRL DM816_CLKCTRL_INDEX(0x58)
15 #define DM816_UART1_CLKCTRL DM816_CLKCTRL_INDEX(0x150)
16 #define DM816_UART2_CLKCTRL DM816_CLKCTRL_INDEX(0x154)
17 #define DM816_UART3_CLKCTRL DM816_CLKCTRL_INDEX(0x158)
18 #define DM816_GPIO1_CLKCTRL DM816_CLKCTRL_INDEX(0x15c)
19 #define DM816_GPIO2_CLKCTRL DM816_CLKCTRL_INDEX(0x160)
20 #define DM816_I2C1_CLKCTRL DM816_CLKCTRL_INDEX(0x164)
21 #define DM816_I2C2_CLKCTRL DM816_CLKCTRL_INDEX(0x168)
22 #define DM816_TIMER1_CLKCTRL DM816_CLKCTRL_INDEX(0x170)
[all …]
/linux/drivers/pmdomain/renesas/
H A Dr8a77970-sysc.c16 { "always-on", 0, 0, R8A77970_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
17 { "ca53-scu", 0x140, 0, R8A77970_PD_CA53_SCU, R8A77970_PD_ALWAYS_ON,
19 { "ca53-cpu0", 0x200, 0, R8A77970_PD_CA53_CPU0, R8A77970_PD_CA53_SCU,
21 { "ca53-cpu1", 0x200, 1, R8A77970_PD_CA53_CPU1, R8A77970_PD_CA53_SCU,
23 { "a3ir", 0x180, 0, R8A77970_PD_A3IR, R8A77970_PD_ALWAYS_ON },
24 { "a2ir0", 0x400, 0, R8A77970_PD_A2IR0, R8A77970_PD_A3IR },
25 { "a2ir1", 0x400, 1, R8A77970_PD_A2IR1, R8A77970_PD_A3IR },
26 { "a2dp", 0x400, 2, R8A77970_PD_A2DP, R8A77970_PD_A3IR },
27 { "a2cn", 0x400, 3, R8A77970_PD_A2CN, R8A77970_PD_A3IR },
28 { "a2sc0", 0x400, 4, R8A77970_PD_A2SC0, R8A77970_PD_A3IR },
[all …]
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dti,iodelay.txt24 reg = <0x4844a000 0x0d1c>;
26 #size-cells = <0>;
35 0x18c A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A19_IN */
36 0x1a4 A_DELAY_PS(265) G_DELAY_PS(360) /* CFG_GPMC_A20_IN */
37 0x1b0 A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A21_IN */
38 0x1bc A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A22_IN */
39 0x1c8 A_DELAY_PS(287) G_DELAY_PS(420) /* CFG_GPMC_A23_IN */
40 0x1d4 A_DELAY_PS(144) G_DELAY_PS(240) /* CFG_GPMC_A24_IN */
41 0x1e0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_IN */
42 0x1ec A_DELAY_PS(120) G_DELAY_PS(0) /* CFG_GPMC_A26_IN */
[all …]
H A Dbrcm,cygnus-pinmux.txt30 reg = <0x0301d0c8 0x1b0>;
33 pinctrl-0 = <&i2s0_default>;
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx25-pinfunc.h16 #define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000
17 #define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000
19 #define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000
20 #define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000
21 #define MX25_PAD_A13__LCDC_CLS 0x00c 0x22C 0x000 0x07 0x000
23 #define MX25_PAD_A14__A14 0x010 0x230 0x000 0x00 0x000
24 #define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x05 0x000
25 #define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x06 0x000
26 #define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x07 0x000
28 #define MX25_PAD_A15__A15 0x014 0x234 0x000 0x00 0x000
[all …]
/linux/drivers/net/wireless/mediatek/mt76/mt7615/
H A Deeprom.h25 MT_EE_CHIP_ID = 0x000,
26 MT_EE_VERSION = 0x002,
27 MT_EE_MAC_ADDR = 0x004,
28 MT_EE_NIC_CONF_0 = 0x034,
29 MT_EE_NIC_CONF_1 = 0x036,
30 MT_EE_WIFI_CONF = 0x03e,
31 MT_EE_CALDATA_FLASH = 0x052,
32 MT_EE_TX0_2G_TARGET_POWER = 0x058,
33 MT_EE_TX0_5G_G0_TARGET_POWER = 0x070,
34 MT7663_EE_5G_RATE_POWER = 0x089,
[all …]
/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_doorbell.h100 AMDGPU_DOORBELL_KIQ = 0x000,
101 AMDGPU_DOORBELL_HIQ = 0x001,
102 AMDGPU_DOORBELL_DIQ = 0x002,
103 AMDGPU_DOORBELL_MEC_RING0 = 0x010,
104 AMDGPU_DOORBELL_MEC_RING1 = 0x011,
105 AMDGPU_DOORBELL_MEC_RING2 = 0x012,
106 AMDGPU_DOORBELL_MEC_RING3 = 0x013,
107 AMDGPU_DOORBELL_MEC_RING4 = 0x014,
108 AMDGPU_DOORBELL_MEC_RING5 = 0x015,
109 AMDGPU_DOORBELL_MEC_RING6 = 0x016,
[all …]
/linux/drivers/ufs/host/
H A Dufs-rockchip.h11 #define SEL_TX_LANE0 0x0
12 #define SEL_TX_LANE1 0x1
13 #define SEL_TX_LANE2 0x2
14 #define SEL_TX_LANE3 0x3
15 #define SEL_RX_LANE0 0x4
16 #define SEL_RX_LANE1 0x5
17 #define SEL_RX_LANE2 0x6
18 #define SEL_RX_LANE3 0x7
20 #define VND_TX_CLK_PRD 0xAA
21 #define VND_TX_CLK_PRD_EN 0xA9
[all …]

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