xref: /linux/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v8.h (revision 8582976acc8504cec53a7b6fed493435eba8437f)
1*c4364048SWesley Cheng /* SPDX-License-Identifier: GPL-2.0 */
2*c4364048SWesley Cheng /*
3*c4364048SWesley Cheng  * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
4*c4364048SWesley Cheng  */
5*c4364048SWesley Cheng 
6*c4364048SWesley Cheng #ifndef QCOM_PHY_QMP_QSERDES_TXRX_V8_H_
7*c4364048SWesley Cheng #define QCOM_PHY_QMP_QSERDES_TXRX_V8_H_
8*c4364048SWesley Cheng 
9*c4364048SWesley Cheng #define QSERDES_V8_TX_TX_EMP_POST1_LVL			0x00c
10*c4364048SWesley Cheng #define QSERDES_V8_TX_TX_DRV_LVL			0x014
11*c4364048SWesley Cheng #define QSERDES_V8_TX_RES_CODE_LANE_TX			0x034
12*c4364048SWesley Cheng #define QSERDES_V8_TX_RES_CODE_LANE_RX			0x038
13*c4364048SWesley Cheng #define QSERDES_V8_TX_RES_CODE_LANE_OFFSET_TX		0x03c
14*c4364048SWesley Cheng #define QSERDES_V8_TX_RES_CODE_LANE_OFFSET_RX		0x040
15*c4364048SWesley Cheng #define QSERDES_V8_TX_TRANSCEIVER_BIAS_EN		0x054
16*c4364048SWesley Cheng #define QSERDES_V8_TX_HIGHZ_DRVR_EN			0x058
17*c4364048SWesley Cheng #define QSERDES_V8_TX_TX_POL_INV			0x05c
18*c4364048SWesley Cheng #define QSERDES_V8_TX_LANE_MODE_1			0x084
19*c4364048SWesley Cheng #define QSERDES_V8_TX_LANE_MODE_2			0x088
20*c4364048SWesley Cheng #define QSERDES_V8_TX_LANE_MODE_3			0x08c
21*c4364048SWesley Cheng #define QSERDES_V8_TX_LANE_MODE_4			0x090
22*c4364048SWesley Cheng #define QSERDES_V8_TX_LANE_MODE_5			0x094
23*c4364048SWesley Cheng #define QSERDES_V8_TX_RCV_DETECT_LVL_2			0x0a4
24*c4364048SWesley Cheng #define QSERDES_V8_TX_PI_QEC_CTRL			0x0e4
25*c4364048SWesley Cheng 
26*c4364048SWesley Cheng #define QSERDES_V8_RX_UCDR_FO_GAIN			0x008
27*c4364048SWesley Cheng #define QSERDES_V8_RX_UCDR_SO_GAIN			0x014
28*c4364048SWesley Cheng #define QSERDES_V8_RX_UCDR_SVS_FO_GAIN			0x020
29*c4364048SWesley Cheng #define QSERDES_V8_RX_UCDR_FASTLOCK_FO_GAIN		0x030
30*c4364048SWesley Cheng #define QSERDES_V8_RX_UCDR_SO_SATURATION_AND_ENABLE	0x034
31*c4364048SWesley Cheng #define QSERDES_V8_RX_UCDR_FASTLOCK_COUNT_LOW		0x03c
32*c4364048SWesley Cheng #define QSERDES_V8_RX_UCDR_FASTLOCK_COUNT_HIGH		0x040
33*c4364048SWesley Cheng #define QSERDES_V8_RX_UCDR_PI_CONTROLS			0x044
34*c4364048SWesley Cheng #define QSERDES_V8_RX_UCDR_SB2_THRESH1			0x04c
35*c4364048SWesley Cheng #define QSERDES_V8_RX_UCDR_SB2_THRESH2			0x050
36*c4364048SWesley Cheng #define QSERDES_V8_RX_UCDR_SB2_GAIN1			0x054
37*c4364048SWesley Cheng #define QSERDES_V8_RX_UCDR_SB2_GAIN2			0x058
38*c4364048SWesley Cheng #define QSERDES_V8_RX_AUX_DATA_TCOARSE_TFINE		0x060
39*c4364048SWesley Cheng #define QSERDES_V8_RX_VGA_CAL_CNTRL1			0x0d4
40*c4364048SWesley Cheng #define QSERDES_V8_RX_VGA_CAL_CNTRL2			0x0d8
41*c4364048SWesley Cheng #define QSERDES_V8_RX_GM_CAL				0x0dc
42*c4364048SWesley Cheng #define QSERDES_V8_RX_RX_EQU_ADAPTOR_CNTRL2		0x0ec
43*c4364048SWesley Cheng #define QSERDES_V8_RX_RX_EQU_ADAPTOR_CNTRL3		0x0f0
44*c4364048SWesley Cheng #define QSERDES_V8_RX_RX_EQU_ADAPTOR_CNTRL4		0x0f4
45*c4364048SWesley Cheng #define QSERDES_V8_RX_RX_IDAC_TSETTLE_LOW		0x0f8
46*c4364048SWesley Cheng #define QSERDES_V8_RX_RX_IDAC_TSETTLE_HIGH		0x0fc
47*c4364048SWesley Cheng #define QSERDES_V8_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1	0x110
48*c4364048SWesley Cheng #define QSERDES_V8_RX_SIGDET_ENABLES			0x118
49*c4364048SWesley Cheng #define QSERDES_V8_RX_SIGDET_CNTRL			0x11c
50*c4364048SWesley Cheng #define QSERDES_V8_RX_SIGDET_DEGLITCH_CNTRL		0x124
51*c4364048SWesley Cheng #define QSERDES_V8_RX_RX_MODE_00_LOW			0x15c
52*c4364048SWesley Cheng #define QSERDES_V8_RX_RX_MODE_00_HIGH			0x160
53*c4364048SWesley Cheng #define QSERDES_V8_RX_RX_MODE_00_HIGH2			0x164
54*c4364048SWesley Cheng #define QSERDES_V8_RX_RX_MODE_00_HIGH3			0x168
55*c4364048SWesley Cheng #define QSERDES_V8_RX_RX_MODE_00_HIGH4			0x16c
56*c4364048SWesley Cheng #define QSERDES_V8_RX_RX_MODE_01_LOW			0x170
57*c4364048SWesley Cheng #define QSERDES_V8_RX_RX_MODE_01_HIGH			0x174
58*c4364048SWesley Cheng #define QSERDES_V8_RX_RX_MODE_01_HIGH2			0x178
59*c4364048SWesley Cheng #define QSERDES_V8_RX_RX_MODE_01_HIGH3			0x17c
60*c4364048SWesley Cheng #define QSERDES_V8_RX_RX_MODE_01_HIGH4			0x180
61*c4364048SWesley Cheng #define QSERDES_V8_RX_DFE_EN_TIMER			0x1a0
62*c4364048SWesley Cheng #define QSERDES_V8_RX_DFE_CTLE_POST_CAL_OFFSET		0x1a4
63*c4364048SWesley Cheng #define QSERDES_V8_RX_DCC_CTRL1				0x1a8
64*c4364048SWesley Cheng #define QSERDES_V8_RX_VTH_CODE				0x1b0
65*c4364048SWesley Cheng #define QSERDES_V8_RX_SIGDET_CAL_CTRL1			0x1e4
66*c4364048SWesley Cheng #define QSERDES_V8_RX_SIGDET_CAL_TRIM			0x1f8
67*c4364048SWesley Cheng 
68*c4364048SWesley Cheng #endif
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