1*1c3c4df0SMichael Walle// SPDX-License-Identifier: GPL-2.0-only OR MIT 2*1c3c4df0SMichael Walle/* 3*1c3c4df0SMichael Walle * SMARC GPIOs. 4*1c3c4df0SMichael Walle * 5*1c3c4df0SMichael Walle * Copyright (c) 2025 Kontron Europe GmbH 6*1c3c4df0SMichael Walle */ 7*1c3c4df0SMichael Walle 8*1c3c4df0SMichael Walle/dts-v1/; 9*1c3c4df0SMichael Walle/plugin/; 10*1c3c4df0SMichael Walle 11*1c3c4df0SMichael Walle#include <dt-bindings/gpio/gpio.h> 12*1c3c4df0SMichael Walle#include "k3-pinctrl.h" 13*1c3c4df0SMichael Walle 14*1c3c4df0SMichael Walle&main_gpio0 { 15*1c3c4df0SMichael Walle pinctrl-names = "default"; 16*1c3c4df0SMichael Walle pinctrl-0 = <&main_gpio0_pins_default>; 17*1c3c4df0SMichael Walle}; 18*1c3c4df0SMichael Walle 19*1c3c4df0SMichael Walle&main_gpio1 { 20*1c3c4df0SMichael Walle pinctrl-names = "default"; 21*1c3c4df0SMichael Walle pinctrl-0 = <&main_gpio1_pins_default>; 22*1c3c4df0SMichael Walle}; 23*1c3c4df0SMichael Walle 24*1c3c4df0SMichael Walle&main_pmx0 { 25*1c3c4df0SMichael Walle main_gpio0_pins_default: main-gpio0-default-pins { 26*1c3c4df0SMichael Walle pinctrl-single,pins = < 27*1c3c4df0SMichael Walle J722S_IOPAD(0x0d0, PIN_INPUT, 7) /* (Y26) VOUT0_DATA6.GPIO0_51 */ 28*1c3c4df0SMichael Walle J722S_IOPAD(0x0d4, PIN_INPUT, 7) /* (Y27) VOUT0_DATA7.GPIO0_52 */ 29*1c3c4df0SMichael Walle J722S_IOPAD(0x118, PIN_INPUT, 7) /* (H26) MMC2_CLK.GPIO0_69 */ 30*1c3c4df0SMichael Walle J722S_IOPAD(0x120, PIN_INPUT, 7) /* (F27) MMC2_CMD.GPIO0_70 */ 31*1c3c4df0SMichael Walle >; 32*1c3c4df0SMichael Walle }; 33*1c3c4df0SMichael Walle 34*1c3c4df0SMichael Walle main_gpio1_pins_default: main-gpio1-default-pins { 35*1c3c4df0SMichael Walle pinctrl-single,pins = < 36*1c3c4df0SMichael Walle J722S_IOPAD(0x194, PIN_INPUT, 7) /* (A25) MCASP0_AXR3.GPIO1_7 */ 37*1c3c4df0SMichael Walle J722S_IOPAD(0x198, PIN_INPUT, 7) /* (A26) MCASP0_AXR2.GPIO1_8 */ 38*1c3c4df0SMichael Walle J722S_IOPAD(0x1ac, PIN_INPUT, 7) /* (C27) MCASP0_AFSR.GPIO1_13 */ 39*1c3c4df0SMichael Walle J722S_IOPAD(0x1b0, PIN_INPUT, 7) /* (F24) MCASP0_ACLKR.GPIO1_14 */ 40*1c3c4df0SMichael Walle J722S_IOPAD(0x1d8, PIN_INPUT, 7) /* (D22) MCAN0_TX.GPIO1_24 */ 41*1c3c4df0SMichael Walle J722S_IOPAD(0x1dc, PIN_INPUT, 7) /* (C22) MCAN0_RX.GPIO1_25 */ 42*1c3c4df0SMichael Walle J722S_IOPAD(0x1e8, PIN_INPUT, 7) /* (C24) I2C1_SCL.GPIO1_28 */ 43*1c3c4df0SMichael Walle J722S_IOPAD(0x1ec, PIN_INPUT, 7) /* (A22) I2C1_SDA.GPIO1_29 */ 44*1c3c4df0SMichael Walle >; 45*1c3c4df0SMichael Walle }; 46*1c3c4df0SMichael Walle}; 47*1c3c4df0SMichael Walle 48*1c3c4df0SMichael Walle&mcu_gpio0 { 49*1c3c4df0SMichael Walle pinctrl-names = "default"; 50*1c3c4df0SMichael Walle pinctrl-0 = <&mcu_gpio0_pins_default>; 51*1c3c4df0SMichael Walle}; 52*1c3c4df0SMichael Walle 53*1c3c4df0SMichael Walle&mcu_pmx0 { 54*1c3c4df0SMichael Walle mcu_gpio0_pins_default: mcu-gpio0-default-pins { 55*1c3c4df0SMichael Walle pinctrl-single,pins = < 56*1c3c4df0SMichael Walle J722S_IOPAD(0x02c, PIN_INPUT, 7) /* (C4) WKUP_UART0_CTSn.MCU_GPIO0_11 */ 57*1c3c4df0SMichael Walle J722S_IOPAD(0x084, PIN_INPUT, 7) /* (F12) WKUP_CLKOUT0.MCU_GPIO0_23 */ 58*1c3c4df0SMichael Walle >; 59*1c3c4df0SMichael Walle }; 60*1c3c4df0SMichael Walle 61*1c3c4df0SMichael Walle}; 62