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/freebsd/sys/powerpc/powermac/
H A Dviareg.h32 #define vBufB 0x0000 /* register B */
33 #define vDirB 0x0400 /* data direction register */
34 #define vDirA 0x0600 /* data direction register */
35 #define vT1C 0x0800 /* Timer 1 counter Lo */
36 #define vT1CH 0x0a00 /* Timer 1 counter Hi */
37 #define vSR 0x1400 /* shift register */
38 #define vACR 0x1600 /* aux control register */
39 #define vPCR 0x1800 /* peripheral control register */
40 #define vIFR 0x1a00 /* interrupt flag register */
41 #define vIER 0x1c00 /* interrupt enable register */
[all …]
/freebsd/sys/dev/sge/
H A Dif_sge.c105 { 0, 0, NULL }
174 DRIVER_MODULE(sge, pci, sge_driver, 0, 0);
175 DRIVER_MODULE(miibus, sge, miibus_driver, 0, 0);
198 if (error != 0) in sge_dma_map_addr()
218 for (i = 0; i < SGE_TIMEOUT; i++) { in sge_read_eeprom()
220 if ((val & EI_REQ) == 0) in sge_read_eeprom()
226 "EEPROM read timeout : 0x%08x\n", val); in sge_read_eeprom()
227 return (0xffff); in sge_read_eeprom()
240 if (val == 0xffff || val == 0) { in sge_get_mac_addr_eeprom()
242 "invalid EEPROM signature : 0x%04x\n", val); in sge_get_mac_addr_eeprom()
[all …]
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Ddra76x.dtsi14 ranges = <0x0 0x42c00000 0x2000>;
17 reg = <0x42c01900 0x4>,
18 <0x42c01904 0x4>,
19 <0x42c01908 0x4>;
24 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_ADC_CLKCTRL 0>;
29 reg = <0x1a00 0x4000>, <0x0 0x18FC>;
37 bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>;
45 target-module@1b0000 { /* 0x489b0000, ap 25 34.0 */
47 reg = <0x1b0000 0x4>,
48 <0x1b0010 0x4>;
[all …]
H A Domap44xx-clocks.dtsi9 #clock-cells = <0>;
16 #clock-cells = <0>;
23 #clock-cells = <0>;
28 reg = <0x0108>;
32 #clock-cells = <0>;
39 #clock-cells = <0>;
46 #clock-cells = <0>;
53 #clock-cells = <0>;
58 reg = <0x0108>;
62 #clock-cells = <0>;
[all …]
H A Domap5.dtsi45 #size-cells = <0>;
47 cpu0: cpu@0 {
50 reg = <0x0>;
69 reg = <0x1>;
115 reg = <0 0x40300000 0 0x20000>; /* 128k */
122 reg = <0 0x48211000 0 0x1000>,
123 <0 0x48212000 0 0x2000>,
124 <0 0x48214000 0 0x2000>,
125 <0 0x48216000 0 0x2000>;
133 reg = <0 0x48281000 0 0x1000>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dphy-mtk-tphy.txt5 controllers on MediaTek SoCs, such as, USB2.0, USB3.0, PCIe, and SATA.
23 the child's base address to 0, the physical address
72 reg = <0 0x11290000 0 0x800>;
78 reg = <0 0x11290800 0 0x100>;
85 reg = <0 0x11290800 0 0x700>;
92 reg = <0 0x11291000 0 0x100>;
113 phy-names = "usb2-0", "usb3-0";
122 shared 0x0000 SPLLC
123 0x0100 FMREG
124 u2 port0 0x0800 U2PHY_COM
[all …]
H A Dmediatek,tphy.yaml15 controllers on MediaTek SoCs, includes USB2.0, USB3.0, PCIe and SATA.
22 shared 0x0000 SPLLC
23 0x0100 FMREG
24 u2 port0 0x0800 U2PHY_COM
25 u3 port0 0x0900 U3PHYD
26 0x0a00 U3PHYD_BANK2
27 0x0b00 U3PHYA
28 0x0c00 U3PHYA_DA
29 u2 port1 0x1000 U2PHY_COM
30 u3 port1 0x1100 U3PHYD
[all …]
/freebsd/sys/dev/usb/wlan/
H A Dif_rumreg.h25 #define RT2573_IFACE_INDEX 0
27 #define RT2573_MCU_CNTL 0x01
28 #define RT2573_WRITE_MAC 0x02
29 #define RT2573_READ_MAC 0x03
30 #define RT2573_WRITE_MULTI_MAC 0x06
31 #define RT2573_READ_MULTI_MAC 0x07
32 #define RT2573_READ_EEPROM 0x09
33 #define RT2573_WRITE_LED 0x0a
38 #define RT2573_AIFSN_CSR 0x0400
39 #define RT2573_CWMIN_CSR 0x0404
[all …]
/freebsd/sys/contrib/device-tree/src/loongarch/
H A Dloongson-2k2000.dtsi17 #size-cells = <0>;
22 reg = <0x0>;
29 reg = <0x1>;
36 #clock-cells = <0>;
51 thermal-sensors = <&tsensor 0>;
71 ranges = <0x0 0x10000000 0x0 0x10000000 0x0 0x10000000>,
72 <0x0 0x02000000 0x0 0x02000000 0x0 0x02000000>,
73 <0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>,
74 <0xfe 0x0 0xfe 0x0 0x0 0x40000000>;
82 ranges = <1 0x0 0x0 0x18400000 0x4000>;
[all …]
/freebsd/sys/contrib/dev/rtw88/
H A Drtw8822c.h11 u8 res0[0x30]; /* 0x120 */
12 u8 vid[2]; /* 0x150 */
15 u8 mac_addr[ETH_ALEN]; /* 0x157 */
16 u8 res2[0x3d];
20 u8 res0[0x4a]; /* 0x120 */
21 u8 mac_addr[ETH_ALEN]; /* 0x16a */
25 u8 mac_addr[ETH_ALEN]; /* 0x120 */
33 u8 ltr_cap; /* 0x133 */
38 u8 res0:2; /* 0x144 */
62 u8 res0[0x0e];
[all …]
H A Ddebug.c84 return 0; in rtw_debugfs_close()
122 seq_printf(m, "reg 0x%03x: 0x%02x\n", addr, val); in rtw_debugfs_get_read_reg()
126 seq_printf(m, "reg 0x%03x: 0x%04x\n", addr, val); in rtw_debugfs_get_read_reg()
130 seq_printf(m, "reg 0x%03x: 0x%08x\n", addr, val); in rtw_debugfs_get_read_reg()
133 return 0; in rtw_debugfs_get_read_reg()
151 seq_printf(m, "rf_read path:%d addr:0x%08x mask:0x%08x val=0x%08x\n", in rtw_debugfs_get_rf_read()
154 return 0; in rtw_debugfs_get_rf_read()
166 return 0; in rtw_debugfs_get_fix_rate()
170 return 0; in rtw_debugfs_get_fix_rate()
179 memset(tmp, 0, size); in rtw_debugfs_copy_from_user()
[all …]
H A Drtw8822c.c21 #define IQK_DONE_8822C 0xaa
56 efuse->country_code[0] = map->country_code[0]; in rtw8822c_read_efuse()
59 efuse->regd = map->rf_board_option & 0x7; in rtw8822c_read_efuse()
64 efuse->power_track_type = (map->tx_pwr_calibrate_rate >> 4) & 0xf; in rtw8822c_read_efuse()
66 for (i = 0; i < 4; i++) in rtw8822c_read_efuse()
84 return 0; in rtw8822c_read_efuse()
114 u32 rf_addr[DACK_RF_8822C] = {0x8f}; in rtw8822c_dac_backup_reg()
115 u32 addrs[DACK_REG_8822C] = {0x180c, 0x181 in rtw8822c_dac_backup_reg()
[all...]
/freebsd/sys/arm/mv/
H A Dmvwin.h45 * SoC Integrated devices: 0xF1000000, 16 MB (VA == PA)
49 #define MV_PHYS_BASE 0xF1000000
53 #define MV_CESA_SRAM_BASE 0xF1100000
56 * External devices: 0x80000000, 1 GB (VA == PA)
70 #define MV_PCI_MEM_PHYS_BASE 0x80000000
75 #define MV_PCI_IO_PHYS_BASE 0xBF000000
79 #define MV_PCI_VA_MEM_BASE 0
80 #define MV_PCI_VA_IO_BASE 0
85 #define MV_DEV_BOOT_BASE 0xF9300000
88 #define MV_DEV_CS0_BASE 0xF9400000
[all …]
H A Dmv_pci.c81 #define debugf(fmt, args...) do { printf(fmt,##args); } while (0)
100 #define PCI_SPACE_LEN 0x00400000
107 printf(" base_pci = 0x%08lx\n", range->base_pci); in mv_pci_range_dump()
108 printf(" base_par = 0x%08lx\n", range->base_parent); in mv_pci_range_dump()
109 printf(" len = 0x%08lx\n", range->len); in mv_pci_range_dump()
128 if ((fdt_addrsize_cells(node, &addr_cells, &size_cells)) != 0) in mv_pci_ranges_decode()
141 if (OF_getprop(node, "ranges", ranges, sizeof(ranges)) <= 0) in mv_pci_ranges_decode()
156 rangesptr = &ranges[0]; in mv_pci_ranges_decode()
157 offset_cells = 0; in mv_pci_ranges_decode()
158 for (i = 0; i < tuples; i++) { in mv_pci_ranges_decode()
[all …]
/freebsd/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dscorpion_reg_map.h77 volatile char pad__0[0x8]; /* 0x0 - 0x8 */
78 volatile u_int32_t MAC_DMA_CR; /* 0x8 - 0xc */
79 volatile char pad__1[0x8]; /* 0xc - 0x14 */
80 volatile u_int32_t MAC_DMA_CFG; /* 0x14 - 0x18 */
81 volatile u_int32_t MAC_DMA_RXBUFPTR_THRESH; /* 0x18 - 0x1c */
82 volatile u_int32_t MAC_DMA_TXDPPTR_THRESH; /* 0x1c - 0x20 */
83 volatile u_int32_t MAC_DMA_MIRT; /* 0x20 - 0x24 */
84 volatile u_int32_t MAC_DMA_GLOBAL_IER; /* 0x24 - 0x28 */
85 volatile u_int32_t MAC_DMA_TIMT; /* 0x28 - 0x2c */
86 volatile u_int32_t MAC_DMA_RIMT; /* 0x2c - 0x30 */
[all …]
/freebsd/sys/dev/bwi/
H A Dbwiphy.c103 #define BWI_PHYTBL_WRSSI 0x1000
104 #define BWI_PHYTBL_NOISE_SCALE 0x1400
105 #define BWI_PHYTBL_NOISE 0x1800
106 #define BWI_PHYTBL_ROTOR 0x2000
107 #define BWI_PHYTBL_DELAY 0x2400
108 #define BWI_PHYTBL_RSSI 0x4000
109 #define BWI_PHYTBL_SIGMA_SQ 0x5000
110 #define BWI_PHYTBL_WRSSI_REV1 0x5400
111 #define BWI_PHYTBL_FREQ 0x5800
187 for (i = 0; i < nitems(bwi_sup_bphy); ++i) { in bwi_phy_attach()
[all …]
/freebsd/sys/contrib/alpine-hal/
H A Dal_hal_nb_regs.h60 /* [0x0] */
62 /* [0x4] */
64 /* [0x8] Force init reset. */
66 /* [0xc] Force init reset per DECEI mode. */
68 /* [0x10] */
70 /* [0x14] */
72 /* [0x18] */
74 /* [0x1c] */
76 /* [0x20] */
78 /* [0x24] */
[all …]
/freebsd/share/i18n/csmapper/CNS/
H A DUCS@SIP%CNS11643-4.src5 SRC_ZONE 0x0057 - 0xFA1C
7 DST_INVALID 0xFFFF
13 # Unicode version: 5.0.0
47 0x0057 = 0x4F7C
48 0x0065 = 0x2156
49 0x0086 = 0x2121
50 0x00A2 = 0x2226
51 0x00A3 = 0x2225
52 0x00F1 = 0x2624
53 0x010E = 0x2128
[all …]
H A DCNS11643-4%UCS@SIP.src5 SRC_ZONE 0x21-0x7E / 0x21-0x7E / 8
7 DST_ILSEQ 0xFFFE
13 # Unicode version: 5.0.0
47 0x2121 = 0x0086
48 0x2125 = 0x1FE8
49 0x2128 = 0x010E
50 0x2129 = 0x0627
51 0x212D = 0x053C
52 0x212E = 0x0675
53 0x212F = 0xF828
[all …]
/freebsd/sys/dev/bwn/
H A Dif_bwn_phy_g.c143 if (mac->mac_phy.hwpctl == 0 || mac->mac_phy.use_hwpctl == NULL) in bwn_has_hwpctl()
144 return (0); in bwn_has_hwpctl()
169 } while(0) in bwn_phy_g_attach()
180 pg->pg_flags = 0; in bwn_phy_g_attach()
181 if (pab0 == 0 || pab1 == 0 || pab2 == 0 || pab0 == -1 || pab1 == -1 || in bwn_phy_g_attach()
185 return (0); in bwn_phy_g_attach()
188 pg->pg_idletssi = (bg == 0 || bg == -1) ? 62 : bg; in bwn_phy_g_attach()
194 for (i = 0; i < 64; i++) { in bwn_phy_g_attach()
196 int8_t j = 0; in bwn_phy_g_attach()
221 return (0); in bwn_phy_g_attach()
[all …]
/freebsd/sys/dev/usb/
H A Dusbdevs50 * #define USB_VENDOR_VNDR 0x????
51 * #define USB_PRODUCT_VNDR_PRDCT 0x????
57 vendor UNKNOWN1 0x0053 Unknown vendor
58 vendor UNKNOWN2 0x0105 Unknown vendor
59 vendor EGALAX2 0x0123 eGalax, Inc.
60 vendor CHIPSBANK 0x0204 Chipsbank Microelectronics Co.
61 vendor HUMAX 0x02ad HUMAX
62 vendor QUAN 0x01e1 Quan
63 vendor LTS 0x0386 LTS
64 vendor BWCT 0x03da Bernd Walter Computer Technology
[all …]
/freebsd/sys/dev/sfxge/common/
H A Defx_regs_mcdi.h55 #define MC_SMEM_P0_DOORBELL_OFST 0x000
56 #define MC_SMEM_P1_DOORBELL_OFST 0x004
58 #define MC_SMEM_P0_PDU_OFST 0x008
59 #define MC_SMEM_P1_PDU_OFST 0x108
60 #define MC_SMEM_PDU_LEN 0x100
61 #define MC_SMEM_P0_PTP_TIME_OFST 0x7f0
62 #define MC_SMEM_P0_STATUS_OFST 0x7f8
63 #define MC_SMEM_P1_STATUS_OFST 0x7fc
67 #define MC_STATUS_DWORD_REBOOT (0xb007b007)
68 #define MC_STATUS_DWORD_ASSERT (0xdeaddead)
[all …]
/freebsd/tools/test/iconv/ref/
H A DUTF-16BE-rev1 0x00 = 0x0000
2 0x01 = 0x0100
3 0x02 = 0x0200
4 0x03 = 0x0300
5 0x04 = 0x0400
6 0x05 = 0x0500
7 0x06 = 0x0600
8 0x07 = 0x0700
9 0x08 = 0x0800
10 0x09 = 0x0900
[all …]
H A DUTF-16LE-rev1 0x00 = 0x0000
2 0x01 = 0x0001
3 0x02 = 0x0002
4 0x03 = 0x0003
5 0x04 = 0x0004
6 0x05 = 0x0005
7 0x06 = 0x0006
8 0x07 = 0x0007
9 0x08 = 0x0008
10 0x09 = 0x0009
[all …]
/freebsd/share/i18n/csmapper/GB/
H A DGB18030%UCS@BMP.src30 SRC_ZONE 0x81-0x84 / 0x30-0x39 / 0x81-0xFE / 0x30-0x39 / 8
32 DST_ILSEQ 0xFFFE
71 # for (i = 0; i < ncharset; ++i) {
74 # charsets[i], charsets[i + off], 0, &norm);
75 # if (ret != 0)
86 # for (i = 0; i < ncharset; ++i)
96 # for (i = 0; i < ncharset; i += 2) {
98 # if (ret == 0) {
101 # if (ret == 0 && tmp == src)
105 # return 0;
[all …]

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