Lines Matching +full:0 +full:x1a00
105 { 0, 0, NULL }
174 DRIVER_MODULE(sge, pci, sge_driver, 0, 0);
175 DRIVER_MODULE(miibus, sge, miibus_driver, 0, 0);
198 if (error != 0) in sge_dma_map_addr()
218 for (i = 0; i < SGE_TIMEOUT; i++) { in sge_read_eeprom()
220 if ((val & EI_REQ) == 0) in sge_read_eeprom()
226 "EEPROM read timeout : 0x%08x\n", val); in sge_read_eeprom()
227 return (0xffff); in sge_read_eeprom()
240 if (val == 0xffff || val == 0) { in sge_get_mac_addr_eeprom()
242 "invalid EEPROM signature : 0x%04x\n", val); in sge_get_mac_addr_eeprom()
246 for (i = 0; i < ETHER_ADDR_LEN; i += 2) { in sge_get_mac_addr_eeprom()
248 dest[i + 0] = (uint8_t)val; in sge_get_mac_addr_eeprom()
252 if ((sge_read_eeprom(sc, EEPROMInfo) & 0x80) != 0) in sge_get_mac_addr_eeprom()
254 return (0); in sge_get_mac_addr_eeprom()
272 { SIS_VENDORID, 0x0965 }, in sge_get_mac_addr_apc()
273 { SIS_VENDORID, 0x0966 }, in sge_get_mac_addr_apc()
274 { SIS_VENDORID, 0x0968 } in sge_get_mac_addr_apc()
280 for (busnum = 0; busnum < devclass_get_maxunit(pci); busnum++) { in sge_get_mac_addr_apc()
284 if (device_get_children(bus, &kids, &numkids) != 0) in sge_get_mac_addr_apc()
286 for (i = 0; i < numkids; i++) { in sge_get_mac_addr_apc()
291 for (j = 0; j < nitems(apc_tbls); j++) { in sge_get_mac_addr_apc()
306 /* Enable port 0x78 and 0x79 to access APC registers. */ in sge_get_mac_addr_apc()
307 reg = pci_read_config(dev, 0x48, 1); in sge_get_mac_addr_apc()
308 pci_write_config(dev, 0x48, reg & ~0x02, 1); in sge_get_mac_addr_apc()
310 pci_read_config(dev, 0x48, 1); in sge_get_mac_addr_apc()
312 for (i = 0; i < ETHER_ADDR_LEN; i++) { in sge_get_mac_addr_apc()
313 outb(0x78, 0x09 + i); in sge_get_mac_addr_apc()
314 dest[i] = inb(0x79); in sge_get_mac_addr_apc()
316 outb(0x78, 0x12); in sge_get_mac_addr_apc()
317 if ((inb(0x79) & 0x80) != 0) in sge_get_mac_addr_apc()
320 pci_write_config(dev, 0x48, reg, 1); in sge_get_mac_addr_apc()
322 return (0); in sge_get_mac_addr_apc()
339 for (i = 0; i < SGE_TIMEOUT; i++) { in sge_miibus_readreg()
341 if ((val & GMI_REQ) == 0) in sge_miibus_readreg()
347 return (0); in sge_miibus_readreg()
364 for (i = 0; i < SGE_TIMEOUT; i++) { in sge_miibus_writereg()
366 if ((val & GMI_REQ) == 0) in sge_miibus_writereg()
372 return (0); in sge_miibus_writereg()
387 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) in sge_miibus_statchg()
389 speed = 0; in sge_miibus_statchg()
403 if ((sc->sge_flags & SGE_FLAG_FASTETHER) == 0) { in sge_miibus_statchg()
412 if ((sc->sge_flags & SGE_FLAG_LINK) == 0) in sge_miibus_statchg()
416 ctl &= ~(0x0f000000 | SC_FDX | SC_SPEED_MASK); in sge_miibus_statchg()
418 ctl |= 0x07000000; in sge_miibus_statchg()
421 ctl |= 0x04000000; in sge_miibus_statchg()
425 if ((sc->sge_flags & SGE_FLAG_GMII) != 0) in sge_miibus_statchg()
426 ctl |= 0x03000000; in sge_miibus_statchg()
429 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { in sge_miibus_statchg()
435 if ((sc->sge_flags & SGE_FLAG_RGMII) != 0) { in sge_miibus_statchg()
436 CSR_WRITE_4(sc, RGMIIDelay, 0x0441); in sge_miibus_statchg()
437 CSR_WRITE_4(sc, RGMIIDelay, 0x0440); in sge_miibus_statchg()
447 hashes[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); in sge_hash_maddr()
465 if ((if_getflags(ifp) & IFF_BROADCAST) != 0) in sge_rxfilter()
467 if ((if_getflags(ifp) & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { in sge_rxfilter()
468 if ((if_getflags(ifp) & IFF_PROMISC) != 0) in sge_rxfilter()
471 hashes[0] = 0xFFFFFFFF; in sge_rxfilter()
472 hashes[1] = 0xFFFFFFFF; in sge_rxfilter()
475 hashes[0] = hashes[1] = 0; in sge_rxfilter()
480 CSR_WRITE_4(sc, RxHashTable, hashes[0]); in sge_rxfilter()
493 if ((if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) == 0) in sge_setvlan()
496 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) in sge_setvlan()
507 CSR_WRITE_4(sc, IntrMask, 0); in sge_reset()
508 CSR_WRITE_4(sc, IntrStatus, 0xffffffff); in sge_reset()
511 CSR_WRITE_4(sc, IntrControl, 0x8000); in sge_reset()
514 CSR_WRITE_4(sc, IntrControl, 0); in sge_reset()
516 CSR_WRITE_4(sc, TX_CTL, 0x1a00); in sge_reset()
517 CSR_WRITE_4(sc, RX_CTL, 0x1a00); in sge_reset()
519 CSR_WRITE_4(sc, IntrMask, 0); in sge_reset()
520 CSR_WRITE_4(sc, IntrStatus, 0xffffffff); in sge_reset()
522 CSR_WRITE_4(sc, GMIIControl, 0); in sge_reset()
557 int error = 0, rid; in sge_attach()
564 callout_init_mtx(&sc->sge_stat_ch, &sc->sge_mtx, 0); in sge_attach()
572 sc->sge_res_id = PCIR_BAR(0); in sge_attach()
582 rid = 0; in sge_attach()
597 if ((pci_read_config(dev, 0x73, 1) & 0x01) != 0) in sge_attach()
602 if ((error = sge_dma_alloc(sc)) != 0) in sge_attach()
621 sge_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0); in sge_attach()
622 if (error != 0) { in sge_attach()
683 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sge_irq); in sge_detach()
692 return (0); in sge_detach()
708 return (0); in sge_shutdown()
720 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) in sge_suspend()
723 return (0); in sge_suspend()
735 if ((if_getflags(ifp) & IFF_UP) != 0) in sge_resume()
738 return (0); in sge_resume()
753 1, 0, /* alignment, boundary */ in sge_dma_alloc()
760 0, /* flags */ in sge_dma_alloc()
764 if (error != 0) { in sge_dma_alloc()
772 SGE_DESC_ALIGN, 0, /* alignment, boundary */ in sge_dma_alloc()
778 0, /* flags */ in sge_dma_alloc()
782 if (error != 0) { in sge_dma_alloc()
791 if (error != 0) { in sge_dma_alloc()
799 if (error != 0) { in sge_dma_alloc()
806 SGE_DESC_ALIGN, 0, /* alignment, boundary */ in sge_dma_alloc()
812 0, /* flags */ in sge_dma_alloc()
816 if (error != 0) { in sge_dma_alloc()
825 if (error != 0) { in sge_dma_alloc()
833 if (error != 0) { in sge_dma_alloc()
840 error = bus_dma_tag_create(cd->sge_tag, 1, 0, BUS_SPACE_MAXADDR, in sge_dma_alloc()
842 SGE_TSO_MAXSEGSIZE, 0, NULL, NULL, &cd->sge_txmbuf_tag); in sge_dma_alloc()
843 if (error != 0) { in sge_dma_alloc()
850 error = bus_dma_tag_create(cd->sge_tag, SGE_RX_BUF_ALIGN, 0, in sge_dma_alloc()
852 MCLBYTES, 0, NULL, NULL, &cd->sge_rxmbuf_tag); in sge_dma_alloc()
853 if (error != 0) { in sge_dma_alloc()
860 for (i = 0; i < SGE_TX_RING_CNT; i++) { in sge_dma_alloc()
864 txd->tx_ndesc = 0; in sge_dma_alloc()
865 error = bus_dmamap_create(cd->sge_txmbuf_tag, 0, in sge_dma_alloc()
867 if (error != 0) { in sge_dma_alloc()
874 error = bus_dmamap_create(cd->sge_rxmbuf_tag, 0, &cd->sge_rx_spare_map); in sge_dma_alloc()
875 if (error != 0) { in sge_dma_alloc()
881 for (i = 0; i < SGE_RX_RING_CNT; i++) { in sge_dma_alloc()
885 error = bus_dmamap_create(cd->sge_rxmbuf_tag, 0, in sge_dma_alloc()
910 if (ld->sge_rx_paddr != 0) in sge_dma_free()
916 ld->sge_rx_paddr = 0; in sge_dma_free()
922 if (ld->sge_tx_paddr != 0) in sge_dma_free()
928 ld->sge_tx_paddr = 0; in sge_dma_free()
934 for (i = 0; i < SGE_RX_RING_CNT; i++) { in sge_dma_free()
952 for (i = 0; i < SGE_TX_RING_CNT; i++) { in sge_dma_free()
984 cd->sge_tx_prod = 0; in sge_list_tx_init()
985 cd->sge_tx_cons = 0; in sge_list_tx_init()
986 cd->sge_tx_cnt = 0; in sge_list_tx_init()
987 return (0); in sge_list_tx_init()
999 for (i = 0; i < SGE_TX_RING_CNT; i++) { in sge_list_tx_free()
1007 txd->tx_ndesc = 0; in sge_list_tx_free()
1011 return (0); in sge_list_tx_free()
1027 cd->sge_rx_cons = 0; in sge_list_rx_init()
1029 for (i = 0; i < SGE_RX_RING_CNT; i++) { in sge_list_rx_init()
1030 if (sge_newbuf(sc, i) != 0) in sge_list_rx_init()
1035 return (0); in sge_list_rx_init()
1047 for (i = 0; i < SGE_RX_RING_CNT; i++) { in sge_list_rx_free()
1058 return (0); in sge_list_rx_free()
1084 cd->sge_rx_spare_map, m, segs, &nsegs, 0); in sge_newbuf()
1085 if (error != 0) { in sge_newbuf()
1104 desc->sge_sts_size = 0; in sge_newbuf()
1105 desc->sge_ptr = htole32(SGE_ADDR_LO(segs[0].ds_addr)); in sge_newbuf()
1106 desc->sge_flags = htole32(segs[0].ds_len); in sge_newbuf()
1110 return (0); in sge_newbuf()
1119 desc->sge_sts_size = 0; in sge_discard_rxbuf()
1148 for (prog = 0; prog < SGE_RX_RING_CNT; prog++, in sge_rxeof()
1150 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) in sge_rxeof()
1154 if ((rxinfo & RDC_OWN) != 0) in sge_rxeof()
1157 if ((rxstat & RDS_CRCOK) == 0 || SGE_RX_ERROR(rxstat) != 0 || in sge_rxeof()
1161 device_printf(sc->sge_dev, "Rx error : 0x%b\n", rxstat, in sge_rxeof()
1169 if (sge_newbuf(sc, cons) != 0) { in sge_rxeof()
1174 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) { in sge_rxeof()
1175 if ((rxinfo & RDC_IP_CSUM) != 0 && in sge_rxeof()
1176 (rxinfo & RDC_IP_CSUM_OK) != 0) in sge_rxeof()
1179 if (((rxinfo & RDC_TCP_CSUM) != 0 && in sge_rxeof()
1180 (rxinfo & RDC_TCP_CSUM_OK) != 0) || in sge_rxeof()
1181 ((rxinfo & RDC_UDP_CSUM) != 0 && in sge_rxeof()
1182 (rxinfo & RDC_UDP_CSUM_OK) != 0)) { in sge_rxeof()
1185 m->m_pkthdr.csum_data = 0xffff; in sge_rxeof()
1189 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0 && in sge_rxeof()
1190 (rxstat & RDS_VLAN) != 0) { in sge_rxeof()
1210 if (prog > 0) { in sge_rxeof()
1237 if (cd->sge_tx_cnt == 0) in sge_txeof()
1245 if ((txstat & TDC_OWN) != 0) in sge_txeof()
1254 if (SGE_TX_ERROR(txstat) != 0) { in sge_txeof()
1256 device_printf(sc->sge_dev, "Tx error : 0x%b\n", in sge_txeof()
1262 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, (txstat & 0xFFFF) - 1); in sge_txeof()
1267 for (nsegs = 0; nsegs < txd->tx_ndesc; nsegs++) { in sge_txeof()
1268 ld->sge_tx_ring[cons].sge_cmdsts = 0; in sge_txeof()
1280 KASSERT(cd->sge_tx_cnt >= 0, in sge_txeof()
1282 txd->tx_ndesc = 0; in sge_txeof()
1283 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); in sge_txeof()
1286 if (cd->sge_tx_cnt == 0) in sge_txeof()
1287 sc->sge_timer = 0; in sge_txeof()
1303 if ((sc->sge_flags & SGE_FLAG_LINK) == 0) { in sge_tick()
1305 if ((sc->sge_flags & SGE_FLAG_LINK) != 0 && in sge_tick()
1331 if (status == 0xFFFFFFFF || (status & SGE_INTRS) == 0) { in sge_intr()
1339 CSR_WRITE_4(sc, IntrMask, 0); in sge_intr()
1350 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) in sge_intr()
1352 if ((status & (INTR_RX_DONE | INTR_RX_IDLE)) != 0) { in sge_intr()
1355 if ((status & INTR_RX_IDLE) != 0) in sge_intr()
1357 0x1a00 | 0x000c | RX_CTL_POLL | RX_CTL_ENB); in sge_intr()
1359 if ((status & (INTR_TX_DONE | INTR_TX_IDLE)) != 0) in sge_intr()
1362 if ((status & SGE_INTRS) == 0) in sge_intr()
1367 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { in sge_intr()
1394 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) { in sge_encap()
1400 if (M_WRITABLE(*m_head) == 0) { in sge_encap()
1449 ip->ip_sum = 0; in sge_encap()
1457 txd->tx_dmamap, *m_head, txsegs, &nsegs, 0); in sge_encap()
1467 txd->tx_dmamap, *m_head, txsegs, &nsegs, 0); in sge_encap()
1468 if (error != 0) { in sge_encap()
1473 } else if (error != 0) in sge_encap()
1476 KASSERT(nsegs != 0, ("zero segment returned")); in sge_encap()
1486 cflags = 0; in sge_encap()
1487 mss = 0; in sge_encap()
1488 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { in sge_encap()
1500 for (i = 0; i < nsegs; i++) { in sge_encap()
1502 if (i == 0) { in sge_encap()
1504 desc->sge_cmdsts = 0; in sge_encap()
1506 desc->sge_sts_size = 0; in sge_encap()
1521 if((m->m_flags & M_VLANTAG) != 0) { in sge_encap()
1527 if ((sc->sge_flags & SGE_FLAG_SPEED_1000) != 0) in sge_encap()
1530 if ((sc->sge_flags & SGE_FLAG_FDX) == 0) { in sge_encap()
1532 if ((sc->sge_flags & SGE_FLAG_SPEED_1000) != 0) in sge_encap()
1540 return (0); in sge_encap()
1559 int queued = 0; in sge_start_locked()
1564 if ((sc->sge_flags & SGE_FLAG_LINK) == 0 || in sge_start_locked()
1569 for (queued = 0; !if_sendq_empty(ifp); ) { in sge_start_locked()
1572 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); in sge_start_locked()
1582 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); in sge_start_locked()
1593 if (queued > 0) { in sge_start_locked()
1597 CSR_WRITE_4(sc, TX_CTL, 0x1a00 | TX_CTL_ENB | TX_CTL_POLL); in sge_start_locked()
1624 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) in sge_init_locked()
1646 CSR_WRITE_4(sc, TxMacControl, 0x60); in sge_init_locked()
1647 CSR_WRITE_4(sc, RxWakeOnLan, 0); in sge_init_locked()
1648 CSR_WRITE_4(sc, RxWakeOnLanData, 0); in sge_init_locked()
1653 for (i = 0; i < ETHER_ADDR_LEN; i++) in sge_init_locked()
1662 if ((sc->sge_flags & SGE_FLAG_FASTETHER) == 0) in sge_init_locked()
1665 if ((sc->sge_flags & SGE_FLAG_RGMII) != 0) in sge_init_locked()
1666 CSR_WRITE_4(sc, StationControl, 0x04008001); in sge_init_locked()
1668 CSR_WRITE_4(sc, StationControl, 0x04000001); in sge_init_locked()
1672 CSR_WRITE_4(sc, IntrControl, 0x08880000); in sge_init_locked()
1674 if (sc->sge_intrcontrol != 0) in sge_init_locked()
1676 if (sc->sge_intrtimer != 0) in sge_init_locked()
1683 CSR_WRITE_4(sc, IntrStatus, 0xFFFFFFFF); in sge_init_locked()
1687 CSR_WRITE_4(sc, TX_CTL, 0x1a00 | TX_CTL_ENB); in sge_init_locked()
1688 CSR_WRITE_4(sc, RX_CTL, 0x1a00 | 0x000c | RX_CTL_POLL | RX_CTL_ENB); in sge_init_locked()
1690 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); in sge_init_locked()
1691 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); in sge_init_locked()
1732 if ((if_getflags(ifp) & IFF_UP) == 0) { in sge_ifmedia_sts()
1748 int error = 0, mask, reinit; in sge_ioctl()
1756 if ((if_getflags(ifp) & IFF_UP) != 0) { in sge_ioctl()
1757 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0 && in sge_ioctl()
1759 (IFF_PROMISC | IFF_ALLMULTI)) != 0) in sge_ioctl()
1763 } else if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) in sge_ioctl()
1770 reinit = 0; in sge_ioctl()
1772 if ((mask & IFCAP_TXCSUM) != 0 && in sge_ioctl()
1773 (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) { in sge_ioctl()
1775 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0) in sge_ioctl()
1776 if_sethwassistbits(ifp, SGE_CSUM_FEATURES, 0); in sge_ioctl()
1778 if_sethwassistbits(ifp, 0, SGE_CSUM_FEATURES); in sge_ioctl()
1780 if ((mask & IFCAP_RXCSUM) != 0 && in sge_ioctl()
1781 (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0) in sge_ioctl()
1783 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && in sge_ioctl()
1784 (if_getcapabilities(ifp) & IFCAP_VLAN_HWCSUM) != 0) in sge_ioctl()
1786 if ((mask & IFCAP_TSO4) != 0 && in sge_ioctl()
1787 (if_getcapabilities(ifp) & IFCAP_TSO4) != 0) { in sge_ioctl()
1789 if ((if_getcapenable(ifp) & IFCAP_TSO4) != 0) in sge_ioctl()
1790 if_sethwassistbits(ifp, CSUM_TSO, 0); in sge_ioctl()
1792 if_sethwassistbits(ifp, 0, CSUM_TSO); in sge_ioctl()
1794 if ((mask & IFCAP_VLAN_HWTSO) != 0 && in sge_ioctl()
1795 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTSO) != 0) in sge_ioctl()
1797 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && in sge_ioctl()
1798 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) { in sge_ioctl()
1804 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0) in sge_ioctl()
1805 if_setcapenablebit(ifp, 0, in sge_ioctl()
1809 if (reinit > 0 && (if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { in sge_ioctl()
1810 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); in sge_ioctl()
1819 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) in sge_ioctl()
1842 if (sc->sge_timer == 0 || --sc->sge_timer > 0) in sge_watchdog()
1846 if ((sc->sge_flags & SGE_FLAG_LINK) == 0) { in sge_watchdog()
1851 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); in sge_watchdog()
1858 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); in sge_watchdog()
1877 sc->sge_timer = 0; in sge_stop()
1879 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); in sge_stop()
1881 CSR_WRITE_4(sc, IntrMask, 0); in sge_stop()
1883 CSR_WRITE_4(sc, IntrStatus, 0xffffffff); in sge_stop()
1885 CSR_WRITE_4(sc, TX_CTL, 0x1a00); in sge_stop()
1886 CSR_WRITE_4(sc, RX_CTL, 0x1a00); in sge_stop()
1889 CSR_WRITE_4(sc, IntrMask, 0); in sge_stop()
1890 CSR_WRITE_4(sc, IntrStatus, 0xffffffff); in sge_stop()