16975124cSRafal Jaworowski /*-
251369649SPedro F. Giffuni * SPDX-License-Identifier: BSD-3-Clause
351369649SPedro F. Giffuni *
4db5ef4fcSRafal Jaworowski * Copyright (c) 2008 MARVELL INTERNATIONAL LTD.
5db5ef4fcSRafal Jaworowski * Copyright (c) 2010 The FreeBSD Foundation
61e92574fSZbigniew Bodek * Copyright (c) 2010-2015 Semihalf
76975124cSRafal Jaworowski * All rights reserved.
86975124cSRafal Jaworowski *
96975124cSRafal Jaworowski * Developed by Semihalf.
106975124cSRafal Jaworowski *
11db5ef4fcSRafal Jaworowski * Portions of this software were developed by Semihalf
12db5ef4fcSRafal Jaworowski * under sponsorship from the FreeBSD Foundation.
13db5ef4fcSRafal Jaworowski *
146975124cSRafal Jaworowski * Redistribution and use in source and binary forms, with or without
156975124cSRafal Jaworowski * modification, are permitted provided that the following conditions
166975124cSRafal Jaworowski * are met:
176975124cSRafal Jaworowski * 1. Redistributions of source code must retain the above copyright
186975124cSRafal Jaworowski * notice, this list of conditions and the following disclaimer.
196975124cSRafal Jaworowski * 2. Redistributions in binary form must reproduce the above copyright
206975124cSRafal Jaworowski * notice, this list of conditions and the following disclaimer in the
216975124cSRafal Jaworowski * documentation and/or other materials provided with the distribution.
226975124cSRafal Jaworowski * 3. Neither the name of MARVELL nor the names of contributors
236975124cSRafal Jaworowski * may be used to endorse or promote products derived from this software
246975124cSRafal Jaworowski * without specific prior written permission.
256975124cSRafal Jaworowski *
266975124cSRafal Jaworowski * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
276975124cSRafal Jaworowski * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
286975124cSRafal Jaworowski * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
296975124cSRafal Jaworowski * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
306975124cSRafal Jaworowski * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
316975124cSRafal Jaworowski * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
326975124cSRafal Jaworowski * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
336975124cSRafal Jaworowski * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
346975124cSRafal Jaworowski * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
356975124cSRafal Jaworowski * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
366975124cSRafal Jaworowski * SUCH DAMAGE.
376975124cSRafal Jaworowski */
386975124cSRafal Jaworowski
396975124cSRafal Jaworowski /*
406975124cSRafal Jaworowski * Marvell integrated PCI/PCI-Express controller driver.
416975124cSRafal Jaworowski */
426975124cSRafal Jaworowski
436975124cSRafal Jaworowski #include <sys/param.h>
446975124cSRafal Jaworowski #include <sys/systm.h>
456975124cSRafal Jaworowski #include <sys/kernel.h>
466975124cSRafal Jaworowski #include <sys/lock.h>
476975124cSRafal Jaworowski #include <sys/malloc.h>
486975124cSRafal Jaworowski #include <sys/module.h>
496975124cSRafal Jaworowski #include <sys/mutex.h>
506975124cSRafal Jaworowski #include <sys/queue.h>
516975124cSRafal Jaworowski #include <sys/bus.h>
526975124cSRafal Jaworowski #include <sys/rman.h>
536975124cSRafal Jaworowski #include <sys/endian.h>
5430b72b68SRuslan Bukin #include <sys/devmap.h>
556975124cSRafal Jaworowski
56dcd08302SNathan Whitehorn #include <machine/fdt.h>
5764dc1cf3SGrzegorz Bernacki #include <machine/intr.h>
5864dc1cf3SGrzegorz Bernacki
596975124cSRafal Jaworowski #include <vm/vm.h>
606975124cSRafal Jaworowski #include <vm/pmap.h>
616975124cSRafal Jaworowski
62db5ef4fcSRafal Jaworowski #include <dev/fdt/fdt_common.h>
63db5ef4fcSRafal Jaworowski #include <dev/ofw/ofw_bus.h>
64db5ef4fcSRafal Jaworowski #include <dev/ofw/ofw_bus_subr.h>
65f9a32acbSAndrew Turner #include <dev/ofw/ofw_pci.h>
666975124cSRafal Jaworowski #include <dev/pci/pcivar.h>
676975124cSRafal Jaworowski #include <dev/pci/pcireg.h>
686975124cSRafal Jaworowski #include <dev/pci/pcib_private.h>
696975124cSRafal Jaworowski
70db5ef4fcSRafal Jaworowski #include "ofw_bus_if.h"
716975124cSRafal Jaworowski #include "pcib_if.h"
726975124cSRafal Jaworowski
736975124cSRafal Jaworowski #include <machine/resource.h>
746975124cSRafal Jaworowski #include <machine/bus.h>
756975124cSRafal Jaworowski
766975124cSRafal Jaworowski #include <arm/mv/mvreg.h>
776975124cSRafal Jaworowski #include <arm/mv/mvvar.h>
78db5ef4fcSRafal Jaworowski #include <arm/mv/mvwin.h>
796975124cSRafal Jaworowski
8064dc1cf3SGrzegorz Bernacki #ifdef DEBUG
8164dc1cf3SGrzegorz Bernacki #define debugf(fmt, args...) do { printf(fmt,##args); } while (0)
8264dc1cf3SGrzegorz Bernacki #else
8364dc1cf3SGrzegorz Bernacki #define debugf(fmt, args...)
8464dc1cf3SGrzegorz Bernacki #endif
8564dc1cf3SGrzegorz Bernacki
8602c7dba9SIan Lepore /*
8702c7dba9SIan Lepore * Code and data related to fdt-based PCI configuration.
8802c7dba9SIan Lepore *
8902c7dba9SIan Lepore * This stuff used to be in dev/fdt/fdt_pci.c and fdt_common.h, but it was
9002c7dba9SIan Lepore * always Marvell-specific so that was deleted and the code now lives here.
9102c7dba9SIan Lepore */
9202c7dba9SIan Lepore
9302c7dba9SIan Lepore struct mv_pci_range {
9402c7dba9SIan Lepore u_long base_pci;
9502c7dba9SIan Lepore u_long base_parent;
9602c7dba9SIan Lepore u_long len;
9702c7dba9SIan Lepore };
9802c7dba9SIan Lepore
9902c7dba9SIan Lepore #define FDT_RANGES_CELLS ((3 + 3 + 2) * 2)
1006534f932SOleksandr Tymoshenko #define PCI_SPACE_LEN 0x00400000
10102c7dba9SIan Lepore
10202c7dba9SIan Lepore static void
mv_pci_range_dump(struct mv_pci_range * range)10302c7dba9SIan Lepore mv_pci_range_dump(struct mv_pci_range *range)
10402c7dba9SIan Lepore {
10502c7dba9SIan Lepore #ifdef DEBUG
10602c7dba9SIan Lepore printf("\n");
10702c7dba9SIan Lepore printf(" base_pci = 0x%08lx\n", range->base_pci);
10802c7dba9SIan Lepore printf(" base_par = 0x%08lx\n", range->base_parent);
10902c7dba9SIan Lepore printf(" len = 0x%08lx\n", range->len);
11002c7dba9SIan Lepore #endif
11102c7dba9SIan Lepore }
11202c7dba9SIan Lepore
11302c7dba9SIan Lepore static int
mv_pci_ranges_decode(phandle_t node,struct mv_pci_range * io_space,struct mv_pci_range * mem_space)11402c7dba9SIan Lepore mv_pci_ranges_decode(phandle_t node, struct mv_pci_range *io_space,
11502c7dba9SIan Lepore struct mv_pci_range *mem_space)
11602c7dba9SIan Lepore {
11702c7dba9SIan Lepore pcell_t ranges[FDT_RANGES_CELLS];
11802c7dba9SIan Lepore struct mv_pci_range *pci_space;
11902c7dba9SIan Lepore pcell_t addr_cells, size_cells, par_addr_cells;
12002c7dba9SIan Lepore pcell_t *rangesptr;
121c16bfb03SJohn Baldwin pcell_t cell0, cell2;
12202c7dba9SIan Lepore int tuple_size, tuples, i, rv, offset_cells, len;
12346db7283SMarcin Wojtas int portid, is_io_space;
12402c7dba9SIan Lepore
12502c7dba9SIan Lepore /*
12602c7dba9SIan Lepore * Retrieve 'ranges' property.
12702c7dba9SIan Lepore */
12802c7dba9SIan Lepore if ((fdt_addrsize_cells(node, &addr_cells, &size_cells)) != 0)
12902c7dba9SIan Lepore return (EINVAL);
13002c7dba9SIan Lepore if (addr_cells != 3 || size_cells != 2)
13102c7dba9SIan Lepore return (ERANGE);
13202c7dba9SIan Lepore
13302c7dba9SIan Lepore par_addr_cells = fdt_parent_addr_cells(node);
13402c7dba9SIan Lepore if (par_addr_cells > 3)
13502c7dba9SIan Lepore return (ERANGE);
13602c7dba9SIan Lepore
13702c7dba9SIan Lepore len = OF_getproplen(node, "ranges");
13802c7dba9SIan Lepore if (len > sizeof(ranges))
13902c7dba9SIan Lepore return (ENOMEM);
14002c7dba9SIan Lepore
14102c7dba9SIan Lepore if (OF_getprop(node, "ranges", ranges, sizeof(ranges)) <= 0)
14202c7dba9SIan Lepore return (EINVAL);
14302c7dba9SIan Lepore
14402c7dba9SIan Lepore tuple_size = sizeof(pcell_t) * (addr_cells + par_addr_cells +
14502c7dba9SIan Lepore size_cells);
14602c7dba9SIan Lepore tuples = len / tuple_size;
14702c7dba9SIan Lepore
14802c7dba9SIan Lepore /*
14902c7dba9SIan Lepore * Initialize the ranges so that we don't have to worry about
15002c7dba9SIan Lepore * having them all defined in the FDT. In particular, it is
151db4fcadfSConrad Meyer * perfectly fine not to want I/O space on PCI buses.
15202c7dba9SIan Lepore */
15302c7dba9SIan Lepore bzero(io_space, sizeof(*io_space));
15402c7dba9SIan Lepore bzero(mem_space, sizeof(*mem_space));
15502c7dba9SIan Lepore
15602c7dba9SIan Lepore rangesptr = &ranges[0];
15702c7dba9SIan Lepore offset_cells = 0;
15802c7dba9SIan Lepore for (i = 0; i < tuples; i++) {
15902c7dba9SIan Lepore cell0 = fdt_data_get((void *)rangesptr, 1);
16002c7dba9SIan Lepore rangesptr++;
161c16bfb03SJohn Baldwin /* cell1 */
16202c7dba9SIan Lepore rangesptr++;
16302c7dba9SIan Lepore cell2 = fdt_data_get((void *)rangesptr, 1);
16402c7dba9SIan Lepore rangesptr++;
16546db7283SMarcin Wojtas portid = fdt_data_get((void *)(rangesptr+1), 1);
16602c7dba9SIan Lepore
16702c7dba9SIan Lepore if (cell0 & 0x02000000) {
16802c7dba9SIan Lepore pci_space = mem_space;
16946db7283SMarcin Wojtas is_io_space = 0;
17002c7dba9SIan Lepore } else if (cell0 & 0x01000000) {
17102c7dba9SIan Lepore pci_space = io_space;
17246db7283SMarcin Wojtas is_io_space = 1;
17302c7dba9SIan Lepore } else {
17402c7dba9SIan Lepore rv = ERANGE;
17502c7dba9SIan Lepore goto out;
17602c7dba9SIan Lepore }
17702c7dba9SIan Lepore
17802c7dba9SIan Lepore if (par_addr_cells == 3) {
17902c7dba9SIan Lepore /*
18002c7dba9SIan Lepore * This is a PCI subnode 'ranges'. Skip cell0 and
18102c7dba9SIan Lepore * cell1 of this entry and only use cell2.
18202c7dba9SIan Lepore */
18302c7dba9SIan Lepore offset_cells = 2;
18402c7dba9SIan Lepore rangesptr += offset_cells;
18502c7dba9SIan Lepore }
18602c7dba9SIan Lepore
1871f7f3314SRuslan Bukin if ((par_addr_cells - offset_cells) > 2) {
18802c7dba9SIan Lepore rv = ERANGE;
18902c7dba9SIan Lepore goto out;
19002c7dba9SIan Lepore }
19102c7dba9SIan Lepore pci_space->base_parent = fdt_data_get((void *)rangesptr,
19202c7dba9SIan Lepore par_addr_cells - offset_cells);
19302c7dba9SIan Lepore rangesptr += par_addr_cells - offset_cells;
19402c7dba9SIan Lepore
195dd279f7aSRuslan Bukin if (size_cells > 2) {
19602c7dba9SIan Lepore rv = ERANGE;
19702c7dba9SIan Lepore goto out;
19802c7dba9SIan Lepore }
19902c7dba9SIan Lepore pci_space->len = fdt_data_get((void *)rangesptr, size_cells);
20002c7dba9SIan Lepore rangesptr += size_cells;
20102c7dba9SIan Lepore
20202c7dba9SIan Lepore pci_space->base_pci = cell2;
20346db7283SMarcin Wojtas
20446db7283SMarcin Wojtas if (pci_space->len == 0) {
20546db7283SMarcin Wojtas pci_space->len = PCI_SPACE_LEN;
20646db7283SMarcin Wojtas pci_space->base_parent = fdt_immr_va +
20746db7283SMarcin Wojtas PCI_SPACE_LEN * ( 2 * portid + is_io_space);
20846db7283SMarcin Wojtas }
20902c7dba9SIan Lepore }
21002c7dba9SIan Lepore rv = 0;
21102c7dba9SIan Lepore out:
21202c7dba9SIan Lepore return (rv);
21302c7dba9SIan Lepore }
21402c7dba9SIan Lepore
21502c7dba9SIan Lepore static int
mv_pci_ranges(phandle_t node,struct mv_pci_range * io_space,struct mv_pci_range * mem_space)21602c7dba9SIan Lepore mv_pci_ranges(phandle_t node, struct mv_pci_range *io_space,
21702c7dba9SIan Lepore struct mv_pci_range *mem_space)
21802c7dba9SIan Lepore {
21902c7dba9SIan Lepore int err;
22002c7dba9SIan Lepore
22102c7dba9SIan Lepore debugf("Processing PCI node: %x\n", node);
22202c7dba9SIan Lepore if ((err = mv_pci_ranges_decode(node, io_space, mem_space)) != 0) {
22302c7dba9SIan Lepore debugf("could not decode parent PCI node 'ranges'\n");
22402c7dba9SIan Lepore return (err);
22502c7dba9SIan Lepore }
22602c7dba9SIan Lepore
22702c7dba9SIan Lepore debugf("Post fixup dump:\n");
22802c7dba9SIan Lepore mv_pci_range_dump(io_space);
22902c7dba9SIan Lepore mv_pci_range_dump(mem_space);
23002c7dba9SIan Lepore return (0);
23102c7dba9SIan Lepore }
23202c7dba9SIan Lepore
23302c7dba9SIan Lepore int
mv_pci_devmap(phandle_t node,struct devmap_entry * devmap,vm_offset_t io_va,vm_offset_t mem_va)23430b72b68SRuslan Bukin mv_pci_devmap(phandle_t node, struct devmap_entry *devmap, vm_offset_t io_va,
23502c7dba9SIan Lepore vm_offset_t mem_va)
23602c7dba9SIan Lepore {
23702c7dba9SIan Lepore struct mv_pci_range io_space, mem_space;
23802c7dba9SIan Lepore int error;
23902c7dba9SIan Lepore
24002c7dba9SIan Lepore if ((error = mv_pci_ranges_decode(node, &io_space, &mem_space)) != 0)
24102c7dba9SIan Lepore return (error);
24202c7dba9SIan Lepore
24302c7dba9SIan Lepore devmap->pd_va = (io_va ? io_va : io_space.base_parent);
24402c7dba9SIan Lepore devmap->pd_pa = io_space.base_parent;
24502c7dba9SIan Lepore devmap->pd_size = io_space.len;
24602c7dba9SIan Lepore devmap++;
24702c7dba9SIan Lepore
24802c7dba9SIan Lepore devmap->pd_va = (mem_va ? mem_va : mem_space.base_parent);
24902c7dba9SIan Lepore devmap->pd_pa = mem_space.base_parent;
25002c7dba9SIan Lepore devmap->pd_size = mem_space.len;
25102c7dba9SIan Lepore return (0);
25202c7dba9SIan Lepore }
25302c7dba9SIan Lepore
25402c7dba9SIan Lepore /*
25502c7dba9SIan Lepore * Code and data related to the Marvell pcib driver.
25602c7dba9SIan Lepore */
25702c7dba9SIan Lepore
2587a22215cSEitan Adler #define PCI_CFG_ENA (1U << 31)
2596975124cSRafal Jaworowski #define PCI_CFG_BUS(bus) (((bus) & 0xff) << 16)
2606975124cSRafal Jaworowski #define PCI_CFG_DEV(dev) (((dev) & 0x1f) << 11)
2616975124cSRafal Jaworowski #define PCI_CFG_FUN(fun) (((fun) & 0x7) << 8)
2626975124cSRafal Jaworowski #define PCI_CFG_PCIE_REG(reg) ((reg) & 0xfc)
2636975124cSRafal Jaworowski
2646975124cSRafal Jaworowski #define PCI_REG_CFG_ADDR 0x0C78
2656975124cSRafal Jaworowski #define PCI_REG_CFG_DATA 0x0C7C
2666975124cSRafal Jaworowski
2676975124cSRafal Jaworowski #define PCIE_REG_CFG_ADDR 0x18F8
2686975124cSRafal Jaworowski #define PCIE_REG_CFG_DATA 0x18FC
2696975124cSRafal Jaworowski #define PCIE_REG_CONTROL 0x1A00
2706975124cSRafal Jaworowski #define PCIE_CTRL_LINK1X 0x00000001
2716975124cSRafal Jaworowski #define PCIE_REG_STATUS 0x1A04
2726975124cSRafal Jaworowski #define PCIE_REG_IRQ_MASK 0x1910
2736975124cSRafal Jaworowski
274e3ac9753SGrzegorz Bernacki #define PCIE_CONTROL_ROOT_CMPLX (1 << 1)
275e3ac9753SGrzegorz Bernacki #define PCIE_CONTROL_HOT_RESET (1 << 24)
2766975124cSRafal Jaworowski
277e3ac9753SGrzegorz Bernacki #define PCIE_LINK_TIMEOUT 1000000
2786975124cSRafal Jaworowski
279e3ac9753SGrzegorz Bernacki #define PCIE_STATUS_LINK_DOWN 1
280e3ac9753SGrzegorz Bernacki #define PCIE_STATUS_DEV_OFFS 16
281e3ac9753SGrzegorz Bernacki
282e3ac9753SGrzegorz Bernacki /* Minimum PCI Memory and I/O allocations taken from PCI spec (in bytes) */
283e3ac9753SGrzegorz Bernacki #define PCI_MIN_IO_ALLOC 4
284e3ac9753SGrzegorz Bernacki #define PCI_MIN_MEM_ALLOC 16
285e3ac9753SGrzegorz Bernacki
286e3ac9753SGrzegorz Bernacki #define BITS_PER_UINT32 (NBBY * sizeof(uint32_t))
2876975124cSRafal Jaworowski
288db5ef4fcSRafal Jaworowski struct mv_pcib_softc {
2896975124cSRafal Jaworowski device_t sc_dev;
2906975124cSRafal Jaworowski
291db5ef4fcSRafal Jaworowski struct rman sc_mem_rman;
292db5ef4fcSRafal Jaworowski bus_addr_t sc_mem_base;
293db5ef4fcSRafal Jaworowski bus_addr_t sc_mem_size;
294e3ac9753SGrzegorz Bernacki uint32_t sc_mem_map[MV_PCI_MEM_SLICE_SIZE /
295e3ac9753SGrzegorz Bernacki (PCI_MIN_MEM_ALLOC * BITS_PER_UINT32)];
296e3ac9753SGrzegorz Bernacki int sc_win_target;
297db5ef4fcSRafal Jaworowski int sc_mem_win_attr;
2986975124cSRafal Jaworowski
299db5ef4fcSRafal Jaworowski struct rman sc_io_rman;
300db5ef4fcSRafal Jaworowski bus_addr_t sc_io_base;
301db5ef4fcSRafal Jaworowski bus_addr_t sc_io_size;
302e3ac9753SGrzegorz Bernacki uint32_t sc_io_map[MV_PCI_IO_SLICE_SIZE /
303e3ac9753SGrzegorz Bernacki (PCI_MIN_IO_ALLOC * BITS_PER_UINT32)];
304db5ef4fcSRafal Jaworowski int sc_io_win_attr;
3056975124cSRafal Jaworowski
3066975124cSRafal Jaworowski struct resource *sc_res;
3076975124cSRafal Jaworowski bus_space_handle_t sc_bsh;
3086975124cSRafal Jaworowski bus_space_tag_t sc_bst;
3096975124cSRafal Jaworowski int sc_rid;
3106975124cSRafal Jaworowski
31164dc1cf3SGrzegorz Bernacki struct mtx sc_msi_mtx;
31264dc1cf3SGrzegorz Bernacki uint32_t sc_msi_bitmap;
31364dc1cf3SGrzegorz Bernacki
3146975124cSRafal Jaworowski int sc_busnr; /* Host bridge bus number */
3156975124cSRafal Jaworowski int sc_devnr; /* Host bridge device number */
316db5ef4fcSRafal Jaworowski int sc_type;
317e3ac9753SGrzegorz Bernacki int sc_mode; /* Endpoint / Root Complex */
3186975124cSRafal Jaworowski
319fefc2cf7SMarcin Wojtas int sc_msi_supported;
320fefc2cf7SMarcin Wojtas int sc_skip_enable_procedure;
321fefc2cf7SMarcin Wojtas int sc_enable_find_root_slot;
322c826a643SNathan Whitehorn struct ofw_bus_iinfo sc_pci_iinfo;
3233a582d09SMarcin Wojtas
3243a582d09SMarcin Wojtas int ap_segment; /* PCI domain */
3256975124cSRafal Jaworowski };
3266975124cSRafal Jaworowski
327db5ef4fcSRafal Jaworowski /* Local forward prototypes */
328db5ef4fcSRafal Jaworowski static int mv_pcib_decode_win(phandle_t, struct mv_pcib_softc *);
329db5ef4fcSRafal Jaworowski static void mv_pcib_hw_cfginit(void);
330db5ef4fcSRafal Jaworowski static uint32_t mv_pcib_hw_cfgread(struct mv_pcib_softc *, u_int, u_int,
331db5ef4fcSRafal Jaworowski u_int, u_int, int);
332db5ef4fcSRafal Jaworowski static void mv_pcib_hw_cfgwrite(struct mv_pcib_softc *, u_int, u_int,
333db5ef4fcSRafal Jaworowski u_int, u_int, uint32_t, int);
334db5ef4fcSRafal Jaworowski static int mv_pcib_init(struct mv_pcib_softc *, int, int);
335db5ef4fcSRafal Jaworowski static int mv_pcib_init_all_bars(struct mv_pcib_softc *, int, int, int, int);
336db5ef4fcSRafal Jaworowski static void mv_pcib_init_bridge(struct mv_pcib_softc *, int, int, int);
337db5ef4fcSRafal Jaworowski static inline void pcib_write_irq_mask(struct mv_pcib_softc *, uint32_t);
338e3ac9753SGrzegorz Bernacki static void mv_pcib_enable(struct mv_pcib_softc *, uint32_t);
339e3ac9753SGrzegorz Bernacki static int mv_pcib_mem_init(struct mv_pcib_softc *);
340db5ef4fcSRafal Jaworowski
341db5ef4fcSRafal Jaworowski /* Forward prototypes */
342db5ef4fcSRafal Jaworowski static int mv_pcib_probe(device_t);
343db5ef4fcSRafal Jaworowski static int mv_pcib_attach(device_t);
344db5ef4fcSRafal Jaworowski
3454e1d94d9SJohn Baldwin static struct rman *mv_pcib_get_rman(device_t, int, u_int);
346db5ef4fcSRafal Jaworowski static struct resource *mv_pcib_alloc_resource(device_t, device_t, int, int *,
3472dd1bdf1SJustin Hibbits rman_res_t, rman_res_t, rman_res_t, u_int);
348fef01f04SJohn Baldwin static int mv_pcib_adjust_resource(device_t, device_t, struct resource *,
3494e1d94d9SJohn Baldwin rman_res_t, rman_res_t);
3509dbf5b0eSJohn Baldwin static int mv_pcib_release_resource(device_t, device_t, struct resource *);
3512baed46eSJohn Baldwin static int mv_pcib_activate_resource(device_t, device_t, struct resource *);
3522baed46eSJohn Baldwin static int mv_pcib_deactivate_resource(device_t, device_t, struct resource *);
353d77f2092SJohn Baldwin static int mv_pcib_map_resource(device_t, device_t, struct resource *,
3544e1d94d9SJohn Baldwin struct resource_map_request *, struct resource_map *);
355d77f2092SJohn Baldwin static int mv_pcib_unmap_resource(device_t, device_t, struct resource *,
3564e1d94d9SJohn Baldwin struct resource_map *);
357db5ef4fcSRafal Jaworowski static int mv_pcib_read_ivar(device_t, device_t, int, uintptr_t *);
358db5ef4fcSRafal Jaworowski static int mv_pcib_write_ivar(device_t, device_t, int, uintptr_t);
3596975124cSRafal Jaworowski
360db5ef4fcSRafal Jaworowski static int mv_pcib_maxslots(device_t);
361db5ef4fcSRafal Jaworowski static uint32_t mv_pcib_read_config(device_t, u_int, u_int, u_int, u_int, int);
362db5ef4fcSRafal Jaworowski static void mv_pcib_write_config(device_t, u_int, u_int, u_int, u_int,
3636975124cSRafal Jaworowski uint32_t, int);
364db5ef4fcSRafal Jaworowski static int mv_pcib_route_interrupt(device_t, device_t, int);
365fefc2cf7SMarcin Wojtas
36664dc1cf3SGrzegorz Bernacki static int mv_pcib_alloc_msi(device_t, device_t, int, int, int *);
36764dc1cf3SGrzegorz Bernacki static int mv_pcib_map_msi(device_t, device_t, int, uint64_t *, uint32_t *);
36864dc1cf3SGrzegorz Bernacki static int mv_pcib_release_msi(device_t, device_t, int, int *);
3696975124cSRafal Jaworowski
3706975124cSRafal Jaworowski /*
3716975124cSRafal Jaworowski * Bus interface definitions.
3726975124cSRafal Jaworowski */
373db5ef4fcSRafal Jaworowski static device_method_t mv_pcib_methods[] = {
3746975124cSRafal Jaworowski /* Device interface */
375db5ef4fcSRafal Jaworowski DEVMETHOD(device_probe, mv_pcib_probe),
376db5ef4fcSRafal Jaworowski DEVMETHOD(device_attach, mv_pcib_attach),
3776975124cSRafal Jaworowski
3786975124cSRafal Jaworowski /* Bus interface */
379db5ef4fcSRafal Jaworowski DEVMETHOD(bus_read_ivar, mv_pcib_read_ivar),
380db5ef4fcSRafal Jaworowski DEVMETHOD(bus_write_ivar, mv_pcib_write_ivar),
3814e1d94d9SJohn Baldwin DEVMETHOD(bus_get_rman, mv_pcib_get_rman),
382db5ef4fcSRafal Jaworowski DEVMETHOD(bus_alloc_resource, mv_pcib_alloc_resource),
3834e1d94d9SJohn Baldwin DEVMETHOD(bus_adjust_resource, mv_pcib_adjust_resource),
384db5ef4fcSRafal Jaworowski DEVMETHOD(bus_release_resource, mv_pcib_release_resource),
3854e1d94d9SJohn Baldwin DEVMETHOD(bus_activate_resource, mv_pcib_activate_resource),
3864e1d94d9SJohn Baldwin DEVMETHOD(bus_deactivate_resource, mv_pcib_deactivate_resource),
3874e1d94d9SJohn Baldwin DEVMETHOD(bus_map_resource, mv_pcib_map_resource),
3884e1d94d9SJohn Baldwin DEVMETHOD(bus_unmap_resource, mv_pcib_unmap_resource),
3896975124cSRafal Jaworowski DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
3906975124cSRafal Jaworowski DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
3916975124cSRafal Jaworowski
3926975124cSRafal Jaworowski /* pcib interface */
393db5ef4fcSRafal Jaworowski DEVMETHOD(pcib_maxslots, mv_pcib_maxslots),
394db5ef4fcSRafal Jaworowski DEVMETHOD(pcib_read_config, mv_pcib_read_config),
395db5ef4fcSRafal Jaworowski DEVMETHOD(pcib_write_config, mv_pcib_write_config),
396db5ef4fcSRafal Jaworowski DEVMETHOD(pcib_route_interrupt, mv_pcib_route_interrupt),
39728586889SWarner Losh DEVMETHOD(pcib_request_feature, pcib_request_feature_allow),
398fefc2cf7SMarcin Wojtas
39964dc1cf3SGrzegorz Bernacki DEVMETHOD(pcib_alloc_msi, mv_pcib_alloc_msi),
40064dc1cf3SGrzegorz Bernacki DEVMETHOD(pcib_release_msi, mv_pcib_release_msi),
40164dc1cf3SGrzegorz Bernacki DEVMETHOD(pcib_map_msi, mv_pcib_map_msi),
40264dc1cf3SGrzegorz Bernacki
403db5ef4fcSRafal Jaworowski /* OFW bus interface */
404db5ef4fcSRafal Jaworowski DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat),
405db5ef4fcSRafal Jaworowski DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model),
406db5ef4fcSRafal Jaworowski DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name),
407db5ef4fcSRafal Jaworowski DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node),
408db5ef4fcSRafal Jaworowski DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type),
4096975124cSRafal Jaworowski
4104b7ec270SMarius Strobl DEVMETHOD_END
4116975124cSRafal Jaworowski };
4126975124cSRafal Jaworowski
413db5ef4fcSRafal Jaworowski static driver_t mv_pcib_driver = {
4146975124cSRafal Jaworowski "pcib",
415db5ef4fcSRafal Jaworowski mv_pcib_methods,
416db5ef4fcSRafal Jaworowski sizeof(struct mv_pcib_softc),
4176975124cSRafal Jaworowski };
4186975124cSRafal Jaworowski
419a3b866cbSJohn Baldwin DRIVER_MODULE(mv_pcib, ofwbus, mv_pcib_driver, 0, 0);
420a3b866cbSJohn Baldwin DRIVER_MODULE(mv_pcib, pcib_ctrl, mv_pcib_driver, 0, 0);
4216975124cSRafal Jaworowski
4226975124cSRafal Jaworowski static struct mtx pcicfg_mtx;
4236975124cSRafal Jaworowski
424db5ef4fcSRafal Jaworowski static int
mv_pcib_probe(device_t self)425db5ef4fcSRafal Jaworowski mv_pcib_probe(device_t self)
4266975124cSRafal Jaworowski {
4271b96faf8SMarcel Moolenaar phandle_t node;
4286975124cSRafal Jaworowski
4291b96faf8SMarcel Moolenaar node = ofw_bus_get_node(self);
430626a1983SAndrew Turner if (!mv_fdt_is_type(node, "pci"))
431db5ef4fcSRafal Jaworowski return (ENXIO);
4321b96faf8SMarcel Moolenaar
433c826a643SNathan Whitehorn if (!(ofw_bus_is_compatible(self, "mrvl,pcie") ||
434c7dbc00cSMarcin Wojtas ofw_bus_is_compatible(self, "mrvl,pci") ||
435c7dbc00cSMarcin Wojtas ofw_bus_node_is_compatible(
436c7dbc00cSMarcin Wojtas OF_parent(node), "marvell,armada-370-pcie")))
437db5ef4fcSRafal Jaworowski return (ENXIO);
4386975124cSRafal Jaworowski
439afffcaa1SOleksandr Tymoshenko if (!ofw_bus_status_okay(self))
440afffcaa1SOleksandr Tymoshenko return (ENXIO);
441afffcaa1SOleksandr Tymoshenko
442db5ef4fcSRafal Jaworowski device_set_desc(self, "Marvell Integrated PCI/PCI-E Controller");
443db5ef4fcSRafal Jaworowski return (BUS_PROBE_DEFAULT);
444db5ef4fcSRafal Jaworowski }
445db5ef4fcSRafal Jaworowski
446db5ef4fcSRafal Jaworowski static int
mv_pcib_attach(device_t self)447db5ef4fcSRafal Jaworowski mv_pcib_attach(device_t self)
448db5ef4fcSRafal Jaworowski {
449db5ef4fcSRafal Jaworowski struct mv_pcib_softc *sc;
450db5ef4fcSRafal Jaworowski phandle_t node, parnode;
45185958649SZbigniew Bodek uint32_t val, reg0;
45285958649SZbigniew Bodek int err, bus, devfn, port_id;
453db5ef4fcSRafal Jaworowski
454db5ef4fcSRafal Jaworowski sc = device_get_softc(self);
455db5ef4fcSRafal Jaworowski sc->sc_dev = self;
456db5ef4fcSRafal Jaworowski
4571b96faf8SMarcel Moolenaar node = ofw_bus_get_node(self);
4581b96faf8SMarcel Moolenaar parnode = OF_parent(node);
45985958649SZbigniew Bodek
46085958649SZbigniew Bodek if (OF_getencprop(node, "marvell,pcie-port", &(port_id),
46185958649SZbigniew Bodek sizeof(port_id)) <= 0) {
46285958649SZbigniew Bodek /* If port ID does not exist in the FDT set value to 0 */
46385958649SZbigniew Bodek if (!OF_hasprop(node, "marvell,pcie-port"))
46485958649SZbigniew Bodek port_id = 0;
46585958649SZbigniew Bodek else
46685958649SZbigniew Bodek return(ENXIO);
46785958649SZbigniew Bodek }
46885958649SZbigniew Bodek
4693a582d09SMarcin Wojtas sc->ap_segment = port_id;
4703a582d09SMarcin Wojtas
47187acb7f8SAndrew Turner if (ofw_bus_node_is_compatible(node, "mrvl,pcie")) {
472db5ef4fcSRafal Jaworowski sc->sc_type = MV_TYPE_PCIE;
47385958649SZbigniew Bodek sc->sc_win_target = MV_WIN_PCIE_TARGET(port_id);
47485958649SZbigniew Bodek sc->sc_mem_win_attr = MV_WIN_PCIE_MEM_ATTR(port_id);
47585958649SZbigniew Bodek sc->sc_io_win_attr = MV_WIN_PCIE_IO_ATTR(port_id);
476fefc2cf7SMarcin Wojtas sc->sc_skip_enable_procedure = 1;
477c7dbc00cSMarcin Wojtas } else if (ofw_bus_node_is_compatible(parnode, "marvell,armada-370-pcie")) {
478c7dbc00cSMarcin Wojtas sc->sc_type = MV_TYPE_PCIE;
479c7dbc00cSMarcin Wojtas sc->sc_win_target = MV_WIN_PCIE_TARGET_ARMADA38X(port_id);
480c7dbc00cSMarcin Wojtas sc->sc_mem_win_attr = MV_WIN_PCIE_MEM_ATTR_ARMADA38X(port_id);
481c7dbc00cSMarcin Wojtas sc->sc_io_win_attr = MV_WIN_PCIE_IO_ATTR_ARMADA38X(port_id);
482c7dbc00cSMarcin Wojtas sc->sc_enable_find_root_slot = 1;
48387acb7f8SAndrew Turner } else if (ofw_bus_node_is_compatible(node, "mrvl,pci")) {
484db5ef4fcSRafal Jaworowski sc->sc_type = MV_TYPE_PCI;
485e3ac9753SGrzegorz Bernacki sc->sc_win_target = MV_WIN_PCI_TARGET;
486db5ef4fcSRafal Jaworowski sc->sc_mem_win_attr = MV_WIN_PCI_MEM_ATTR;
487db5ef4fcSRafal Jaworowski sc->sc_io_win_attr = MV_WIN_PCI_IO_ATTR;
488db5ef4fcSRafal Jaworowski } else
489db5ef4fcSRafal Jaworowski return (ENXIO);
490db5ef4fcSRafal Jaworowski
491db5ef4fcSRafal Jaworowski /*
492db5ef4fcSRafal Jaworowski * Retrieve our mem-mapped registers range.
493db5ef4fcSRafal Jaworowski */
494db5ef4fcSRafal Jaworowski sc->sc_rid = 0;
495db5ef4fcSRafal Jaworowski sc->sc_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &sc->sc_rid,
496db5ef4fcSRafal Jaworowski RF_ACTIVE);
497db5ef4fcSRafal Jaworowski if (sc->sc_res == NULL) {
498db5ef4fcSRafal Jaworowski device_printf(self, "could not map memory\n");
499db5ef4fcSRafal Jaworowski return (ENXIO);
500db5ef4fcSRafal Jaworowski }
501db5ef4fcSRafal Jaworowski sc->sc_bst = rman_get_bustag(sc->sc_res);
502db5ef4fcSRafal Jaworowski sc->sc_bsh = rman_get_bushandle(sc->sc_res);
503db5ef4fcSRafal Jaworowski
504e3ac9753SGrzegorz Bernacki val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_CONTROL);
505e3ac9753SGrzegorz Bernacki sc->sc_mode = (val & PCIE_CONTROL_ROOT_CMPLX ? MV_MODE_ROOT :
506e3ac9753SGrzegorz Bernacki MV_MODE_ENDPOINT);
507e3ac9753SGrzegorz Bernacki
508e3ac9753SGrzegorz Bernacki /*
509e3ac9753SGrzegorz Bernacki * Get PCI interrupt info.
510e3ac9753SGrzegorz Bernacki */
511c826a643SNathan Whitehorn if (sc->sc_mode == MV_MODE_ROOT)
512c826a643SNathan Whitehorn ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(pcell_t));
513e3ac9753SGrzegorz Bernacki
514db5ef4fcSRafal Jaworowski /*
515db5ef4fcSRafal Jaworowski * Configure decode windows for PCI(E) access.
516db5ef4fcSRafal Jaworowski */
517db5ef4fcSRafal Jaworowski if (mv_pcib_decode_win(node, sc) != 0)
518db5ef4fcSRafal Jaworowski return (ENXIO);
519db5ef4fcSRafal Jaworowski
520db5ef4fcSRafal Jaworowski mv_pcib_hw_cfginit();
521db5ef4fcSRafal Jaworowski
522db5ef4fcSRafal Jaworowski /*
523e3ac9753SGrzegorz Bernacki * Enable PCIE device.
524e3ac9753SGrzegorz Bernacki */
52585958649SZbigniew Bodek mv_pcib_enable(sc, port_id);
526e3ac9753SGrzegorz Bernacki
527e3ac9753SGrzegorz Bernacki /*
528e3ac9753SGrzegorz Bernacki * Memory management.
529e3ac9753SGrzegorz Bernacki */
530e3ac9753SGrzegorz Bernacki err = mv_pcib_mem_init(sc);
531e3ac9753SGrzegorz Bernacki if (err)
532e3ac9753SGrzegorz Bernacki return (err);
533e3ac9753SGrzegorz Bernacki
53485958649SZbigniew Bodek /*
53585958649SZbigniew Bodek * Preliminary bus enumeration to find first linked devices and set
53685958649SZbigniew Bodek * appropriate bus number from which should start the actual enumeration
53785958649SZbigniew Bodek */
53885958649SZbigniew Bodek for (bus = 0; bus < PCI_BUSMAX; bus++) {
53985958649SZbigniew Bodek for (devfn = 0; devfn < mv_pcib_maxslots(self); devfn++) {
54085958649SZbigniew Bodek reg0 = mv_pcib_read_config(self, bus, devfn, devfn & 0x7, 0x0, 4);
54185958649SZbigniew Bodek if (reg0 == (~0U))
54285958649SZbigniew Bodek continue; /* no device */
54385958649SZbigniew Bodek else {
54485958649SZbigniew Bodek sc->sc_busnr = bus; /* update bus number */
54585958649SZbigniew Bodek break;
54685958649SZbigniew Bodek }
54785958649SZbigniew Bodek }
54885958649SZbigniew Bodek }
54985958649SZbigniew Bodek
550e3ac9753SGrzegorz Bernacki if (sc->sc_mode == MV_MODE_ROOT) {
551e3ac9753SGrzegorz Bernacki err = mv_pcib_init(sc, sc->sc_busnr,
552e3ac9753SGrzegorz Bernacki mv_pcib_maxslots(sc->sc_dev));
553e3ac9753SGrzegorz Bernacki if (err)
554e3ac9753SGrzegorz Bernacki goto error;
555e3ac9753SGrzegorz Bernacki
5565b56413dSWarner Losh device_add_child(self, "pci", DEVICE_UNIT_ANY);
557e3ac9753SGrzegorz Bernacki } else {
558e3ac9753SGrzegorz Bernacki sc->sc_devnr = 1;
559e3ac9753SGrzegorz Bernacki bus_space_write_4(sc->sc_bst, sc->sc_bsh,
560e3ac9753SGrzegorz Bernacki PCIE_REG_STATUS, 1 << PCIE_STATUS_DEV_OFFS);
5615b56413dSWarner Losh device_add_child(self, "pci_ep", DEVICE_UNIT_ANY);
562e3ac9753SGrzegorz Bernacki }
563e3ac9753SGrzegorz Bernacki
56464dc1cf3SGrzegorz Bernacki mtx_init(&sc->sc_msi_mtx, "msi_mtx", NULL, MTX_DEF);
565*18250ec6SJohn Baldwin bus_attach_children(self);
566*18250ec6SJohn Baldwin return (0);
567e3ac9753SGrzegorz Bernacki
568e3ac9753SGrzegorz Bernacki error:
569e3ac9753SGrzegorz Bernacki /* XXX SYS_RES_ should be released here */
570e3ac9753SGrzegorz Bernacki rman_fini(&sc->sc_mem_rman);
571e3ac9753SGrzegorz Bernacki rman_fini(&sc->sc_io_rman);
572e3ac9753SGrzegorz Bernacki
573e3ac9753SGrzegorz Bernacki return (err);
574e3ac9753SGrzegorz Bernacki }
575e3ac9753SGrzegorz Bernacki
576e3ac9753SGrzegorz Bernacki static void
mv_pcib_enable(struct mv_pcib_softc * sc,uint32_t unit)577e3ac9753SGrzegorz Bernacki mv_pcib_enable(struct mv_pcib_softc *sc, uint32_t unit)
578e3ac9753SGrzegorz Bernacki {
579e3ac9753SGrzegorz Bernacki uint32_t val;
580e3ac9753SGrzegorz Bernacki int timeout;
581e3ac9753SGrzegorz Bernacki
582fefc2cf7SMarcin Wojtas if (sc->sc_skip_enable_procedure)
583fefc2cf7SMarcin Wojtas goto pcib_enable_root_mode;
584fefc2cf7SMarcin Wojtas
585e3ac9753SGrzegorz Bernacki /*
586e3ac9753SGrzegorz Bernacki * Check if PCIE device is enabled.
587e3ac9753SGrzegorz Bernacki */
5884b1bfa3fSMarcin Wojtas if ((sc->sc_skip_enable_procedure == 0) &&
5894b1bfa3fSMarcin Wojtas (read_cpu_ctrl(CPU_CONTROL) & CPU_CONTROL_PCIE_DISABLE(unit))) {
590e3ac9753SGrzegorz Bernacki write_cpu_ctrl(CPU_CONTROL, read_cpu_ctrl(CPU_CONTROL) &
591e3ac9753SGrzegorz Bernacki ~(CPU_CONTROL_PCIE_DISABLE(unit)));
592e3ac9753SGrzegorz Bernacki
593e3ac9753SGrzegorz Bernacki timeout = PCIE_LINK_TIMEOUT;
594e3ac9753SGrzegorz Bernacki val = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
595e3ac9753SGrzegorz Bernacki PCIE_REG_STATUS);
596e3ac9753SGrzegorz Bernacki while (((val & PCIE_STATUS_LINK_DOWN) == 1) && (timeout > 0)) {
597e3ac9753SGrzegorz Bernacki DELAY(1000);
598e3ac9753SGrzegorz Bernacki timeout -= 1000;
599e3ac9753SGrzegorz Bernacki val = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
600e3ac9753SGrzegorz Bernacki PCIE_REG_STATUS);
601e3ac9753SGrzegorz Bernacki }
602e3ac9753SGrzegorz Bernacki }
603e3ac9753SGrzegorz Bernacki
604fefc2cf7SMarcin Wojtas pcib_enable_root_mode:
605e3ac9753SGrzegorz Bernacki if (sc->sc_mode == MV_MODE_ROOT) {
606e3ac9753SGrzegorz Bernacki /*
607db5ef4fcSRafal Jaworowski * Enable PCI bridge.
608db5ef4fcSRafal Jaworowski */
609e3ac9753SGrzegorz Bernacki val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIR_COMMAND);
610e3ac9753SGrzegorz Bernacki val |= PCIM_CMD_SERRESPEN | PCIM_CMD_BUSMASTEREN |
611e3ac9753SGrzegorz Bernacki PCIM_CMD_MEMEN | PCIM_CMD_PORTEN;
612e3ac9753SGrzegorz Bernacki bus_space_write_4(sc->sc_bst, sc->sc_bsh, PCIR_COMMAND, val);
613e3ac9753SGrzegorz Bernacki }
614e3ac9753SGrzegorz Bernacki }
615db5ef4fcSRafal Jaworowski
616e3ac9753SGrzegorz Bernacki static int
mv_pcib_mem_init(struct mv_pcib_softc * sc)617e3ac9753SGrzegorz Bernacki mv_pcib_mem_init(struct mv_pcib_softc *sc)
618e3ac9753SGrzegorz Bernacki {
619e3ac9753SGrzegorz Bernacki int err;
620db5ef4fcSRafal Jaworowski
621e3ac9753SGrzegorz Bernacki /*
622e3ac9753SGrzegorz Bernacki * Memory management.
623e3ac9753SGrzegorz Bernacki */
624db5ef4fcSRafal Jaworowski sc->sc_mem_rman.rm_type = RMAN_ARRAY;
625db5ef4fcSRafal Jaworowski err = rman_init(&sc->sc_mem_rman);
626db5ef4fcSRafal Jaworowski if (err)
627db5ef4fcSRafal Jaworowski return (err);
628db5ef4fcSRafal Jaworowski
629db5ef4fcSRafal Jaworowski sc->sc_io_rman.rm_type = RMAN_ARRAY;
630db5ef4fcSRafal Jaworowski err = rman_init(&sc->sc_io_rman);
631db5ef4fcSRafal Jaworowski if (err) {
632db5ef4fcSRafal Jaworowski rman_fini(&sc->sc_mem_rman);
633db5ef4fcSRafal Jaworowski return (err);
634db5ef4fcSRafal Jaworowski }
635db5ef4fcSRafal Jaworowski
636db5ef4fcSRafal Jaworowski err = rman_manage_region(&sc->sc_mem_rman, sc->sc_mem_base,
637db5ef4fcSRafal Jaworowski sc->sc_mem_base + sc->sc_mem_size - 1);
638db5ef4fcSRafal Jaworowski if (err)
639db5ef4fcSRafal Jaworowski goto error;
640db5ef4fcSRafal Jaworowski
641db5ef4fcSRafal Jaworowski err = rman_manage_region(&sc->sc_io_rman, sc->sc_io_base,
642db5ef4fcSRafal Jaworowski sc->sc_io_base + sc->sc_io_size - 1);
643db5ef4fcSRafal Jaworowski if (err)
644db5ef4fcSRafal Jaworowski goto error;
645db5ef4fcSRafal Jaworowski
646e3ac9753SGrzegorz Bernacki return (0);
647db5ef4fcSRafal Jaworowski
648db5ef4fcSRafal Jaworowski error:
649db5ef4fcSRafal Jaworowski rman_fini(&sc->sc_mem_rman);
650db5ef4fcSRafal Jaworowski rman_fini(&sc->sc_io_rman);
651e3ac9753SGrzegorz Bernacki
652db5ef4fcSRafal Jaworowski return (err);
653db5ef4fcSRafal Jaworowski }
654db5ef4fcSRafal Jaworowski
655e3ac9753SGrzegorz Bernacki static inline uint32_t
pcib_bit_get(uint32_t * map,uint32_t bit)656e3ac9753SGrzegorz Bernacki pcib_bit_get(uint32_t *map, uint32_t bit)
657e3ac9753SGrzegorz Bernacki {
658e3ac9753SGrzegorz Bernacki uint32_t n = bit / BITS_PER_UINT32;
659e3ac9753SGrzegorz Bernacki
660e3ac9753SGrzegorz Bernacki bit = bit % BITS_PER_UINT32;
661e3ac9753SGrzegorz Bernacki return (map[n] & (1 << bit));
662e3ac9753SGrzegorz Bernacki }
663e3ac9753SGrzegorz Bernacki
664e3ac9753SGrzegorz Bernacki static inline void
pcib_bit_set(uint32_t * map,uint32_t bit)665e3ac9753SGrzegorz Bernacki pcib_bit_set(uint32_t *map, uint32_t bit)
666e3ac9753SGrzegorz Bernacki {
667e3ac9753SGrzegorz Bernacki uint32_t n = bit / BITS_PER_UINT32;
668e3ac9753SGrzegorz Bernacki
669e3ac9753SGrzegorz Bernacki bit = bit % BITS_PER_UINT32;
670e3ac9753SGrzegorz Bernacki map[n] |= (1 << bit);
671e3ac9753SGrzegorz Bernacki }
672e3ac9753SGrzegorz Bernacki
673e3ac9753SGrzegorz Bernacki static inline uint32_t
pcib_map_check(uint32_t * map,uint32_t start,uint32_t bits)674e3ac9753SGrzegorz Bernacki pcib_map_check(uint32_t *map, uint32_t start, uint32_t bits)
675e3ac9753SGrzegorz Bernacki {
676e3ac9753SGrzegorz Bernacki uint32_t i;
677e3ac9753SGrzegorz Bernacki
678e3ac9753SGrzegorz Bernacki for (i = start; i < start + bits; i++)
679e3ac9753SGrzegorz Bernacki if (pcib_bit_get(map, i))
680e3ac9753SGrzegorz Bernacki return (0);
681e3ac9753SGrzegorz Bernacki
682e3ac9753SGrzegorz Bernacki return (1);
683e3ac9753SGrzegorz Bernacki }
684e3ac9753SGrzegorz Bernacki
685e3ac9753SGrzegorz Bernacki static inline void
pcib_map_set(uint32_t * map,uint32_t start,uint32_t bits)686e3ac9753SGrzegorz Bernacki pcib_map_set(uint32_t *map, uint32_t start, uint32_t bits)
687e3ac9753SGrzegorz Bernacki {
688e3ac9753SGrzegorz Bernacki uint32_t i;
689e3ac9753SGrzegorz Bernacki
690e3ac9753SGrzegorz Bernacki for (i = start; i < start + bits; i++)
691e3ac9753SGrzegorz Bernacki pcib_bit_set(map, i);
692e3ac9753SGrzegorz Bernacki }
693e3ac9753SGrzegorz Bernacki
694e3ac9753SGrzegorz Bernacki /*
695e3ac9753SGrzegorz Bernacki * The idea of this allocator is taken from ARM No-Cache memory
696e3ac9753SGrzegorz Bernacki * management code (sys/arm/arm/vm_machdep.c).
697e3ac9753SGrzegorz Bernacki */
698e3ac9753SGrzegorz Bernacki static bus_addr_t
pcib_alloc(struct mv_pcib_softc * sc,uint32_t smask)699e3ac9753SGrzegorz Bernacki pcib_alloc(struct mv_pcib_softc *sc, uint32_t smask)
700e3ac9753SGrzegorz Bernacki {
701e3ac9753SGrzegorz Bernacki uint32_t bits, bits_limit, i, *map, min_alloc, size;
702e3ac9753SGrzegorz Bernacki bus_addr_t addr = 0;
703e3ac9753SGrzegorz Bernacki bus_addr_t base;
704e3ac9753SGrzegorz Bernacki
705e3ac9753SGrzegorz Bernacki if (smask & 1) {
706e3ac9753SGrzegorz Bernacki base = sc->sc_io_base;
707e3ac9753SGrzegorz Bernacki min_alloc = PCI_MIN_IO_ALLOC;
708e3ac9753SGrzegorz Bernacki bits_limit = sc->sc_io_size / min_alloc;
709e3ac9753SGrzegorz Bernacki map = sc->sc_io_map;
710e3ac9753SGrzegorz Bernacki smask &= ~0x3;
711e3ac9753SGrzegorz Bernacki } else {
712e3ac9753SGrzegorz Bernacki base = sc->sc_mem_base;
713e3ac9753SGrzegorz Bernacki min_alloc = PCI_MIN_MEM_ALLOC;
714e3ac9753SGrzegorz Bernacki bits_limit = sc->sc_mem_size / min_alloc;
715e3ac9753SGrzegorz Bernacki map = sc->sc_mem_map;
716e3ac9753SGrzegorz Bernacki smask &= ~0xF;
717e3ac9753SGrzegorz Bernacki }
718e3ac9753SGrzegorz Bernacki
719e3ac9753SGrzegorz Bernacki size = ~smask + 1;
720e3ac9753SGrzegorz Bernacki bits = size / min_alloc;
721e3ac9753SGrzegorz Bernacki
722e3ac9753SGrzegorz Bernacki for (i = 0; i + bits <= bits_limit; i += bits)
723e3ac9753SGrzegorz Bernacki if (pcib_map_check(map, i, bits)) {
724e3ac9753SGrzegorz Bernacki pcib_map_set(map, i, bits);
725e3ac9753SGrzegorz Bernacki addr = base + (i * min_alloc);
726e3ac9753SGrzegorz Bernacki return (addr);
727e3ac9753SGrzegorz Bernacki }
728e3ac9753SGrzegorz Bernacki
729e3ac9753SGrzegorz Bernacki return (addr);
730e3ac9753SGrzegorz Bernacki }
731e3ac9753SGrzegorz Bernacki
732db5ef4fcSRafal Jaworowski static int
mv_pcib_init_bar(struct mv_pcib_softc * sc,int bus,int slot,int func,int barno)733db5ef4fcSRafal Jaworowski mv_pcib_init_bar(struct mv_pcib_softc *sc, int bus, int slot, int func,
734db5ef4fcSRafal Jaworowski int barno)
735db5ef4fcSRafal Jaworowski {
736e3ac9753SGrzegorz Bernacki uint32_t addr, bar;
737db5ef4fcSRafal Jaworowski int reg, width;
738db5ef4fcSRafal Jaworowski
739db5ef4fcSRafal Jaworowski reg = PCIR_BAR(barno);
740e3ac9753SGrzegorz Bernacki
741e3ac9753SGrzegorz Bernacki /*
742e3ac9753SGrzegorz Bernacki * Need to init the BAR register with 0xffffffff before correct
743e3ac9753SGrzegorz Bernacki * value can be read.
744e3ac9753SGrzegorz Bernacki */
745e3ac9753SGrzegorz Bernacki mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg, ~0, 4);
746db5ef4fcSRafal Jaworowski bar = mv_pcib_read_config(sc->sc_dev, bus, slot, func, reg, 4);
747db5ef4fcSRafal Jaworowski if (bar == 0)
748db5ef4fcSRafal Jaworowski return (1);
749db5ef4fcSRafal Jaworowski
750db5ef4fcSRafal Jaworowski /* Calculate BAR size: 64 or 32 bit (in 32-bit units) */
751db5ef4fcSRafal Jaworowski width = ((bar & 7) == 4) ? 2 : 1;
752db5ef4fcSRafal Jaworowski
753e3ac9753SGrzegorz Bernacki addr = pcib_alloc(sc, bar);
754e3ac9753SGrzegorz Bernacki if (!addr)
755db5ef4fcSRafal Jaworowski return (-1);
756db5ef4fcSRafal Jaworowski
757db5ef4fcSRafal Jaworowski if (bootverbose)
758e3ac9753SGrzegorz Bernacki printf("PCI %u:%u:%u: reg %x: smask=%08x: addr=%08x\n",
759e3ac9753SGrzegorz Bernacki bus, slot, func, reg, bar, addr);
760db5ef4fcSRafal Jaworowski
761db5ef4fcSRafal Jaworowski mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg, addr, 4);
762db5ef4fcSRafal Jaworowski if (width == 2)
763db5ef4fcSRafal Jaworowski mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg + 4,
764db5ef4fcSRafal Jaworowski 0, 4);
765db5ef4fcSRafal Jaworowski
766db5ef4fcSRafal Jaworowski return (width);
7676975124cSRafal Jaworowski }
7686975124cSRafal Jaworowski
7696975124cSRafal Jaworowski static void
mv_pcib_init_bridge(struct mv_pcib_softc * sc,int bus,int slot,int func)770db5ef4fcSRafal Jaworowski mv_pcib_init_bridge(struct mv_pcib_softc *sc, int bus, int slot, int func)
771db5ef4fcSRafal Jaworowski {
772db5ef4fcSRafal Jaworowski bus_addr_t io_base, mem_base;
773db5ef4fcSRafal Jaworowski uint32_t io_limit, mem_limit;
774db5ef4fcSRafal Jaworowski int secbus;
775db5ef4fcSRafal Jaworowski
776db5ef4fcSRafal Jaworowski io_base = sc->sc_io_base;
777db5ef4fcSRafal Jaworowski io_limit = io_base + sc->sc_io_size - 1;
778db5ef4fcSRafal Jaworowski mem_base = sc->sc_mem_base;
779db5ef4fcSRafal Jaworowski mem_limit = mem_base + sc->sc_mem_size - 1;
780db5ef4fcSRafal Jaworowski
781db5ef4fcSRafal Jaworowski /* Configure I/O decode registers */
782db5ef4fcSRafal Jaworowski mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOBASEL_1,
783db5ef4fcSRafal Jaworowski io_base >> 8, 1);
784db5ef4fcSRafal Jaworowski mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOBASEH_1,
785db5ef4fcSRafal Jaworowski io_base >> 16, 2);
786db5ef4fcSRafal Jaworowski mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOLIMITL_1,
787db5ef4fcSRafal Jaworowski io_limit >> 8, 1);
788db5ef4fcSRafal Jaworowski mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOLIMITH_1,
789db5ef4fcSRafal Jaworowski io_limit >> 16, 2);
790db5ef4fcSRafal Jaworowski
791db5ef4fcSRafal Jaworowski /* Configure memory decode registers */
792db5ef4fcSRafal Jaworowski mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_MEMBASE_1,
793db5ef4fcSRafal Jaworowski mem_base >> 16, 2);
794db5ef4fcSRafal Jaworowski mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_MEMLIMIT_1,
795db5ef4fcSRafal Jaworowski mem_limit >> 16, 2);
796db5ef4fcSRafal Jaworowski
797db5ef4fcSRafal Jaworowski /* Disable memory prefetch decode */
798db5ef4fcSRafal Jaworowski mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMBASEL_1,
799db5ef4fcSRafal Jaworowski 0x10, 2);
800db5ef4fcSRafal Jaworowski mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMBASEH_1,
801db5ef4fcSRafal Jaworowski 0x0, 4);
802db5ef4fcSRafal Jaworowski mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMLIMITL_1,
803db5ef4fcSRafal Jaworowski 0xF, 2);
804db5ef4fcSRafal Jaworowski mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMLIMITH_1,
805db5ef4fcSRafal Jaworowski 0x0, 4);
806db5ef4fcSRafal Jaworowski
807db5ef4fcSRafal Jaworowski secbus = mv_pcib_read_config(sc->sc_dev, bus, slot, func,
808db5ef4fcSRafal Jaworowski PCIR_SECBUS_1, 1);
809db5ef4fcSRafal Jaworowski
810db5ef4fcSRafal Jaworowski /* Configure buses behind the bridge */
811db5ef4fcSRafal Jaworowski mv_pcib_init(sc, secbus, PCI_SLOTMAX);
812db5ef4fcSRafal Jaworowski }
813db5ef4fcSRafal Jaworowski
814db5ef4fcSRafal Jaworowski static int
mv_pcib_init(struct mv_pcib_softc * sc,int bus,int maxslot)815db5ef4fcSRafal Jaworowski mv_pcib_init(struct mv_pcib_softc *sc, int bus, int maxslot)
816db5ef4fcSRafal Jaworowski {
817db5ef4fcSRafal Jaworowski int slot, func, maxfunc, error;
818db5ef4fcSRafal Jaworowski uint8_t hdrtype, command, class, subclass;
819db5ef4fcSRafal Jaworowski
820db5ef4fcSRafal Jaworowski for (slot = 0; slot <= maxslot; slot++) {
821db5ef4fcSRafal Jaworowski maxfunc = 0;
822db5ef4fcSRafal Jaworowski for (func = 0; func <= maxfunc; func++) {
823db5ef4fcSRafal Jaworowski hdrtype = mv_pcib_read_config(sc->sc_dev, bus, slot,
824db5ef4fcSRafal Jaworowski func, PCIR_HDRTYPE, 1);
825db5ef4fcSRafal Jaworowski
826db5ef4fcSRafal Jaworowski if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
827db5ef4fcSRafal Jaworowski continue;
828db5ef4fcSRafal Jaworowski
829db5ef4fcSRafal Jaworowski if (func == 0 && (hdrtype & PCIM_MFDEV))
830db5ef4fcSRafal Jaworowski maxfunc = PCI_FUNCMAX;
831db5ef4fcSRafal Jaworowski
832db5ef4fcSRafal Jaworowski command = mv_pcib_read_config(sc->sc_dev, bus, slot,
833db5ef4fcSRafal Jaworowski func, PCIR_COMMAND, 1);
834db5ef4fcSRafal Jaworowski command &= ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN);
835db5ef4fcSRafal Jaworowski mv_pcib_write_config(sc->sc_dev, bus, slot, func,
836db5ef4fcSRafal Jaworowski PCIR_COMMAND, command, 1);
837db5ef4fcSRafal Jaworowski
838db5ef4fcSRafal Jaworowski error = mv_pcib_init_all_bars(sc, bus, slot, func,
839db5ef4fcSRafal Jaworowski hdrtype);
840db5ef4fcSRafal Jaworowski
841db5ef4fcSRafal Jaworowski if (error)
842db5ef4fcSRafal Jaworowski return (error);
843db5ef4fcSRafal Jaworowski
844db5ef4fcSRafal Jaworowski command |= PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN |
845db5ef4fcSRafal Jaworowski PCIM_CMD_PORTEN;
846db5ef4fcSRafal Jaworowski mv_pcib_write_config(sc->sc_dev, bus, slot, func,
847db5ef4fcSRafal Jaworowski PCIR_COMMAND, command, 1);
848db5ef4fcSRafal Jaworowski
849db5ef4fcSRafal Jaworowski /* Handle PCI-PCI bridges */
850db5ef4fcSRafal Jaworowski class = mv_pcib_read_config(sc->sc_dev, bus, slot,
851db5ef4fcSRafal Jaworowski func, PCIR_CLASS, 1);
852db5ef4fcSRafal Jaworowski subclass = mv_pcib_read_config(sc->sc_dev, bus, slot,
853db5ef4fcSRafal Jaworowski func, PCIR_SUBCLASS, 1);
854db5ef4fcSRafal Jaworowski
855db5ef4fcSRafal Jaworowski if (class != PCIC_BRIDGE ||
856db5ef4fcSRafal Jaworowski subclass != PCIS_BRIDGE_PCI)
857db5ef4fcSRafal Jaworowski continue;
858db5ef4fcSRafal Jaworowski
859db5ef4fcSRafal Jaworowski mv_pcib_init_bridge(sc, bus, slot, func);
860db5ef4fcSRafal Jaworowski }
861db5ef4fcSRafal Jaworowski }
862db5ef4fcSRafal Jaworowski
863db5ef4fcSRafal Jaworowski /* Enable all ABCD interrupts */
864db5ef4fcSRafal Jaworowski pcib_write_irq_mask(sc, (0xF << 24));
865db5ef4fcSRafal Jaworowski
866db5ef4fcSRafal Jaworowski return (0);
867db5ef4fcSRafal Jaworowski }
868db5ef4fcSRafal Jaworowski
869db5ef4fcSRafal Jaworowski static int
mv_pcib_init_all_bars(struct mv_pcib_softc * sc,int bus,int slot,int func,int hdrtype)870db5ef4fcSRafal Jaworowski mv_pcib_init_all_bars(struct mv_pcib_softc *sc, int bus, int slot,
871db5ef4fcSRafal Jaworowski int func, int hdrtype)
872db5ef4fcSRafal Jaworowski {
873db5ef4fcSRafal Jaworowski int maxbar, bar, i;
874db5ef4fcSRafal Jaworowski
875db5ef4fcSRafal Jaworowski maxbar = (hdrtype & PCIM_HDRTYPE) ? 0 : 6;
876db5ef4fcSRafal Jaworowski bar = 0;
877db5ef4fcSRafal Jaworowski
878db5ef4fcSRafal Jaworowski /* Program the base address registers */
879db5ef4fcSRafal Jaworowski while (bar < maxbar) {
880db5ef4fcSRafal Jaworowski i = mv_pcib_init_bar(sc, bus, slot, func, bar);
881db5ef4fcSRafal Jaworowski bar += i;
882db5ef4fcSRafal Jaworowski if (i < 0) {
883db5ef4fcSRafal Jaworowski device_printf(sc->sc_dev,
884db5ef4fcSRafal Jaworowski "PCI IO/Memory space exhausted\n");
885db5ef4fcSRafal Jaworowski return (ENOMEM);
886db5ef4fcSRafal Jaworowski }
887db5ef4fcSRafal Jaworowski }
888db5ef4fcSRafal Jaworowski
889db5ef4fcSRafal Jaworowski return (0);
890db5ef4fcSRafal Jaworowski }
891db5ef4fcSRafal Jaworowski
8924e1d94d9SJohn Baldwin static struct rman *
mv_pcib_get_rman(device_t dev,int type,u_int flags)8934e1d94d9SJohn Baldwin mv_pcib_get_rman(device_t dev, int type, u_int flags)
8944e1d94d9SJohn Baldwin {
8954e1d94d9SJohn Baldwin struct mv_pcib_softc *sc = device_get_softc(dev);
8964e1d94d9SJohn Baldwin
8974e1d94d9SJohn Baldwin switch (type) {
8984e1d94d9SJohn Baldwin case SYS_RES_IOPORT:
8994e1d94d9SJohn Baldwin return (&sc->sc_io_rman);
9004e1d94d9SJohn Baldwin case SYS_RES_MEMORY:
9014e1d94d9SJohn Baldwin return (&sc->sc_mem_rman);
9024e1d94d9SJohn Baldwin default:
9034e1d94d9SJohn Baldwin return (NULL);
9044e1d94d9SJohn Baldwin }
9054e1d94d9SJohn Baldwin }
9064e1d94d9SJohn Baldwin
907db5ef4fcSRafal Jaworowski static struct resource *
mv_pcib_alloc_resource(device_t dev,device_t child,int type,int * rid,rman_res_t start,rman_res_t end,rman_res_t count,u_int flags)908db5ef4fcSRafal Jaworowski mv_pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
9092dd1bdf1SJustin Hibbits rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
910db5ef4fcSRafal Jaworowski {
911db5ef4fcSRafal Jaworowski struct mv_pcib_softc *sc = device_get_softc(dev);
912db5ef4fcSRafal Jaworowski
913db5ef4fcSRafal Jaworowski switch (type) {
914db5ef4fcSRafal Jaworowski case SYS_RES_IOPORT:
915db5ef4fcSRafal Jaworowski case SYS_RES_MEMORY:
916db5ef4fcSRafal Jaworowski break;
9173a582d09SMarcin Wojtas case PCI_RES_BUS:
9183a582d09SMarcin Wojtas return (pci_domain_alloc_bus(sc->ap_segment, child, rid, start,
9193a582d09SMarcin Wojtas end, count, flags));
920db5ef4fcSRafal Jaworowski default:
921e3ac9753SGrzegorz Bernacki return (BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
922db5ef4fcSRafal Jaworowski type, rid, start, end, count, flags));
92374b8d63dSPedro F. Giffuni }
924db5ef4fcSRafal Jaworowski
9257915adb5SJustin Hibbits if (RMAN_IS_DEFAULT_RANGE(start, end)) {
926e3ac9753SGrzegorz Bernacki start = sc->sc_mem_base;
927e3ac9753SGrzegorz Bernacki end = sc->sc_mem_base + sc->sc_mem_size - 1;
928e3ac9753SGrzegorz Bernacki count = sc->sc_mem_size;
929e3ac9753SGrzegorz Bernacki }
930e3ac9753SGrzegorz Bernacki
931e3ac9753SGrzegorz Bernacki if ((start < sc->sc_mem_base) || (start + count - 1 != end) ||
932e3ac9753SGrzegorz Bernacki (end > sc->sc_mem_base + sc->sc_mem_size - 1))
933e3ac9753SGrzegorz Bernacki return (NULL);
934e3ac9753SGrzegorz Bernacki
9354e1d94d9SJohn Baldwin return (bus_generic_rman_alloc_resource(dev, child, type, rid,
9364e1d94d9SJohn Baldwin start, end, count, flags));
937db5ef4fcSRafal Jaworowski }
938db5ef4fcSRafal Jaworowski
9394e1d94d9SJohn Baldwin static int
mv_pcib_adjust_resource(device_t dev,device_t child,struct resource * r,rman_res_t start,rman_res_t end)940fef01f04SJohn Baldwin mv_pcib_adjust_resource(device_t dev, device_t child,
9414e1d94d9SJohn Baldwin struct resource *r, rman_res_t start, rman_res_t end)
9424e1d94d9SJohn Baldwin {
9434e1d94d9SJohn Baldwin struct mv_pcib_softc *sc = device_get_softc(dev);
9444e1d94d9SJohn Baldwin
945fef01f04SJohn Baldwin switch (rman_get_type(r)) {
9464e1d94d9SJohn Baldwin case SYS_RES_IOPORT:
9474e1d94d9SJohn Baldwin case SYS_RES_MEMORY:
948fef01f04SJohn Baldwin return (bus_generic_rman_adjust_resource(dev, child, r, start,
949fef01f04SJohn Baldwin end));
9504e1d94d9SJohn Baldwin case PCI_RES_BUS:
9514e1d94d9SJohn Baldwin return (pci_domain_adjust_bus(sc->ap_segment, child, r, start,
9524e1d94d9SJohn Baldwin end));
9534e1d94d9SJohn Baldwin default:
954fef01f04SJohn Baldwin return (bus_generic_adjust_resource(dev, child, r, start, end));
9554e1d94d9SJohn Baldwin }
956db5ef4fcSRafal Jaworowski }
957db5ef4fcSRafal Jaworowski
958db5ef4fcSRafal Jaworowski static int
mv_pcib_release_resource(device_t dev,device_t child,struct resource * res)9599dbf5b0eSJohn Baldwin mv_pcib_release_resource(device_t dev, device_t child, struct resource *res)
960db5ef4fcSRafal Jaworowski {
9613a582d09SMarcin Wojtas struct mv_pcib_softc *sc = device_get_softc(dev);
962db5ef4fcSRafal Jaworowski
9639dbf5b0eSJohn Baldwin switch (rman_get_type(res)) {
9644e1d94d9SJohn Baldwin case SYS_RES_IOPORT:
9654e1d94d9SJohn Baldwin case SYS_RES_MEMORY:
9669dbf5b0eSJohn Baldwin return (bus_generic_rman_release_resource(dev, child, res));
9674e1d94d9SJohn Baldwin case PCI_RES_BUS:
9689dbf5b0eSJohn Baldwin return (pci_domain_release_bus(sc->ap_segment, child, res));
9694e1d94d9SJohn Baldwin default:
9709dbf5b0eSJohn Baldwin return (bus_generic_release_resource(dev, child, res));
9714e1d94d9SJohn Baldwin }
9724e1d94d9SJohn Baldwin }
973db5ef4fcSRafal Jaworowski
9744e1d94d9SJohn Baldwin static int
mv_pcib_activate_resource(device_t dev,device_t child,struct resource * r)9752baed46eSJohn Baldwin mv_pcib_activate_resource(device_t dev, device_t child, struct resource *r)
9764e1d94d9SJohn Baldwin {
9774e1d94d9SJohn Baldwin struct mv_pcib_softc *sc = device_get_softc(dev);
9784e1d94d9SJohn Baldwin
9792baed46eSJohn Baldwin switch (rman_get_type(r)) {
9804e1d94d9SJohn Baldwin case SYS_RES_IOPORT:
9814e1d94d9SJohn Baldwin case SYS_RES_MEMORY:
9822baed46eSJohn Baldwin return (bus_generic_rman_activate_resource(dev, child, r));
9834e1d94d9SJohn Baldwin case PCI_RES_BUS:
9842baed46eSJohn Baldwin return (pci_domain_activate_bus(sc->ap_segment, child, r));
9854e1d94d9SJohn Baldwin default:
9862baed46eSJohn Baldwin return (bus_generic_activate_resource(dev, child, r));
9874e1d94d9SJohn Baldwin }
9884e1d94d9SJohn Baldwin }
9894e1d94d9SJohn Baldwin
9904e1d94d9SJohn Baldwin static int
mv_pcib_deactivate_resource(device_t dev,device_t child,struct resource * r)9912baed46eSJohn Baldwin mv_pcib_deactivate_resource(device_t dev, device_t child, struct resource *r)
9924e1d94d9SJohn Baldwin {
9934e1d94d9SJohn Baldwin struct mv_pcib_softc *sc = device_get_softc(dev);
9944e1d94d9SJohn Baldwin
9952baed46eSJohn Baldwin switch (rman_get_type(r)) {
9964e1d94d9SJohn Baldwin case SYS_RES_IOPORT:
9974e1d94d9SJohn Baldwin case SYS_RES_MEMORY:
9982baed46eSJohn Baldwin return (bus_generic_rman_deactivate_resource(dev, child, r));
9994e1d94d9SJohn Baldwin case PCI_RES_BUS:
10002baed46eSJohn Baldwin return (pci_domain_deactivate_bus(sc->ap_segment, child, r));
10014e1d94d9SJohn Baldwin default:
10022baed46eSJohn Baldwin return (bus_generic_deactivate_resource(dev, child, r));
10034e1d94d9SJohn Baldwin }
10044e1d94d9SJohn Baldwin }
10054e1d94d9SJohn Baldwin
10064e1d94d9SJohn Baldwin static int
mv_pcib_map_resource(device_t dev,device_t child,struct resource * r,struct resource_map_request * argsp,struct resource_map * map)1007d77f2092SJohn Baldwin mv_pcib_map_resource(device_t dev, device_t child, struct resource *r,
10084e1d94d9SJohn Baldwin struct resource_map_request *argsp, struct resource_map *map)
10094e1d94d9SJohn Baldwin {
10104e1d94d9SJohn Baldwin struct resource_map_request args;
10114e1d94d9SJohn Baldwin rman_res_t length, start;
10124e1d94d9SJohn Baldwin int error;
10134e1d94d9SJohn Baldwin
10144e1d94d9SJohn Baldwin /* Resources must be active to be mapped. */
10154e1d94d9SJohn Baldwin if (!(rman_get_flags(r) & RF_ACTIVE))
10164e1d94d9SJohn Baldwin return (ENXIO);
10174e1d94d9SJohn Baldwin
10184e1d94d9SJohn Baldwin /* Mappings are only supported on I/O and memory resources. */
1019d77f2092SJohn Baldwin switch (rman_get_type(r)) {
10204e1d94d9SJohn Baldwin case SYS_RES_IOPORT:
10214e1d94d9SJohn Baldwin case SYS_RES_MEMORY:
10224e1d94d9SJohn Baldwin break;
10234e1d94d9SJohn Baldwin default:
10244e1d94d9SJohn Baldwin return (EINVAL);
10254e1d94d9SJohn Baldwin }
10264e1d94d9SJohn Baldwin
10274e1d94d9SJohn Baldwin resource_init_map_request(&args);
10284e1d94d9SJohn Baldwin error = resource_validate_map_request(r, argsp, &args, &start, &length);
10294e1d94d9SJohn Baldwin if (error)
10304e1d94d9SJohn Baldwin return (error);
10314e1d94d9SJohn Baldwin
10324e1d94d9SJohn Baldwin map->r_bustag = fdtbus_bs_tag;
10334e1d94d9SJohn Baldwin map->r_bushandle = start;
10344e1d94d9SJohn Baldwin map->r_size = length;
10354e1d94d9SJohn Baldwin return (0);
10364e1d94d9SJohn Baldwin }
10374e1d94d9SJohn Baldwin
10384e1d94d9SJohn Baldwin static int
mv_pcib_unmap_resource(device_t dev,device_t child,struct resource * r,struct resource_map * map)1039d77f2092SJohn Baldwin mv_pcib_unmap_resource(device_t dev, device_t child, struct resource *r,
1040d77f2092SJohn Baldwin struct resource_map *map)
10414e1d94d9SJohn Baldwin {
1042d77f2092SJohn Baldwin switch (rman_get_type(r)) {
10434e1d94d9SJohn Baldwin case SYS_RES_IOPORT:
10444e1d94d9SJohn Baldwin case SYS_RES_MEMORY:
10454e1d94d9SJohn Baldwin return (0);
10464e1d94d9SJohn Baldwin default:
10474e1d94d9SJohn Baldwin return (EINVAL);
10484e1d94d9SJohn Baldwin }
1049db5ef4fcSRafal Jaworowski }
1050db5ef4fcSRafal Jaworowski
1051db5ef4fcSRafal Jaworowski static int
mv_pcib_read_ivar(device_t dev,device_t child,int which,uintptr_t * result)1052db5ef4fcSRafal Jaworowski mv_pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
1053db5ef4fcSRafal Jaworowski {
1054db5ef4fcSRafal Jaworowski struct mv_pcib_softc *sc = device_get_softc(dev);
1055db5ef4fcSRafal Jaworowski
1056db5ef4fcSRafal Jaworowski switch (which) {
1057db5ef4fcSRafal Jaworowski case PCIB_IVAR_BUS:
1058db5ef4fcSRafal Jaworowski *result = sc->sc_busnr;
1059db5ef4fcSRafal Jaworowski return (0);
1060db5ef4fcSRafal Jaworowski case PCIB_IVAR_DOMAIN:
1061db5ef4fcSRafal Jaworowski *result = device_get_unit(dev);
1062db5ef4fcSRafal Jaworowski return (0);
1063db5ef4fcSRafal Jaworowski }
1064db5ef4fcSRafal Jaworowski
1065db5ef4fcSRafal Jaworowski return (ENOENT);
1066db5ef4fcSRafal Jaworowski }
1067db5ef4fcSRafal Jaworowski
1068db5ef4fcSRafal Jaworowski static int
mv_pcib_write_ivar(device_t dev,device_t child,int which,uintptr_t value)1069db5ef4fcSRafal Jaworowski mv_pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
1070db5ef4fcSRafal Jaworowski {
1071db5ef4fcSRafal Jaworowski struct mv_pcib_softc *sc = device_get_softc(dev);
1072db5ef4fcSRafal Jaworowski
1073db5ef4fcSRafal Jaworowski switch (which) {
1074db5ef4fcSRafal Jaworowski case PCIB_IVAR_BUS:
1075db5ef4fcSRafal Jaworowski sc->sc_busnr = value;
1076db5ef4fcSRafal Jaworowski return (0);
1077db5ef4fcSRafal Jaworowski }
1078db5ef4fcSRafal Jaworowski
1079db5ef4fcSRafal Jaworowski return (ENOENT);
1080db5ef4fcSRafal Jaworowski }
1081db5ef4fcSRafal Jaworowski
1082db5ef4fcSRafal Jaworowski static inline void
pcib_write_irq_mask(struct mv_pcib_softc * sc,uint32_t mask)1083db5ef4fcSRafal Jaworowski pcib_write_irq_mask(struct mv_pcib_softc *sc, uint32_t mask)
1084db5ef4fcSRafal Jaworowski {
1085db5ef4fcSRafal Jaworowski
108626872c13SZbigniew Bodek if (sc->sc_type != MV_TYPE_PCIE)
1087db5ef4fcSRafal Jaworowski return;
1088db5ef4fcSRafal Jaworowski
1089db5ef4fcSRafal Jaworowski bus_space_write_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_IRQ_MASK, mask);
1090db5ef4fcSRafal Jaworowski }
1091db5ef4fcSRafal Jaworowski
1092db5ef4fcSRafal Jaworowski static void
mv_pcib_hw_cfginit(void)1093db5ef4fcSRafal Jaworowski mv_pcib_hw_cfginit(void)
10946975124cSRafal Jaworowski {
10956975124cSRafal Jaworowski static int opened = 0;
10966975124cSRafal Jaworowski
10976975124cSRafal Jaworowski if (opened)
10986975124cSRafal Jaworowski return;
10996975124cSRafal Jaworowski
11006975124cSRafal Jaworowski mtx_init(&pcicfg_mtx, "pcicfg", NULL, MTX_SPIN);
11016975124cSRafal Jaworowski opened = 1;
11026975124cSRafal Jaworowski }
11036975124cSRafal Jaworowski
11046975124cSRafal Jaworowski static uint32_t
mv_pcib_hw_cfgread(struct mv_pcib_softc * sc,u_int bus,u_int slot,u_int func,u_int reg,int bytes)1105db5ef4fcSRafal Jaworowski mv_pcib_hw_cfgread(struct mv_pcib_softc *sc, u_int bus, u_int slot,
11066975124cSRafal Jaworowski u_int func, u_int reg, int bytes)
11076975124cSRafal Jaworowski {
11086975124cSRafal Jaworowski uint32_t addr, data, ca, cd;
11096975124cSRafal Jaworowski
1110db5ef4fcSRafal Jaworowski ca = (sc->sc_type != MV_TYPE_PCI) ?
11116975124cSRafal Jaworowski PCIE_REG_CFG_ADDR : PCI_REG_CFG_ADDR;
1112db5ef4fcSRafal Jaworowski cd = (sc->sc_type != MV_TYPE_PCI) ?
11136975124cSRafal Jaworowski PCIE_REG_CFG_DATA : PCI_REG_CFG_DATA;
11146975124cSRafal Jaworowski addr = PCI_CFG_ENA | PCI_CFG_BUS(bus) | PCI_CFG_DEV(slot) |
11156975124cSRafal Jaworowski PCI_CFG_FUN(func) | PCI_CFG_PCIE_REG(reg);
11166975124cSRafal Jaworowski
11176975124cSRafal Jaworowski mtx_lock_spin(&pcicfg_mtx);
11186975124cSRafal Jaworowski bus_space_write_4(sc->sc_bst, sc->sc_bsh, ca, addr);
11196975124cSRafal Jaworowski
11206975124cSRafal Jaworowski data = ~0;
11216975124cSRafal Jaworowski switch (bytes) {
11226975124cSRafal Jaworowski case 1:
11236975124cSRafal Jaworowski data = bus_space_read_1(sc->sc_bst, sc->sc_bsh,
11246975124cSRafal Jaworowski cd + (reg & 3));
11256975124cSRafal Jaworowski break;
11266975124cSRafal Jaworowski case 2:
11276975124cSRafal Jaworowski data = le16toh(bus_space_read_2(sc->sc_bst, sc->sc_bsh,
11286975124cSRafal Jaworowski cd + (reg & 2)));
11296975124cSRafal Jaworowski break;
11306975124cSRafal Jaworowski case 4:
11316975124cSRafal Jaworowski data = le32toh(bus_space_read_4(sc->sc_bst, sc->sc_bsh,
11326975124cSRafal Jaworowski cd));
11336975124cSRafal Jaworowski break;
11346975124cSRafal Jaworowski }
11356975124cSRafal Jaworowski mtx_unlock_spin(&pcicfg_mtx);
11366975124cSRafal Jaworowski return (data);
11376975124cSRafal Jaworowski }
11386975124cSRafal Jaworowski
11396975124cSRafal Jaworowski static void
mv_pcib_hw_cfgwrite(struct mv_pcib_softc * sc,u_int bus,u_int slot,u_int func,u_int reg,uint32_t data,int bytes)1140db5ef4fcSRafal Jaworowski mv_pcib_hw_cfgwrite(struct mv_pcib_softc *sc, u_int bus, u_int slot,
11416975124cSRafal Jaworowski u_int func, u_int reg, uint32_t data, int bytes)
11426975124cSRafal Jaworowski {
11436975124cSRafal Jaworowski uint32_t addr, ca, cd;
11446975124cSRafal Jaworowski
1145db5ef4fcSRafal Jaworowski ca = (sc->sc_type != MV_TYPE_PCI) ?
11466975124cSRafal Jaworowski PCIE_REG_CFG_ADDR : PCI_REG_CFG_ADDR;
1147db5ef4fcSRafal Jaworowski cd = (sc->sc_type != MV_TYPE_PCI) ?
11486975124cSRafal Jaworowski PCIE_REG_CFG_DATA : PCI_REG_CFG_DATA;
11496975124cSRafal Jaworowski addr = PCI_CFG_ENA | PCI_CFG_BUS(bus) | PCI_CFG_DEV(slot) |
11506975124cSRafal Jaworowski PCI_CFG_FUN(func) | PCI_CFG_PCIE_REG(reg);
11516975124cSRafal Jaworowski
11526975124cSRafal Jaworowski mtx_lock_spin(&pcicfg_mtx);
11536975124cSRafal Jaworowski bus_space_write_4(sc->sc_bst, sc->sc_bsh, ca, addr);
11546975124cSRafal Jaworowski
11556975124cSRafal Jaworowski switch (bytes) {
11566975124cSRafal Jaworowski case 1:
11576975124cSRafal Jaworowski bus_space_write_1(sc->sc_bst, sc->sc_bsh,
11586975124cSRafal Jaworowski cd + (reg & 3), data);
11596975124cSRafal Jaworowski break;
11606975124cSRafal Jaworowski case 2:
11616975124cSRafal Jaworowski bus_space_write_2(sc->sc_bst, sc->sc_bsh,
11626975124cSRafal Jaworowski cd + (reg & 2), htole16(data));
11636975124cSRafal Jaworowski break;
11646975124cSRafal Jaworowski case 4:
11656975124cSRafal Jaworowski bus_space_write_4(sc->sc_bst, sc->sc_bsh,
11666975124cSRafal Jaworowski cd, htole32(data));
11676975124cSRafal Jaworowski break;
11686975124cSRafal Jaworowski }
11696975124cSRafal Jaworowski mtx_unlock_spin(&pcicfg_mtx);
11706975124cSRafal Jaworowski }
11716975124cSRafal Jaworowski
11726975124cSRafal Jaworowski static int
mv_pcib_maxslots(device_t dev)1173db5ef4fcSRafal Jaworowski mv_pcib_maxslots(device_t dev)
11746975124cSRafal Jaworowski {
1175db5ef4fcSRafal Jaworowski struct mv_pcib_softc *sc = device_get_softc(dev);
11766975124cSRafal Jaworowski
1177db5ef4fcSRafal Jaworowski return ((sc->sc_type != MV_TYPE_PCI) ? 1 : PCI_SLOTMAX);
11786975124cSRafal Jaworowski }
11796975124cSRafal Jaworowski
11801e92574fSZbigniew Bodek static int
mv_pcib_root_slot(device_t dev,u_int bus,u_int slot,u_int func)11811e92574fSZbigniew Bodek mv_pcib_root_slot(device_t dev, u_int bus, u_int slot, u_int func)
11821e92574fSZbigniew Bodek {
11831e92574fSZbigniew Bodek struct mv_pcib_softc *sc = device_get_softc(dev);
11841e92574fSZbigniew Bodek uint32_t vendor, device;
11851e92574fSZbigniew Bodek
1186fefc2cf7SMarcin Wojtas /* On platforms other than Armada38x, root link is always at slot 0 */
1187fefc2cf7SMarcin Wojtas if (!sc->sc_enable_find_root_slot)
1188fefc2cf7SMarcin Wojtas return (slot == 0);
1189fefc2cf7SMarcin Wojtas
11901e92574fSZbigniew Bodek vendor = mv_pcib_hw_cfgread(sc, bus, slot, func, PCIR_VENDOR,
11911e92574fSZbigniew Bodek PCIR_VENDOR_LENGTH);
11921e92574fSZbigniew Bodek device = mv_pcib_hw_cfgread(sc, bus, slot, func, PCIR_DEVICE,
11931e92574fSZbigniew Bodek PCIR_DEVICE_LENGTH) & MV_DEV_FAMILY_MASK;
11941e92574fSZbigniew Bodek
11951e92574fSZbigniew Bodek return (vendor == PCI_VENDORID_MRVL && device == MV_DEV_ARMADA38X);
11961e92574fSZbigniew Bodek }
11971e92574fSZbigniew Bodek
11986975124cSRafal Jaworowski static uint32_t
mv_pcib_read_config(device_t dev,u_int bus,u_int slot,u_int func,u_int reg,int bytes)1199db5ef4fcSRafal Jaworowski mv_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func,
12006975124cSRafal Jaworowski u_int reg, int bytes)
12016975124cSRafal Jaworowski {
1202db5ef4fcSRafal Jaworowski struct mv_pcib_softc *sc = device_get_softc(dev);
12036975124cSRafal Jaworowski
1204e3ac9753SGrzegorz Bernacki /* Return ~0 if link is inactive or trying to read from Root */
1205e3ac9753SGrzegorz Bernacki if ((bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_STATUS) &
12061e92574fSZbigniew Bodek PCIE_STATUS_LINK_DOWN) || mv_pcib_root_slot(dev, bus, slot, func))
12076975124cSRafal Jaworowski return (~0U);
12086975124cSRafal Jaworowski
1209db5ef4fcSRafal Jaworowski return (mv_pcib_hw_cfgread(sc, bus, slot, func, reg, bytes));
12106975124cSRafal Jaworowski }
12116975124cSRafal Jaworowski
12126975124cSRafal Jaworowski static void
mv_pcib_write_config(device_t dev,u_int bus,u_int slot,u_int func,u_int reg,uint32_t val,int bytes)1213db5ef4fcSRafal Jaworowski mv_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func,
12146975124cSRafal Jaworowski u_int reg, uint32_t val, int bytes)
12156975124cSRafal Jaworowski {
1216db5ef4fcSRafal Jaworowski struct mv_pcib_softc *sc = device_get_softc(dev);
12176975124cSRafal Jaworowski
1218e3ac9753SGrzegorz Bernacki /* Return if link is inactive or trying to write to Root */
1219e3ac9753SGrzegorz Bernacki if ((bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_STATUS) &
12201e92574fSZbigniew Bodek PCIE_STATUS_LINK_DOWN) || mv_pcib_root_slot(dev, bus, slot, func))
12216975124cSRafal Jaworowski return;
12226975124cSRafal Jaworowski
1223db5ef4fcSRafal Jaworowski mv_pcib_hw_cfgwrite(sc, bus, slot, func, reg, val, bytes);
12246975124cSRafal Jaworowski }
12256975124cSRafal Jaworowski
1226db5ef4fcSRafal Jaworowski static int
mv_pcib_route_interrupt(device_t bus,device_t dev,int pin)1227c826a643SNathan Whitehorn mv_pcib_route_interrupt(device_t bus, device_t dev, int pin)
12286975124cSRafal Jaworowski {
1229db5ef4fcSRafal Jaworowski struct mv_pcib_softc *sc;
1230c826a643SNathan Whitehorn struct ofw_pci_register reg;
1231bbc6da03SNathan Whitehorn uint32_t pintr, mintr[4];
1232bbc6da03SNathan Whitehorn int icells;
1233c826a643SNathan Whitehorn phandle_t iparent;
1234db5ef4fcSRafal Jaworowski
1235c826a643SNathan Whitehorn sc = device_get_softc(bus);
1236c826a643SNathan Whitehorn pintr = pin;
1237db5ef4fcSRafal Jaworowski
1238c826a643SNathan Whitehorn /* Fabricate imap information in case this isn't an OFW device */
1239c826a643SNathan Whitehorn bzero(®, sizeof(reg));
1240c826a643SNathan Whitehorn reg.phys_hi = (pci_get_bus(dev) << OFW_PCI_PHYS_HI_BUSSHIFT) |
1241c826a643SNathan Whitehorn (pci_get_slot(dev) << OFW_PCI_PHYS_HI_DEVICESHIFT) |
1242c826a643SNathan Whitehorn (pci_get_function(dev) << OFW_PCI_PHYS_HI_FUNCTIONSHIFT);
1243db5ef4fcSRafal Jaworowski
1244bbc6da03SNathan Whitehorn icells = ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo,
1245bbc6da03SNathan Whitehorn ®, sizeof(reg), &pintr, sizeof(pintr), mintr, sizeof(mintr),
1246bbc6da03SNathan Whitehorn &iparent);
1247bbc6da03SNathan Whitehorn if (icells > 0)
1248bbc6da03SNathan Whitehorn return (ofw_bus_map_intr(dev, iparent, icells, mintr));
1249c826a643SNathan Whitehorn
1250c826a643SNathan Whitehorn /* Maybe it's a real interrupt, not an intpin */
1251c826a643SNathan Whitehorn if (pin > 4)
1252c826a643SNathan Whitehorn return (pin);
1253c826a643SNathan Whitehorn
1254c826a643SNathan Whitehorn device_printf(bus, "could not route pin %d for device %d.%d\n",
1255db5ef4fcSRafal Jaworowski pin, pci_get_slot(dev), pci_get_function(dev));
1256db5ef4fcSRafal Jaworowski return (PCI_INVALID_IRQ);
1257db5ef4fcSRafal Jaworowski }
1258db5ef4fcSRafal Jaworowski
1259db5ef4fcSRafal Jaworowski static int
mv_pcib_decode_win(phandle_t node,struct mv_pcib_softc * sc)1260db5ef4fcSRafal Jaworowski mv_pcib_decode_win(phandle_t node, struct mv_pcib_softc *sc)
1261db5ef4fcSRafal Jaworowski {
126202c7dba9SIan Lepore struct mv_pci_range io_space, mem_space;
1263db5ef4fcSRafal Jaworowski device_t dev;
12646975124cSRafal Jaworowski int error;
12656975124cSRafal Jaworowski
1266db5ef4fcSRafal Jaworowski dev = sc->sc_dev;
1267db5ef4fcSRafal Jaworowski
126802c7dba9SIan Lepore if ((error = mv_pci_ranges(node, &io_space, &mem_space)) != 0) {
1269db5ef4fcSRafal Jaworowski device_printf(dev, "could not retrieve 'ranges' data\n");
1270db5ef4fcSRafal Jaworowski return (error);
1271db5ef4fcSRafal Jaworowski }
1272db5ef4fcSRafal Jaworowski
12736975124cSRafal Jaworowski /* Configure CPU decoding windows */
1274e3ac9753SGrzegorz Bernacki error = decode_win_cpu_set(sc->sc_win_target,
1275e3ac9753SGrzegorz Bernacki sc->sc_io_win_attr, io_space.base_parent, io_space.len, ~0);
12766975124cSRafal Jaworowski if (error < 0) {
1277db5ef4fcSRafal Jaworowski device_printf(dev, "could not set up CPU decode "
12786975124cSRafal Jaworowski "window for PCI IO\n");
1279db5ef4fcSRafal Jaworowski return (ENXIO);
12806975124cSRafal Jaworowski }
1281e3ac9753SGrzegorz Bernacki error = decode_win_cpu_set(sc->sc_win_target,
1282e3ac9753SGrzegorz Bernacki sc->sc_mem_win_attr, mem_space.base_parent, mem_space.len,
1283e3ac9753SGrzegorz Bernacki mem_space.base_parent);
12846975124cSRafal Jaworowski if (error < 0) {
1285db5ef4fcSRafal Jaworowski device_printf(dev, "could not set up CPU decode "
12866975124cSRafal Jaworowski "windows for PCI MEM\n");
1287db5ef4fcSRafal Jaworowski return (ENXIO);
12886975124cSRafal Jaworowski }
12896975124cSRafal Jaworowski
1290db5ef4fcSRafal Jaworowski sc->sc_io_base = io_space.base_parent;
1291db5ef4fcSRafal Jaworowski sc->sc_io_size = io_space.len;
1292db5ef4fcSRafal Jaworowski
1293db5ef4fcSRafal Jaworowski sc->sc_mem_base = mem_space.base_parent;
1294db5ef4fcSRafal Jaworowski sc->sc_mem_size = mem_space.len;
1295db5ef4fcSRafal Jaworowski
1296db5ef4fcSRafal Jaworowski return (0);
12976975124cSRafal Jaworowski }
12986975124cSRafal Jaworowski
129964dc1cf3SGrzegorz Bernacki static int
mv_pcib_map_msi(device_t dev,device_t child,int irq,uint64_t * addr,uint32_t * data)130064dc1cf3SGrzegorz Bernacki mv_pcib_map_msi(device_t dev, device_t child, int irq, uint64_t *addr,
130164dc1cf3SGrzegorz Bernacki uint32_t *data)
130264dc1cf3SGrzegorz Bernacki {
130364dc1cf3SGrzegorz Bernacki struct mv_pcib_softc *sc;
130464dc1cf3SGrzegorz Bernacki
130564dc1cf3SGrzegorz Bernacki sc = device_get_softc(dev);
1306fefc2cf7SMarcin Wojtas if (!sc->sc_msi_supported)
1307fefc2cf7SMarcin Wojtas return (ENOTSUP);
1308fefc2cf7SMarcin Wojtas
130964dc1cf3SGrzegorz Bernacki irq = irq - MSI_IRQ;
131064dc1cf3SGrzegorz Bernacki
131164dc1cf3SGrzegorz Bernacki /* validate parameters */
131264dc1cf3SGrzegorz Bernacki if (isclr(&sc->sc_msi_bitmap, irq)) {
131364dc1cf3SGrzegorz Bernacki device_printf(dev, "invalid MSI 0x%x\n", irq);
131464dc1cf3SGrzegorz Bernacki return (EINVAL);
131564dc1cf3SGrzegorz Bernacki }
131664dc1cf3SGrzegorz Bernacki
131764dc1cf3SGrzegorz Bernacki mv_msi_data(irq, addr, data);
131864dc1cf3SGrzegorz Bernacki
131964dc1cf3SGrzegorz Bernacki debugf("%s: irq: %d addr: %jx data: %x\n",
132064dc1cf3SGrzegorz Bernacki __func__, irq, *addr, *data);
132164dc1cf3SGrzegorz Bernacki
132264dc1cf3SGrzegorz Bernacki return (0);
132364dc1cf3SGrzegorz Bernacki }
132464dc1cf3SGrzegorz Bernacki
132564dc1cf3SGrzegorz Bernacki static int
mv_pcib_alloc_msi(device_t dev,device_t child,int count,int maxcount __unused,int * irqs)132664dc1cf3SGrzegorz Bernacki mv_pcib_alloc_msi(device_t dev, device_t child, int count,
132764dc1cf3SGrzegorz Bernacki int maxcount __unused, int *irqs)
132864dc1cf3SGrzegorz Bernacki {
132964dc1cf3SGrzegorz Bernacki struct mv_pcib_softc *sc;
133064dc1cf3SGrzegorz Bernacki u_int start = 0, i;
133164dc1cf3SGrzegorz Bernacki
1332fefc2cf7SMarcin Wojtas sc = device_get_softc(dev);
1333fefc2cf7SMarcin Wojtas if (!sc->sc_msi_supported)
1334fefc2cf7SMarcin Wojtas return (ENOTSUP);
1335fefc2cf7SMarcin Wojtas
133664dc1cf3SGrzegorz Bernacki if (powerof2(count) == 0 || count > MSI_IRQ_NUM)
133764dc1cf3SGrzegorz Bernacki return (EINVAL);
133864dc1cf3SGrzegorz Bernacki
133964dc1cf3SGrzegorz Bernacki mtx_lock(&sc->sc_msi_mtx);
134064dc1cf3SGrzegorz Bernacki
134164dc1cf3SGrzegorz Bernacki for (start = 0; (start + count) < MSI_IRQ_NUM; start++) {
134264dc1cf3SGrzegorz Bernacki for (i = start; i < start + count; i++) {
134364dc1cf3SGrzegorz Bernacki if (isset(&sc->sc_msi_bitmap, i))
134464dc1cf3SGrzegorz Bernacki break;
134564dc1cf3SGrzegorz Bernacki }
134664dc1cf3SGrzegorz Bernacki if (i == start + count)
134764dc1cf3SGrzegorz Bernacki break;
134864dc1cf3SGrzegorz Bernacki }
134964dc1cf3SGrzegorz Bernacki
135064dc1cf3SGrzegorz Bernacki if ((start + count) == MSI_IRQ_NUM) {
135164dc1cf3SGrzegorz Bernacki mtx_unlock(&sc->sc_msi_mtx);
135264dc1cf3SGrzegorz Bernacki return (ENXIO);
135364dc1cf3SGrzegorz Bernacki }
135464dc1cf3SGrzegorz Bernacki
135564dc1cf3SGrzegorz Bernacki for (i = start; i < start + count; i++) {
135664dc1cf3SGrzegorz Bernacki setbit(&sc->sc_msi_bitmap, i);
135789489567SZbigniew Bodek *irqs++ = MSI_IRQ + i;
135864dc1cf3SGrzegorz Bernacki }
135964dc1cf3SGrzegorz Bernacki debugf("%s: start: %x count: %x\n", __func__, start, count);
136064dc1cf3SGrzegorz Bernacki
136164dc1cf3SGrzegorz Bernacki mtx_unlock(&sc->sc_msi_mtx);
136264dc1cf3SGrzegorz Bernacki return (0);
136364dc1cf3SGrzegorz Bernacki }
136464dc1cf3SGrzegorz Bernacki
136564dc1cf3SGrzegorz Bernacki static int
mv_pcib_release_msi(device_t dev,device_t child,int count,int * irqs)136664dc1cf3SGrzegorz Bernacki mv_pcib_release_msi(device_t dev, device_t child, int count, int *irqs)
136764dc1cf3SGrzegorz Bernacki {
136864dc1cf3SGrzegorz Bernacki struct mv_pcib_softc *sc;
136964dc1cf3SGrzegorz Bernacki u_int i;
137064dc1cf3SGrzegorz Bernacki
137164dc1cf3SGrzegorz Bernacki sc = device_get_softc(dev);
1372fefc2cf7SMarcin Wojtas if(!sc->sc_msi_supported)
1373fefc2cf7SMarcin Wojtas return (ENOTSUP);
1374fefc2cf7SMarcin Wojtas
137564dc1cf3SGrzegorz Bernacki mtx_lock(&sc->sc_msi_mtx);
137664dc1cf3SGrzegorz Bernacki
137764dc1cf3SGrzegorz Bernacki for (i = 0; i < count; i++)
137864dc1cf3SGrzegorz Bernacki clrbit(&sc->sc_msi_bitmap, irqs[i] - MSI_IRQ);
137964dc1cf3SGrzegorz Bernacki
138064dc1cf3SGrzegorz Bernacki mtx_unlock(&sc->sc_msi_mtx);
138164dc1cf3SGrzegorz Bernacki return (0);
138264dc1cf3SGrzegorz Bernacki }
1383