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/freebsd/sys/dev/bxe/
H A Dbxe_dump.h33 #define DRV_DUMP_XSTORM_WAITP_ADDRESS 0x2b8a80
34 #define DRV_DUMP_TSTORM_WAITP_ADDRESS 0x1b8a80
35 #define DRV_DUMP_USTORM_WAITP_ADDRESS 0x338a80
36 #define DRV_DUMP_CSTORM_WAITP_ADDRESS 0x238a80
56 #define BNX2X_DUMP_VERSION 0x61111111
76 static const uint32_t page_vals_e2[] = {0, 128};
79 {0x58000, 4608, DUMP_CHIP_E2, 0x30}
85 static const uint32_t page_vals_e3[] = {0, 128};
88 {0x58000, 4608, DUMP_CHIP_E3A0 | DUMP_CHIP_E3B0, 0x30}
92 { 0x2000, 1, 0x1f, 0xfff},
[all …]
/freebsd/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300_aic.c50 #define ATH_AIC_MIN_ROT_DIR_ATT_DB 0
51 #define ATH_AIC_MIN_ROT_QUAD_ATT_DB 0
54 #define ATH_AIC_SRAM_AUTO_INCREMENT 0x80000000
55 #define ATH_AIC_SRAM_GAIN_TABLE_OFFSET 0x280
56 #define ATH_AIC_SRAM_CAL_OFFSET 0x140
59 #define ATH_AIC_BT_JUPITER_CTRL 0x66820
60 #define ATH_AIC_BT_AIC_ENABLE 0x02
64 0, 3, 9, 15, 21, 27};
79 0x00000, // 0
80 0x00000,
[all …]
/freebsd/sys/dev/vt/logo/
H A Dlogo_freebsd.c37 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0x00, 0x00,
38 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
39 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
40 0x00, 0x00, 0x00, 0x07, 0xff, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
41 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x00, 0x00,
42 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
43 0x0f, 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
44 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00,
45 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1f, 0xff, 0xfe,
46 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
[all …]
/freebsd/sys/crypto/des/
H A Ddes_setkey.c65 int des_check_key=0;
71 for (i=0; i<DES_KEY_SZ; i++) in des_set_odd_parity()
79 for (i=0; i<DES_KEY_SZ; i++) in des_check_key_parity()
82 return(0); in des_check_key_parity()
99 {0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01},
100 {0xFE,0xFE,0xFE,0xFE,0xFE,0xFE,0xFE,0xFE},
101 {0x1F,0x1F,0x1F,0x1F,0x0E,0x0E,0x0E,0x0E},
102 {0xE0,0xE0,0xE0,0xE0,0xF1,0xF1,0xF1,0xF1},
104 {0x01,0xFE,0x01,0xFE,0x01,0xFE,0x01,0xFE},
105 {0xFE,0x01,0xFE,0x01,0xFE,0x01,0xFE,0x01},
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8mp-debix-model-a.dts26 pinctrl-0 = <&pinctrl_gpio_led>;
28 led-0 {
39 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
50 pinctrl-0 = <&pinctrl_reg_usb_hub>;
77 pinctrl-0 = <&pinctrl_eqos>;
85 #size-cells = <0>;
87 ethphy0: ethernet-phy@0 { /* RTL8211E */
89 reg = <0>;
100 pinctrl-0 = <&pinctrl_i2c1>;
105 reg = <0x2
[all...]
H A Dimx8mm-innocomm-wb15-evk.dts22 pinctrl-0 = <&pinctrl_gpio_leds>;
24 led-0 {
34 pinctrl-0 = <&pinctrl_reg_vsd_3v3>;
45 pinctrl-0 = <&pinctrl_fec_phy_reg>;
56 pinctrl-0 = <&pinctrl_fec>;
64 #size-cells = <0>;
68 reg = <0x1>;
70 pinctrl-0 = <&pinctrl_fec_phy>;
106 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x03
107 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x03
[all …]
H A Dimx8mp-dhcom-som.dtsi23 reg = <0x0 0x40000000 0 0x08000000>;
40 gpio = <&gpio2 19 0>; /* SD2_RESET */
43 pinctrl-0 = <&pinctrl_usdhc2_vmmc>;
83 pinctrl-0 = <&pinctrl_ecspi1>;
90 pinctrl-0 = <&pinctrl_ecspi2>;
97 pinctrl-0 = <&pinctrl_eqos_rgmii>;
105 #size-cells = <0>;
[all...]
H A Dimx8mm-icore-mx8mm.dtsi30 pinctrl-0 = <&pinctrl_fec1>;
36 #size-cells = <0>;
50 pinctrl-0 = <&pinctrl_i2c1>;
55 reg = <0x08>;
148 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
149 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
150 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
151 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
152 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
153 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
[all …]
H A Dimx8mq-nitrogen-som.dtsi58 pinctrl-0 = <&pinctrl_fec1>;
65 #size-cells = <0>;
82 pinctrl-0 = <&pinctrl_i2c1>;
88 pinctrl-0 = <&pinctrl_i2c1_pca9546>;
89 reg = <0x70>;
92 #size-cells = <0>;
94 i2c1a: i2c@0 {
95 reg = <0>;
97 #size-cells = <0>;
101 reg = <0x60>;
[all …]
H A Dimx8mm-var-som-symphony.dts17 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
28 pinctrl-0 = <&pinctrl_reg_usb_otg2_vbus>;
63 gpios = <&pca9534 0 GPIO_ACTIVE_LOW>;
76 pinctrl-0 = <&pinctrl_i2c2>;
81 reg = <0x20>;
84 pinctrl-0 = <&pinctrl_pca9534>;
115 reg = <0x3d>;
119 pinctrl-0 = <&pinctrl_ptn5150>;
128 reg = <0x38>;
130 pinctrl-0 = <&pinctrl_captouch>;
[all …]
H A Dimx8mq-sr-som.dtsi20 pinctrl-0 = <&pinctrl_fec1>;
28 #size-cells = <0>;
41 pinctrl-0 = <&pinctrl_i2c1>;
47 reg = <0x08>;
131 reg = <0x50>;
146 pinctrl-0 = <&pinctrl_qspi>;
150 spi_flash: flash@0 {
153 reg = <0>;
162 pinctrl-0 = <&pinctrl_uart1>;
171 pinctrl-0
[all...]
H A Dimx8mp-msc-sm2s.dtsi25 pinctrl-0 = <&pinctrl_usb0_vbus>;
36 pinctrl-0 = <&pinctrl_usb1_vbus>;
46 pinctrl-0 = <&pinctrl_usdhc2_vmmc>;
70 lcd0_backlight: backlight-0 {
73 pinctrl-0 = <&pinctrl_lcd0_backlight>;
74 pwms = <&pwm1 0 100000 0>;
75 brightness-levels = <0 255>;
85 pinctrl-0 = <&pinctrl_lcd1_backlight>;
86 pwms = <&pwm2 0 10000
[all...]
/freebsd/sys/contrib/device-tree/Bindings/mmc/
H A Dcdns,sdhci.yaml36 # sampling clock. The delay starts from 5ns (for delay parameter equal to 0)
42 minimum: 0
43 maximum: 0x1f
48 minimum: 0
49 maximum: 0x1f
54 minimum: 0
55 maximum: 0x1f
60 minimum: 0
61 maximum: 0x1f
66 minimum: 0
[all …]
H A Dsdhci-am654.yaml64 minimum: 0
65 maximum: 0xf
70 minimum: 0
71 maximum: 0xf
76 minimum: 0
77 maximum: 0xf
82 minimum: 0
83 maximum: 0xf
88 minimum: 0
89 maximum: 0xf
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nvidia/
H A Dtegra30-cpu-opp.dtsi10 opp-supported-hw = <0x1F 0x31FE>;
16 opp-supported-hw = <0x1F 0x0C01>;
22 opp-supported-hw = <0x1F 0x0200>;
28 opp-supported-hw = <0x1F 0x31FE>;
34 opp-supported-hw = <0x1F 0x0C01>;
40 opp-supported-hw = <0x1F 0x0200>;
46 opp-supported-hw = <0x1F 0x31FE>;
53 opp-supported-hw = <0x1F 0x0C01>;
60 opp-supported-hw = <0x1F 0x0200>;
67 opp-supported-hw = <0x1F 0x0C00>;
[all …]
/freebsd/sys/dev/etherswitch/ar40xx/
H A Dar40xx_hw_psgmii.c88 0, sc->sc_psgmii_mem_size, BUS_SPACE_BARRIER_WRITE); in ar40xx_hw_psgmii_reg_write()
97 0, sc->sc_psgmii_mem_size, BUS_SPACE_BARRIER_READ); in ar40xx_hw_psgmii_reg_read()
109 0x2200); in ar40xx_hw_psgmii_set_mac_mode()
111 0x8380); in ar40xx_hw_psgmii_set_mac_mode()
117 return (0); in ar40xx_hw_psgmii_set_mac_mode()
130 MDIO_WRITEREG(sc->sc_mdio_dev, phy, 0x0, 0x9000); in ar40xx_hw_psgmii_single_phy_testing()
131 MDIO_WRITEREG(sc->sc_mdio_dev, phy, 0x0, 0x4140); in ar40xx_hw_psgmii_single_phy_testing()
133 for (j = 0; j < AR40XX_PSGMII_CALB_NUM; j++) { in ar40xx_hw_psgmii_single_phy_testing()
136 status = MDIO_READREG(sc->sc_mdio_dev, phy, 0x11); in ar40xx_hw_psgmii_single_phy_testing()
151 ar40xx_hw_phy_mmd_write(sc, phy, 7, 0x8029, 0x0000); in ar40xx_hw_psgmii_single_phy_testing()
[all …]
/freebsd/sys/gnu/dev/bwn/phy_n/
H A Dif_bwn_radio_2057.c81 { 0x0E, 0x20 }, { 0x31, 0x00 }, { 0x32, 0x00 }, { 0x33, 0x00 },
82 { 0x35, 0x26 }, { 0x3C, 0xff }, { 0x3D, 0xff }, { 0x3E, 0xff },
83 { 0x3F, 0xff }, { 0x62, 0x33 }, { 0x8A, 0xf0 }, { 0x8B, 0x10 },
84 { 0x8C, 0xf0 }, { 0x91, 0x3f }, { 0x92, 0x36 }, { 0xA4, 0x8c },
85 { 0xA8, 0x55 }, { 0xAF, 0x01 }, { 0x10F, 0xf0 }, { 0x110, 0x10 },
86 { 0x111, 0xf0 }, { 0x116, 0x3f }, { 0x117, 0x36 }, { 0x129, 0x8c },
87 { 0x12D, 0x55 }, { 0x134, 0x01 }, { 0x15E, 0x00 }, { 0x15F, 0x00 },
88 { 0x160, 0x00 }, { 0x161, 0x00 }, { 0x162, 0x00 }, { 0x163, 0x00 },
89 { 0x169, 0x02 }, { 0x16A, 0x00 }, { 0x16B, 0x00 }, { 0x16C, 0x00 },
90 { 0x1A4, 0x00 }, { 0x1A5, 0x00 }, { 0x1A6, 0x00 }, { 0x1AA, 0x00 },
[all …]
/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dmicrel.txt12 KSZ8001: register 0x1e, bits 15..14
13 KSZ8041: register 0x1e, bits 15..14
14 KSZ8021: register 0x1f, bits 5..4
15 KSZ8031: register 0x1f, bits 5..4
16 KSZ8051: register 0x1f, bits 5..4
17 KSZ8081: register 0x1f, bits 5..4
18 KSZ8091: register 0x1f, bits 5..4
19 LAN8814: register EP5.0, bit 6
/freebsd/crypto/openssl/crypto/des/
H A Dset_key.c63 for (i = 0; i < DES_KEY_SZ; i++) in DES_set_odd_parity()
69 * Return 1 if parity is okay and 0 if not.
76 for (i = 0; i < DES_KEY_SZ; i++) { in DES_check_key_parity()
96 {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01},
97 {0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE},
98 {0x1F, 0x1F, 0x1F, 0x1F, 0x0E, 0x0E, 0x0E, 0x0E},
99 {0xE0, 0xE0, 0xE0, 0xE0, 0xF1, 0xF1, 0xF1, 0xF1},
101 {0x01, 0xFE, 0x01, 0xFE, 0x01, 0xFE, 0x01, 0xFE},
102 {0xFE, 0x01, 0xFE, 0x01, 0xFE, 0x01, 0xFE, 0x01},
103 {0x1F, 0xE0, 0x1F, 0xE0, 0x0E, 0xF1, 0x0E, 0xF1},
[all …]
/freebsd/usr.sbin/bhyve/
H A Dpci_xhci.h32 #define PCI_USBREV 0x60 /* USB protocol revision */
71 #define XHCI_MAX_STREAMS_LOG 0
92 #define XHCI_SCTX_0_ROUTE_SET(x) ((x) & 0xFFFFF)
93 #define XHCI_SCTX_0_ROUTE_GET(x) ((x) & 0xFFFFF)
94 #define XHCI_SCTX_0_SPEED_SET(x) (((x) & 0xF) << 20)
95 #define XHCI_SCTX_0_SPEED_GET(x) (((x) >> 20) & 0xF)
96 #define XHCI_SCTX_0_MTT_SET(x) (((x) & 0x1) << 25)
97 #define XHCI_SCTX_0_MTT_GET(x) (((x) >> 25) & 0x1)
98 #define XHCI_SCTX_0_HUB_SET(x) (((x) & 0x1) << 26)
99 #define XHCI_SCTX_0_HUB_GET(x) (((x) >> 26) & 0x1)
[all …]
/freebsd/sys/dev/iicbus/pmic/rockchip/
H A Drk808.c48 {NULL, 0}
56 .enable_mask = 0x1,
58 .voltage_mask = 0x3F,
68 .enable_mask = 0x2,
70 .voltage_mask = 0x3F,
81 .enable_mask = 0x4,
87 .enable_mask = 0x8,
89 .voltage_mask = 0xF,
99 .enable_mask = 0x1,
101 .voltage_mask = 0x1F,
[all …]
/freebsd/sys/contrib/libsodium/test/default/
H A Dsign.c6 = { 0x42, 0x11, 0x51, 0xa4, 0x59, 0xfa, 0xea, 0xde, 0x3d, 0x24, 0x71,
7 0x15, 0xf9, 0x4a, 0xed, 0xae, 0x42, 0x31, 0x81, 0x24, 0x09, 0x5a,
8 0xfa, 0xbe, 0x4d, 0x14, 0x51, 0xa5, 0x59, 0xfa, 0xed, 0xee };
18 …0x9d,0x61,0xb1,0x9d,0xef,0xfd,0x5a,0x60,0xba,0x84,0x4a,0xf4,0x92,0xec,0x2c,0xc4,0x44,0x49,0xc5,0x6…
19 …0x4c,0xcd,0x08,0x9b,0x28,0xff,0x96,0xda,0x9d,0xb6,0xc3,0x46,0xec,0x11,0x4e,0x0f,0x5b,0x8a,0x31,0x9…
20 …0xc5,0xaa,0x8d,0xf4,0x3f,0x9f,0x83,0x7b,0xed,0xb7,0x44,0x2f,0x31,0xdc,0xb7,0xb1,0x66,0xd3,0x85,0x3…
21 …0x0d,0x4a,0x05,0xb0,0x73,0x52,0xa5,0x43,0x6e,0x18,0x03,0x56,0xda,0x0a,0xe6,0xef,0xa0,0x34,0x5f,0xf…
22 …0x6d,0xf9,0x34,0x0c,0x13,0x8c,0xc1,0x88,0xb5,0xfe,0x44,0x64,0xeb,0xaa,0x3f,0x7f,0xc2,0x06,0xa2,0xd…
23 …0xb7,0x80,0x38,0x1a,0x65,0xed,0xf8,0xb7,0x8f,0x69,0x45,0xe8,0xdb,0xec,0x79,0x41,0xac,0x04,0x9f,0xd…
24 …0x78,0xae,0x9e,0xff,0xe6,0xf2,0x45,0xe9,0x24,0xa7,0xbe,0x63,0x04,0x11,0x46,0xeb,0xc6,0x70,0xdb,0xd…
[all …]
/freebsd/sys/dev/vt/hw/vga/
H A Dvt_vga_reg.h32 * controller registers, can be located either at 0x3B0 or at 0x3D0 in I/O
34 * has the CRT controller registers at 0x3B0.
37 * interest anymore. As such, the CRT controller can be located at 0x3D0 in
45 * Richard F. Ferraro, Addison-Wesley, ISBN 0-201-62490-7
48 #define VGA_MEM_BASE 0xA0000
49 #define VGA_MEM_SIZE 0x10000
50 #define VGA_TXT_BASE 0xB8000
51 #define VGA_TXT_SIZE 0x08000
52 #define VGA_REG_BASE 0x3c0
53 #define VGA_REG_SIZE 0x10+0x0c
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dsdm845-wcd9340.dtsi14 #size-cells = <0>;
16 wcd9340_ifd: ifd@0,0 {
18 reg = <0 0>;
21 wcd9340: codec@1,0 {
23 reg = <1 0>;
35 #clock-cells = <0>;
39 pinctrl-0 = <&wcd_intr_default>;
54 reg = <0x4
[all...]
/freebsd/sys/dev/qlxgbe/
H A Dql_fw.c39 0x03, 0x00, 0x40, 0x40, 0x05, 0x04, 0x43, 0x00, 0x00, 0x00, 0x00, 0x00,
40 0xa8, 0x49, 0x1b, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
41 0x00, 0x00, 0x00, 0x00, 0xba, 0x8f, 0x63, 0x84, 0x2f, 0x5a, 0x19, 0xd4,
42 0x00, 0x00, 0x00, 0x00, 0x3e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
43 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
44 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
45 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
46 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
47 0xe0, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xf3, 0x03, 0x00,
48 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
[all …]

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