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/freebsd/lib/libpmc/pmu-events/arch/x86/jaketown/
H A Duncore-cache.json4 "Counter": "0,1,2,3",
11 "Counter": "0,1",
12 "EventCode": "0x34",
14 "Filter": "filter_state=0x1",
17 "UMask": "0x11",
22 "Counter": "0,1",
23 "EventCode": "0x37",
27 "UMask": "0x1",
32 "Counter": "0,1",
33 "EventCode": "0x35",
[all …]
/freebsd/sys/dev/clk/allwinner/
H A Dccu_h6_r.c55 CCU_RESET(RST_R_APB1_TIMER, 0x11c, 16)
56 CCU_RESET(RST_R_APB1_TWD, 0x12c, 16)
57 CCU_RESET(RST_R_APB1_PWM, 0x13c, 16)
58 CCU_RESET(RST_R_APB2_UART, 0x18c, 16)
59 CCU_RESET(RST_R_APB2_I2C, 0x19c, 16)
60 CCU_RESET(RST_R_APB1_IR, 0x1cc, 16)
61 CCU_RESET(RST_R_APB1_W1, 0x1ec, 16)
65 CCU_GATE(CLK_R_APB1_TIMER, "r_apb1-timer", "r_apb1", 0x11c, 0)
66 CCU_GATE(CLK_R_APB1_TWD, "r_apb1-twd", "r_apb1", 0x12c, 0)
67 CCU_GATE(CLK_R_APB1_PWM, "r_apb1-pwm", "r_apb1", 0x13c, 0)
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nxp/vf/
H A Dvf610-pinfunc.h14 #define ALT0 0x0
15 #define ALT1 0x1
16 #define ALT2 0x2
17 #define ALT3 0x3
18 #define ALT4 0x4
19 #define ALT5 0x5
20 #define ALT6 0x6
21 #define ALT7 0x7
24 #define VF610_PAD_PTA6__GPIO_0 0x000 0x000 ALT0 0x0
25 #define VF610_PAD_PTA6__RMII_CLKOUT 0x000 0x000 ALT1 0x0
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8mq-pinfunc.h15 #define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0…
16 #define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0…
17 #define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0…
18 #define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0…
19 #define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0…
20 #define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
21 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
22 #define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
23 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
24 #define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
[all …]
H A Dimx8mp-pinfunc.h13 #define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x014 0x274 0x000 0x0 0x0
14 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0
15 #define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0
16 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x014 0x274 0x000 0x6 0x0
17 #define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x018 0x278 0x000 0x0 0x0
18 #define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x0
19 #define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0
20 #define MX8MP_IOMUXC_GPIO1_IO01__CCM_EXT_CLK2 0x018 0x278 0x000 0x6 0x0
21 #define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02 0x01C 0x27C 0x000 0x0 0x0
22 #define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0
[all …]
H A Dimx8mm-pinfunc.h14 #define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
15 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
16 #define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
17 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
18 #define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
19 #define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0…
20 #define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0…
21 #define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0…
22 #define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0…
23 #define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0…
[all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/ivytown/
H A Duncore-cache.json4 "Counter": "0,1,2,3",
11 "Counter": "0,1",
12 "EventCode": "0x34",
14 "Filter": "filter_state=0x1",
17 "UMask": "0x11",
22 "Counter": "0,1",
23 "EventCode": "0x37",
27 "UMask": "0x1",
32 "Counter": "0,1",
33 "EventCode": "0x35",
[all …]
/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dqcom,edp-phy.yaml45 const: 0
67 reg = <0x0aec2a00 0x1c0>,
68 <0x0aec2200 0xa0>,
69 <0x0aec2600 0xa0>,
70 <0x0aec2000 0x19c>;
72 clocks = <&dispcc 0>, <&dispcc 1>;
76 #phy-cells = <0>;
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimxrt1050-pinfunc.h10 #define IMX_PAD_SION 0x40000000
17 #define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0
18 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0
19 #define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1
20 #define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0
21 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0
22 #define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0
24 #define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0
25 #define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0
26 #define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1
[all …]
H A Dimx50-pinfunc.h13 #define MX50_PAD_KEY_COL0__KPP_COL_0 0x020 0x2cc 0x000 0x0 0x0
14 #define MX50_PAD_KEY_COL0__GPIO4_0 0x020 0x2cc 0x000 0x1 0x0
15 #define MX50_PAD_KEY_COL0__EIM_NANDF_CLE 0x020 0x2cc 0x000 0x2 0x0
16 #define MX50_PAD_KEY_COL0__CTI_TRIGIN7 0x020 0x2cc 0x000 0x6 0x0
17 #define MX50_PAD_KEY_COL0__USBPHY1_TXREADY 0x020 0x2cc 0x000 0x7 0x0
18 #define MX50_PAD_KEY_ROW0__KPP_ROW_0 0x024 0x2d0 0x000 0x0 0x0
19 #define MX50_PAD_KEY_ROW0__GPIO4_1 0x024 0x2d0 0x000 0x1 0x0
20 #define MX50_PAD_KEY_ROW0__EIM_NANDF_ALE 0x024 0x2d0 0x000 0x2 0x0
21 #define MX50_PAD_KEY_ROW0__CTI_TRIGIN_ACK7 0x024 0x2d0 0x000 0x6 0x0
22 #define MX50_PAD_KEY_ROW0__USBPHY1_RXVALID 0x024 0x2d0 0x000 0x7 0x0
[all …]
H A Dimx25-pinfunc.h16 #define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000
17 #define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000
19 #define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000
20 #define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000
21 #define MX25_PAD_A13__LCDC_CLS 0x00c 0x22C 0x000 0x07 0x000
23 #define MX25_PAD_A14__A14 0x010 0x230 0x000 0x00 0x000
24 #define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x05 0x000
25 #define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x06 0x000
26 #define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x07 0x000
28 #define MX25_PAD_A15__A15 0x014 0x234 0x000 0x00 0x000
[all …]
H A Dimx6sl-pinfunc.h13 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0
14 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0
15 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0
16 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0
17 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0
18 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0
19 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0
20 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0
21 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0
22 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0
[all …]
H A Dimxrt1170-pinfunc.h10 #define IMX_PAD_SION 0x40000000
17 #define IOMUXC_GPIO_LPSR_00_FLEXCAN3_TX 0x000 0x040 0x0 0x0 0x0
18 #define IOMUXC_GPIO_LPSR_00_MIC_CLK 0x000 0x040 0x0 0x1 0x0
19 #define IOMUXC_GPIO_LPSR_00_MQS_RIGHT 0x000 0x040 0x0 0x2 0x0
20 #define IOMUXC_GPIO_LPSR_00_ARM_CM4_EVENTO 0x000 0x040 0x0 0x3 0x0
21 #define IOMUXC_GPIO_LPSR_00_GPIO_MUX6_IO00 0x000 0x040 0x0 0x5 0x0
22 #define IOMUXC_GPIO_LPSR_00_LPUART12_TXD 0x000 0x040 0x0B0 0x6 0x0
23 #define IOMUXC_GPIO_LPSR_00_SAI4_MCLK 0x000 0x040 0x0C8 0x7 0x0
24 #define IOMUXC_GPIO_LPSR_00_GPIO12_IO00 0x000 0x040 0x0 0xA 0x0
26 #define IOMUXC_GPIO_LPSR_01_FLEXCAN3_RX 0x004 0x044 0x080 0x0 0x0
[all …]
/freebsd/sys/contrib/device-tree/Bindings/display/rockchip/
H A Drockchip-vop.yaml107 reg = <0xff930000 0x19c>,
108 <0xff931000 0x1000>;
122 #size-cells = <0>;
123 vopb_out_edp: endpoint@0 {
124 reg = <0>;
/freebsd/tools/test/stress2/misc/
H A Dsyzkaller8.sh3 # panic: prot 0x3 is not subset of max_prot 0x5
4 # cpuid = 0
7 # db_trace_self_wrapper() at db_trace_self_wrapper+0x47/frame 0xfffffe0015fe8650
8 # vpanic() at vpanic+0x1c7/frame 0xfffffe0015fe86b0
9 # panic() at panic+0x43/frame 0xfffffe0015fe8710
10 # vm_map_insert() at vm_map_insert+0xa11/frame 0xfffffe0015fe87d0
11 # vm_map_fixed() at vm_map_fixed+0x19c/frame 0xfffffe0015fe8850
12 # vm_mmap_object() at vm_mmap_object+0x3be/frame 0xfffffe0015fe88e0
13 # shm_mmap() at shm_mmap+0x2e3/frame 0xfffffe0015fe8980
14 # kern_mmap_req() at kern_mmap_req+0xa72/frame 0xfffffe0015fe8a70
[all …]
H A Dkevent10.sh34 # panic: Assertion size > 0 failed at ../../../kern/subr_vmem.c:1082
38 # db_trace_self_wrapper() at db_trace_self_wrapper+0x2b/frame 0xfffffe0173117650
39 # vpanic() at vpanic+0x19c/frame 0xfffffe01731176d0
40 # kassert_panic() at kassert_panic+0x126/frame 0xfffffe0173117740
41 # vmem_alloc() at vmem_alloc+0x11b/frame 0xfffffe0173117780
42 # kmem_malloc() at kmem_malloc+0x33/frame 0xfffffe01731177b0
43 # uma_large_malloc() at uma_large_malloc+0x48/frame 0xfffffe01731177f0
44 # malloc() at malloc+0xe3/frame 0xfffffe0173117840
45 # ktrgenio() at ktrgenio+0x60/frame 0xfffffe0173117880
46 # sys_kevent() at sys_kevent+0x12f/frame 0xfffffe0173117930
[all …]
/freebsd/sys/dev/qat/include/
H A Dadf_gen4vf_hw_csr_data.h6 #define ADF_RING_CSR_ADDR_OFFSET_GEN4VF 0x0
7 #define ADF_RING_BUNDLE_SIZE_GEN4 0x2000
8 #define ADF_RING_CSR_RING_HEAD 0x0C0
9 #define ADF_RING_CSR_RING_TAIL 0x100
10 #define ADF_RING_CSR_E_STAT 0x14C
11 #define ADF_RING_CSR_RING_CONFIG_GEN4 0x1000
12 #define ADF_RING_CSR_RING_LBASE_GEN4 0x1040
13 #define ADF_RING_CSR_RING_UBASE_GEN4 0x1080
14 #define ADF_RING_CSR_INT_FLAG 0x170
15 #define ADF_RING_CSR_INT_FLAG_AND_COL 0x184
[all …]
/freebsd/usr.sbin/cxgbetool/
H A Dreg_defs_t4vf.c7 { "SGE_KDOORBELL", 0x000, 0 },
10 { "PIDX", 0, 14 },
11 { "SGE_GTS", 0x004, 0 },
15 { "CIDXInc", 0, 12 },
17 { NULL, 0, 0 }
21 { "SGE_VF_KDOORBELL", 0x000, 0 },
[all...]
/freebsd/sys/arm/freescale/imx/
H A Dimx6_anatopreg.h32 #define IMX6_ANALOG_CCM_PLL_ARM 0x000
33 #define IMX6_ANALOG_CCM_PLL_ARM_SET 0x004
34 #define IMX6_ANALOG_CCM_PLL_ARM_CLR 0x008
35 #define IMX6_ANALOG_CCM_PLL_ARM_TOG 0x00C
36 #define IMX6_ANALOG_CCM_PLL_ARM_DIV_MASK 0x7F
39 #define IMX6_ANALOG_CCM_PLL_ARM_CLK_SRC_MASK (0x03 << 16)
40 #define IMX6_ANALOG_CCM_PLL_USB1 0x010
41 #define IMX6_ANALOG_CCM_PLL_USB1_SET 0x014
42 #define IMX6_ANALOG_CCM_PLL_USB1_CLR 0x018
43 #define IMX6_ANALOG_CCM_PLL_USB1_TOG 0x01C
[all …]
/freebsd/sys/dev/qat/include/common/
H A Dadf_gen4_hw_data.h9 #define ADF_BANK_INT_SRC_SEL_MASK 0x44UL
10 #define ADF_RING_CSR_RING_CONFIG 0x1000
11 #define ADF_RING_CSR_RING_LBASE 0x1040
12 #define ADF_RING_CSR_RING_UBASE 0x1080
13 #define ADF_RING_CSR_RING_HEAD 0x0C0
14 #define ADF_RING_CSR_RING_TAIL 0x100
15 #define ADF_RING_CSR_E_STAT 0x14C
16 #define ADF_RING_CSR_INT_FLAG 0x170
17 #define ADF_RING_CSR_INT_SRCSEL 0x174
18 #define ADF_RING_CSR_INT_COL_CTL 0x180
[all …]
H A Dadf_gen2_hw_data.h10 #define ADF_BANK_INT_SRC_SEL_MASK_0 0x4444444CUL
11 #define ADF_BANK_INT_SRC_SEL_MASK_X 0x44444444UL
12 #define ADF_RING_CSR_RING_CONFIG 0x000
13 #define ADF_RING_CSR_RING_LBASE 0x040
14 #define ADF_RING_CSR_RING_UBASE 0x080
15 #define ADF_RING_CSR_RING_HEAD 0x0C0
16 #define ADF_RING_CSR_RING_TAIL 0x100
17 #define ADF_RING_CSR_E_STAT 0x14C
18 #define ADF_RING_CSR_INT_FLAG 0x170
19 #define ADF_RING_CSR_INT_SRCSEL 0x174
[all …]
/freebsd/sys/dev/qat/qat_common/
H A Dadf_hw_arbiter.c18 #define ADF_ARB_REG_SIZE 0x4
19 #define ADF_ARB_WTR_SIZE 0x20
20 #define ADF_ARB_OFFSET 0x30000
21 #define ADF_ARB_REG_SLOT 0x1000
22 #define ADF_ARB_WTR_OFFSET 0x010
23 #define ADF_ARB_RO_EN_OFFSET 0x090
24 #define ADF_ARB_WQCFG_OFFSET 0x100
25 #define ADF_ARB_WRK_2_SER_MAP_OFFSET 0x180
26 #define ADF_ARB_RINGSRVARBEN_OFFSET 0x19C
53 struct resource *csr = accel_dev->transport->banks[0].csr_addr; in adf_init_arb()
[all …]
/freebsd/sys/dev/bhnd/cores/pcie2/
H A Dbhnd_pcie2_reg.h31 #define BHND_PCIE2_DMA64_TRANSLATION 0x8000000000000000 /**< PCIe-Gen2 DMA64 address translation */
32 #define BHND_PCIE2_DMA64_MASK 0xc000000000000000 /**< PCIe-Gen2 DMA64 translation mask */
38 #define BHND_PCIE2_CLK_CONTROL 0x000
40 #define BHND_PCIE2_RC_PM_CONTROL 0x004
41 #define BHND_PCIE2_RC_PM_STATUS 0x008
42 #define BHND_PCIE2_EP_PM_CONTROL 0x00C
43 #define BHND_PCIE2_EP_PM_STATUS 0x010
44 #define BHND_PCIE2_EP_LTR_CONTROL 0x014
45 #define BHND_PCIE2_EP_LTR_STATUS 0x018
46 #define BHND_PCIE2_EP_OBFF_STATUS 0x01C
[all …]
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Domap5-board-common.dtsi55 pinctrl-0 = <&wlan_pins>;
65 #phy-cells = <0>;
72 #phy-cells = <0>;
79 pinctrl-0 = <&tpd12s015_pins>;
85 #size-cells = <0>;
87 port@0 {
88 reg = <0>;
154 pinctrl-0 = <
161 OMAP5_IOPAD(0x1be, PIN_OUTPUT | MUX_MODE6) /* mcspi1_somi.gpio5_141 */
167 OMAP5_IOPAD(0x18
[all...]
H A Domap4-var-som-om44.dtsi15 reg = <0x80000000 0x40000000>; /* 1 GB */
38 pinctrl-0 = <
45 #phy-cells = <0>;
64 pinctrl-0 = <
70 OMAP4_IOPAD(0x19c, PIN_OUTPUT | MUX_MODE3) /* fref_clk2_out.gpio_182 */
71 OMAP4_IOPAD(0x1a0, PIN_INPUT | MUX_MODE0) /* sys_nirq2.sys_nirq2 */
77 OMAP4_IOPAD(0x090, PIN_INPUT | MUX_MODE3) /* gpmc_ncs4.gpio_101 (irq) */
78 OMAP4_IOPAD(0x092, PIN_OUTPUT | MUX_MODE3) /* gpmc_ncs5.gpio_102 (rst) */
84 OMAP4_IOPAD(0x140, PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_cts_rctx.uart3_cts_rctx */
85 OMAP4_IOPAD(0x142, PIN_OUTPUT | MUX_MODE0) /* uart3_rts_sd.uart3_rts_sd */
[all …]

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