18 #define ADF_ARB_REG_SIZE 0x4
19 #define ADF_ARB_WTR_SIZE 0x20
20 #define ADF_ARB_OFFSET 0x30000
21 #define ADF_ARB_REG_SLOT 0x1000
22 #define ADF_ARB_WTR_OFFSET 0x010
23 #define ADF_ARB_RO_EN_OFFSET 0x090
24 #define ADF_ARB_WQCFG_OFFSET 0x100
25 #define ADF_ARB_WRK_2_SER_MAP_OFFSET 0x180
26 #define ADF_ARB_RINGSRVARBEN_OFFSET 0x19C
53 	struct resource *csr = accel_dev->transport->banks[0].csr_addr;  in adf_init_arb()
54 	u32 arb_cfg = 0x1 << 31 | 0x4 << 4 | 0x1;  in adf_init_arb()
62 	for (arb = 0; arb < ADF_ARB_NUM; arb++)  in adf_init_arb()
65 	return 0;  in adf_init_arb()
73 	struct resource *csr = accel_dev->transport->banks[0].csr_addr;  in adf_init_gen2_arb()
87 	for (i = 0; i < hw_data->num_engines; i++)  in adf_init_gen2_arb()
93 	return 0;  in adf_init_gen2_arb()
149 	arbenable |= mask & 0xFF;  in adf_enable_ring_arb()
170 	arbenable &= ~mask & 0xFF;  in adf_disable_ring_arb()
187 	csr = accel_dev->transport->banks[0].csr_addr;  in adf_exit_arb()
192 	for (i = 0; i < ADF_ARB_NUM; i++)  in adf_exit_arb()
193 		WRITE_CSR_ARB_SARCONFIG(csr, info.arbiter_offset, i, 0);  in adf_exit_arb()
197 		for (i = 0; i < hw_data->num_engines; i++)  in adf_exit_arb()
202 						    0);  in adf_exit_arb()
206 	for (i = 0; i < GET_MAX_BANKS(accel_dev); i++)  in adf_exit_arb()
207 		csr_ops->write_csr_ring_srv_arb_en(csr, i, 0);  in adf_exit_arb()
220 	csr = accel_dev->transport->banks[0].csr_addr;  in adf_disable_arb()
224 	for (i = 0; i < GET_MAX_BANKS(accel_dev); i++)  in adf_disable_arb()
225 		csr_ops->write_csr_ring_srv_arb_en(csr, i, 0);  in adf_disable_arb()