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Searched +full:0 +full:x19004 (Results 1 – 13 of 13) sorted by relevance

/linux/drivers/clk/qcom/
H A Dgcc-sdx55.c33 { 249600000, 2000000000, 0 },
37 .offset = 0x0,
42 .enable_reg = 0x6d000,
43 .enable_mask = BIT(0),
56 { 0x0, 1 },
57 { 0x1, 2 },
58 { 0x3, 4 },
59 { 0x7, 8 },
64 .offset = 0x0,
81 .offset = 0x76000,
[all …]
H A Dgcc-sdm660.c51 .offset = 0x0,
54 .enable_reg = 0x52000,
55 .enable_mask = BIT(0),
81 .offset = 0x00000,
94 .offset = 0x1000,
97 .enable_reg = 0x52000,
124 .offset = 0x1000,
137 .offset = 0x77000,
140 .enable_reg = 0x52000,
154 .offset = 0x77000,
[all …]
H A Dgcc-sdx65.c36 .offset = 0x0,
39 .enable_reg = 0x6d000,
40 .enable_mask = BIT(0),
53 { 0x1, 2 },
58 .offset = 0x0,
73 { P_BI_TCXO, 0 },
91 { P_BI_TCXO, 0 },
105 { P_BI_TCXO, 0 },
119 { P_PCIE_PIPE_CLK, 0 },
129 { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
[all …]
H A Dgcc-msm8996.c49 .offset = 0x00000,
52 .enable_reg = 0x52000,
53 .enable_mask = BIT(0),
79 .offset = 0x00000,
94 .enable_reg = 0x5200c,
95 .enable_mask = BIT(0),
111 .enable_reg = 0x5200c,
126 .offset = 0x77000,
129 .enable_reg = 0x52000,
143 .offset = 0x77000,
[all …]
H A Dgcc-msm8998.c27 #define GCC_MMSS_MISC 0x0902C
28 #define GCC_GPU_MISC 0x71028
31 { 250000000, 2000000000, 0 },
36 .offset = 0x0,
41 .enable_reg = 0x52000,
42 .enable_mask = BIT(0),
55 .offset = 0x0,
68 .offset = 0x0,
81 .offset = 0x0,
94 .offset = 0x0,
[all …]
H A Dgcc-ipq4019.c112 .reg = 0x2e020,
120 .reg = 0x2f020,
171 return 0; in clk_cpu_div_set_rate()
214 { 384000000, P_XO, 0xd, 0, 0 },
215 { 413000000, P_XO, 0xc, 0, 0 },
216 { 448000000, P_XO, 0xb, 0, 0 },
217 { 488000000, P_XO, 0xa, 0, 0 },
218 { 512000000, P_XO, 0x9, 0, 0 },
219 { 537000000, P_XO, 0x8, 0, 0 },
220 { 565000000, P_XO, 0x7, 0, 0 },
[all …]
H A Dgcc-ipq5424.c53 .offset = 0x20000,
56 .enable_reg = 0xb000,
57 .enable_mask = BIT(0),
81 .offset = 0x21000,
84 .enable_reg = 0xb000,
96 { 0x1, 2 },
101 .offset = 0x21000,
116 .offset = 0x22000,
119 .enable_reg = 0xb000,
142 { P_XO, 0 },
[all …]
H A Dgcc-sm8650.c64 .offset = 0x0,
67 .enable_reg = 0x52020,
68 .enable_mask = BIT(0),
81 .offset = 0x0,
84 .enable_reg = 0x57020,
85 .enable_mask = BIT(0),
98 { 0x1, 2 },
103 .offset = 0x0,
120 .offset = 0x0,
137 .offset = 0x4000,
[all …]
H A Dgcc-x1e80100.c52 .offset = 0x0,
55 .enable_reg = 0x52030,
56 .enable_mask = BIT(0),
69 { 0x1, 2 },
74 .offset = 0x0,
91 .offset = 0x4000,
94 .enable_reg = 0x52030,
108 .offset = 0x7000,
111 .enable_reg = 0x52030,
125 .offset = 0x8000,
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dqcs404.dtsi24 #clock-cells = <0>;
30 #clock-cells = <0>;
37 #size-cells = <0>;
42 reg = <0x100>;
56 reg = <0x101>;
70 reg = <0x102>;
84 reg = <0x103>;
104 cpu_sleep_0: cpu-sleep-0 {
107 arm,psci-suspend-param = <0x40000003>;
161 reg = <0 0x80000000 0 0>;
[all …]
/linux/drivers/pinctrl/tegra/
H A Dpinctrl-tegra234.c1433 .mux_bit = 0, \
1447 #define drive_soc_gpio08_pb0 DRV_PINGROUP_ENTRY_Y(0x500c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1448 #define drive_soc_gpio36_pm5 DRV_PINGROUP_ENTRY_Y(0x10004, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1449 #define drive_soc_gpio53_pm6 DRV_PINGROUP_ENTRY_Y(0x1000c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1450 #define drive_soc_gpio55_pm4 DRV_PINGROUP_ENTRY_Y(0x10014, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1451 #define drive_soc_gpio38_pm7 DRV_PINGROUP_ENTRY_Y(0x1001c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1452 #define drive_soc_gpio39_pn1 DRV_PINGROUP_ENTRY_Y(0x10024, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1453 #define drive_soc_gpio40_pn2 DRV_PINGROUP_ENTRY_Y(0x1002c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1454 #define drive_dp_aux_ch0_hpd_pm0 DRV_PINGROUP_ENTRY_Y(0x10034, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1455 #define drive_dp_aux_ch1_hpd_pm1 DRV_PINGROUP_ENTRY_Y(0x1003c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/nbif/
H A Dnbif_6_3_1_offset.h28 // base address: 0x0
29 …IRQ_BRIDGE_CNTL 0x003e
33 // base address: 0x0
34 …BIF_CFG_DEV0_EPF0_VENDOR_ID 0x0000
35 …BIF_CFG_DEV0_EPF0_DEVICE_ID 0x0002
36 …BIF_CFG_DEV0_EPF0_COMMAND 0x0004
37 …BIF_CFG_DEV0_EPF0_STATUS 0x0006
38 …BIF_CFG_DEV0_EPF0_REVISION_ID 0x0008
39 …BIF_CFG_DEV0_EPF0_PROG_INTERFACE 0x0009
40 …BIF_CFG_DEV0_EPF0_SUB_CLASS 0x000a
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/nbio/
H A Dnbio_4_3_0_offset.h29 // base address: 0x0
30 …BIF_BX0_PCIE_INDEX 0x000c
31 …e regBIF_BX0_PCIE_INDEX_BASE_IDX 0
32 …BIF_BX0_PCIE_DATA 0x000d
33 …e regBIF_BX0_PCIE_DATA_BASE_IDX 0
34 …BIF_BX0_PCIE_INDEX2 0x000e
35 …e regBIF_BX0_PCIE_INDEX2_BASE_IDX 0
36 …BIF_BX0_PCIE_DATA2 0x000f
37 …e regBIF_BX0_PCIE_DATA2_BASE_IDX 0
38 …BIF_BX0_PCIE_INDEX_HI 0x0010
[all …]